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Journal articles on the topic 'Dispositifs CMOS et integration'

Author: Grafiati

Published: 7 July 2024

Last updated: 31 July 2025

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1

Yadav, Sachin, Pieter Cardinael, Ming Zhao, et al. "(Digital Presentation) Substrate Effects in GaN-on-Si Hemt Technology for RF FEM Applications." ECS Meeting Abstracts MA2022-02, no. 32 (2022): 1208. http://dx.doi.org/10.1149/ma2022-02321208mtgabs.

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Abstract : GaN-on-Si HEMTs are emerging as a viable candidate for front-end-of-module (FEM) implementation in 5G and beyond user equipment and small-cell applications [1][2]. This is because GaN HEMTs based power amplifiers and switches have high power handling capability as well as excellent switch figure-of-merit (Ron × Coff). The cost-effective integration of GaN HEMTs on silicon substrates not only benefit from standard CMOS back-end-of-the-line processing but also wafer-level integration with Si-CMOS [1][3], enabling complex functionality and better performance than the standalone counter

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Mori, Takahiro. "(Invited, Digital Presentation) Silicon Compatible Quantum Computers: Challenges in Devices, Integration, and Circuits." ECS Meeting Abstracts MA2022-01, no. 29 (2022): 1297. http://dx.doi.org/10.1149/ma2022-01291297mtgabs.

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Quantum computers have been attractive because they could realize large-scale and highly complicated calculations that conventional computers cannot solve within a finite time. The large-scale integration of qubits, which are the building block of quantum computers, is required to realize their practical application. Indeed, fault-tolerant quantum computers require the integration of one million qubits. Therefore, silicon qubits is a high-profile candidate because they have advanced process and miniaturization technologies developed with VLSI. In addition, silicon qubits are advantageous in op

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Andrieu, François. "(Invited) Advanced Non-Volatile-Memory Embedded with CMOS: Performance and Challenges." ECS Meeting Abstracts MA2025-01, no. 36 (2025): 1729. https://doi.org/10.1149/ma2025-01361729mtgabs.

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The microcontroller (MCU) market is progressively adopting alternatives to the NOR Flash as the embedded technology solutions below the 28nm node. Foundries already propose Magnetic Random Access Memory (MRAM) or oxide-based Resistive RAM (ReRAM) that are integrated in the Back-End-Of-the-Line (BEOL) above CMOS from 22nm node down to 12nm [1], [2], [3], [4], [5]. Another company offers the Phase-Change-Memory (PCM) as the resistive element at the 28nm and 18nm [6], [7]. The physics behind the switching mechanisms of these devices is different and so their comparative advantages/drawbacks. In t

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KHERRA, Nawal, Fouzia ROUAGHE, David D. PERRODIN, and Mobina RAHNAMA. "Students' Voices: Exploring Perceptions of Hybrid Language Learning." Langues & Cultures 5, no. 01 (2024): 250–63. http://dx.doi.org/10.62339/jlc.v5i01.242.

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Thispaper reflects on the gradual integration of hybrid systems in Algeria's university education context. Our contribution is intended as an analytical study of this new form of training provided for students studying for a degree in French language and literature. It uses action research results to understand current and actual hybrid teaching practices, learners' acquisition and engagement strategies in a new teaching situation, and their perceptions of this new teaching/learning mode. The results reflect excellent student perceptions of the media coverage and mediation of the hybrid system

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Chaudhary, Mayur, and Yu-Lun Chueh. "Dual Threshold and Memory Switching Induced By Conducting Filament Morphology in Ag/WSe₂ Based ECM Cell." ECS Meeting Abstracts MA2022-02, no. 36 (2022): 1334. http://dx.doi.org/10.1149/ma2022-02361334mtgabs.

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In recent years, two-dimensional (2D) materials-based RRAMs have gained high importance because of their thermal and mechanical stability, and better potentiation-depression controllability. 2D materials based conductive bridge random access memory (CBRAM) has been considered as promising approach for neuromorphic and image processing technology [1]. Despite much progress in CMOS technology, the growth and deposition technology of 2D materials for semiconductor integrated circuit are much complex and is generally available at wafer scale [2]. In addition, high growth temperature for high quali

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Ernst, Thomas, Frank Fournel, Lucie Le Van-Jodin, et al. "(Invited) Emerging Paths for Heterogeneous 3D Integration." ECS Meeting Abstracts MA2025-01, no. 36 (2025): 1723. https://doi.org/10.1149/ma2025-01361723mtgabs.

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Over the past two decades, 3D techniques combined with heterogeneous integration, combining different functions and materials, have emerged as a key enabler for overcoming the physical and scaling limits of traditional 2D integration. These approaches are now expanding across multiple domains, including CMOS, memories, photonics, imagers, and RF systems, with the aim of delivering next-generation integrated systems for advanced computing (AI), analog/RF, and imaging applications. In this presentation, we will explore the fundamental techniques, recent advancements, and some challenges associat

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Deprat, Fabien, Jeremy Vives, Alexis Gauthier, et al. "(Invited) Epitaxial Process Development and Challenges for Advanced SiGe BiCMOS." ECS Meeting Abstracts MA2024-02, no. 32 (2024): 2318. https://doi.org/10.1149/ma2024-02322318mtgabs.

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Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) are used daily, mainly in the communication field. Their co-integration with Complementary Metal Oxide Semiconductor (CMOS) technology, i.e. BiCMOS, enables versatile microchips that combine analog, radio-frequency and digital functions. Applications that drive the development of BiCMOS technologies today are Low Earth Orbit (LEO) satellite communications, for which the minimum noise figure of SiGe HBT (NFMIN) between 10 and 30 GHz is one of the most critical figures of merit on the receiver side. It is expected that BiCMOS wil

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Nguyen, Ngoc-Anh, Olivier Schneegans, Jouhaiz Rouchou, et al. "(G02 Best Presentation Award Winner) Elaboration and Characterization of CMOS Compatible, Pico-Joule Energy Consumption, Electrochemical Synaptic Transistors for Neuromorphic Computing." ECS Meeting Abstracts MA2022-01, no. 29 (2022): 1293. http://dx.doi.org/10.1149/ma2022-01291293mtgabs.

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Non-Von Neumann computing application constituted by artificial synapses based on electrochemical random-access memory (ECRAM) has aroused tremendous attention owing to its capability to perform parallel operations, thus reducing the cost of time and energy spent [1-3]. Existing ECRAM synapses comprise two-terminal memristors and three-terminal synaptic transistors (SynT). While low cost, scalability, and high density are the highlights for memristors, their nonlinear, asymmetric state modulation, high ON current withdrawal, and sneak path in crossbar array integration prevent them from becomi

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Pekarik, Jack, Vibhor Jain, Crystal Kenney, et al. "Challenges for Sige Bicmos in Advanced-Node SOI." ECS Meeting Abstracts MA2022-02, no. 32 (2022): 1196. http://dx.doi.org/10.1149/ma2022-02321196mtgabs.

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D-band (110-170GHz) spectrum is gaining attention for various applications, including 6G mm-Wave, sub-THz sensing, and radar. These systems require lattice spacing for antenna elements at sub-1mm and a very low loss signal path from antenna to integrated chip. A highly efficient front-end in a very small form factor will be required for these systems. This drives the requirement for a monolithically integrated high-gain, high-efficiency front-end that also leverages the benefits of a high-speed / high-density digital CMOS. Silicon germanium (SiGe) heterojunction bipolar transistors (HBT) integ

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Daszko, Sebastian, Carsten Richter, Jens Martin, et al. "Transfer Printable Single-Crystalline Coupons for III-V on Si Integration." ECS Meeting Abstracts MA2022-02, no. 17 (2022): 863. http://dx.doi.org/10.1149/ma2022-0217863mtgabs.

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The next-generation internet (6G) requires highly functional devices that e.g. realize frequencies in the THz range for higher data rates and lower latencies. Those requirements exceed the physical limits of established CMOS technologies based on silicon (Si). Hence, there is demand for other semiconductor materials with superior electronic and optical properties that complement Si. One of the key candidates is the III-V compound semiconductor, indium phosphide (InP). Due to its high electron mobility and direct band gap, InP-based devices allow access to frequencies >100 GHz and operate at

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Lamy, Yann, Florian Dupont, Guillaume Rodriguez, et al. "(Invited) Lithium-Based Components Integrated on Silicon: Disruptive, Promising and Credible Solutions for 5G & Beyond." ECS Meeting Abstracts MA2022-01, no. 29 (2022): 1286. http://dx.doi.org/10.1149/ma2022-01291286mtgabs.

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Following a trend similar to Moore’s low which prevailed for decades for active circuits, RF integrated passive components have reinvented themselves over the years in order to sustain continuous performance and size requirements. Their roadmap is still unrolling, thanks to a wide variety of new materials integration: high-k dielectrics for capacitors[1] ,[2] , magnetic material for inductors [3], aluminium nitride[4] (now scandium doped) for RF filters, or more recently phase-change materials for RF switches[5]. In the last few years, RF integrated passives built upon Lithium-based materials

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Kanyandekwe, Joël, Matthias Bauer, Tanguy Marion, et al. "Very Low Temperature Tensile and Selective Si:P Epitaxy for Advanced CMOS Devices." ECS Meeting Abstracts MA2022-02, no. 32 (2022): 1190. http://dx.doi.org/10.1149/ma2022-02321190mtgabs.

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Nowadays, “more Moore” and “more than Moore” device architectures are becoming more and more complex. In CEA-Leti, we work on the “CoolCubeTM” 3D sequential integration which is based on the stacking of FDSOI devices [1]. We present solutions, at T<500°C, for the integration of SiP Raised Sources & Drains (RSD) in the upper devices without degrading the electrical performances of the bottom ones. We also target a lowering of the RSD resistance and an increase of the electron mobility in the channel of NMOS devices thanks to tensile strain [2]. Such a know-how will be useful to minimize

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Xu, Xiaopeng, Xi-Wei Lin, Youxin Gao, and Soren Smidstrup. "(Invited) 3DIC Hierarchical Thermal and Mechanical Analysis with Continuum and Atomistic Modeling." ECS Meeting Abstracts MA2022-02, no. 17 (2022): 845. http://dx.doi.org/10.1149/ma2022-0217845mtgabs.

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3D IC heterogeneous integration technologies employ numerous materials with widely varying thermal and mechanical properties and distinct deformation behaviors. During 3D integration processes, the constituent materials undergo various thermal cycles. Because of thermal expansion coefficient mismatch, the materials are essentially subject to mechanical loadings for these thermal ramps. The resulting chip, package, and board interactions lead to 3D stack warpage, silicon mobility variation, and material damage. Under operation conditions, heat can be trapped between insulation layers and leads

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Rosseel, Erik, Clement Porret, Thomas Dursap, et al. "Source/Drain Epitaxy for Nanosheet-Based CFET Devices." ECS Meeting Abstracts MA2024-02, no. 32 (2024): 2298. https://doi.org/10.1149/ma2024-02322298mtgabs.

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The complementary field-effect transistor (CFET) is an attractive device architecture for beyond 1 nm CMOS technology nodes where n- and p-MOS nanosheet devices are placed on top of each other [1-3]. In the present paper, we discuss the progress in source/drain (SD) epitaxy development for nanosheet and monolithic CFET (mCFET) devices. A schematic cross-section of a mCFET stack is shown in Figure 1, in the case of a Metal-Diffusion-first (MD-first) integration scheme [3]. In this case, the p-MOS device is made first, leading to a bottom SiGe:B (B-SiGe:B) SD epi layer. The n-MOS device with top

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Quay, Ruediger, Arnulf Leuther, Sebastien Chartier, Laurenz John, and Axel Tessmann. "(Invited) III-V Integration on Silicon for Resource-Efficient Sensor-Technology." ECS Meeting Abstracts MA2023-01, no. 33 (2023): 1853. http://dx.doi.org/10.1149/ma2023-01331853mtgabs.

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This work deals with the wafer-level integration of advanced group III-V devices and integrated circuits on silicon substrate for RF-sensor integration, such as radar functions a very high frequencies beyond 300 GHz [1]. The aim is to achieve both performance improvements on device level, co-integration with digital functions, and advanced integration to achieve a greener usage of material critical to the environment. Submillimeter-Wave frequency bands beyond 300 GHz allow for broadband transmit and receive windows, serviceable to both communications and radar-based applications—increasing dat

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Fournel, Frank, Loic Sanchez, Brigitte Montmayeul, et al. "(Invited) Optoelectronic and 3D Applications with Die to Wafer Direct Bonding: From Mechanisms to Applications." ECS Meeting Abstracts MA2022-02, no. 17 (2022): 853. http://dx.doi.org/10.1149/ma2022-0217853mtgabs.

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Abstract—Wafer direct bonding is now a widely spread technique in microelectronics. However in many interesting applications, wafer bonding is not adapted due to size, material or technological node differences. Die to wafer bonding could then lead to innovative devices. After explaining some specific fundamental mechanisms, III/V die to wafer bonding and copper hybrid bonding will be presented for photonic and 3D applications. Introduction SOI or backside image sensors’ fabrication in mass production, for instance, calls upon direct wafer bonding that has become a standard technology availabl

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Offrein, Bert Jan. "(Invited) Analog Signal Processing Technologies for Power-Efficient Neural Network Inference and Training." ECS Meeting Abstracts MA2025-01, no. 31 (2025): 1590. https://doi.org/10.1149/ma2025-01311590mtgabs.

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Artificial Intelligence (AI) is now widely available in society and business operations. To enhance the performance and functionality, the neural network architectures behind AI are exponentially increasing in size and have reached a trillion parameters [1]. This puts enormous pressure on the hardware applied to train and infer such networks with respect to the compute, energy and cost. This challenge is addressed by scaling AI datacenter systems, i.e. the compute performance, memory capacity, connectivity bandwidth at all levels and the size [2]. Power-efficiency enhancements are obtained thr

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Chien, Jun-Chau. "(Invited) Continuous Monitoring of Small Molecules Using Electrochemical Aptamer-Based Biosensors with CMOS Electronics." ECS Meeting Abstracts MA2024-01, no. 33 (2024): 1617. http://dx.doi.org/10.1149/ma2024-01331617mtgabs.

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The ability to continuously monitor specific “molecules” over a long period of time can provide fundamentally new insights into disease dynamics and the transition from a healthy state and lead to the design of next-generation screening and detection tools. However, currently only a few biomolecules, such as glucose, oxygen, and dopamine, can be continuously and real-time monitored with significant relevance to chronic disease management. The prevalent glucose sensor uses glucose oxidase (GOx), an enzyme designed to oxidize glucose persistently in its proximity, producing an electrochemical cu

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Gong, Xiao. "(Invited) BEOL-Compatible Oxide Semiconductor Logic and Memory Devices." ECS Meeting Abstracts MA2023-02, no. 30 (2023): 1524. http://dx.doi.org/10.1149/ma2023-02301524mtgabs.

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3D monolithic integration of logic and memory devices has emerged as one of the key enablers for next-generation electronic devices to address the ever-increasing demand for higher integration density, better performance and energy efficiency. BEOL-compatible oxide semiconductors show great potential to revolutionize the field thanks to their unique properties [1]. We present our recent advancement related to BEOL-compatible oxide semiconductors for logic and memory applications. The digital-etch-enabled nanowire transistors and α-IGZO-based eDRAM will first be discussed, followed by the ferro

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Azi Kammoun, Safia, and Jérôme Palazzolo. "L’espoir comme ressource psychologique pour le bien-être des étudiants : Analyse de contenu de l’apport de la psychologie positive." European Scientific Journal, ESJ 20, no. 29 (2024): 43. http://dx.doi.org/10.19044/esj.2024.v20n29p43.

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Introduction : La santé mentale des étudiants est préoccupante. La littérature scientifique affirme le mal-être des étudiants qui se traduit par une détresse psychologique. Cette détresse se manifeste par des troubles de l’humeur, du sommeil, de l’alimentation, une dépression, de l’anxiété, un stress chronique. L’accès au monde universitaire est une réalité stressante avec un lot de défis et de grands changements déroutants. L’étudiant doit mobiliser ses ressources psychologiques telles-que l’estime de soi, l’optimisme, l’espoir etc., pour s’ajuster à ce nouveau monde. Notre article a pour obj

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O'Sullivan, Eugene J. "(Invited) Electrochemistry: Adventures in Metallization." ECS Meeting Abstracts MA2022-02, no. 30 (2022): 1081. http://dx.doi.org/10.1149/ma2022-02301081mtgabs.

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Microelectronics has benefited enormously from electrochemistry, particularly in metallization. Metallizing through-holes in multilevel printed circuit boards was a major, successful application of electroless Cu (1). Electroless Co-based magnetic films deposited on non-magnetic electroless nickel films on rigid aluminum disks propelled the magnetic storage industry for years. A decade or more ago, it looked as if electroless Co(W)(P) was the ideal candidate to replace PVD Ta-based liners for CMOS back-end-of-line (BEOL) builds (2). Its cost undid it, however, despite meeting selectivity, diff

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Cheema, Suraj. "(Invited) Atomic-Scale Design of Advanced Transistors Via Ultrathin Negative Capacitance Gate Stacks." ECS Meeting Abstracts MA2024-02, no. 32 (2024): 2312. https://doi.org/10.1149/ma2024-02322312mtgabs.

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Negative capacitance [1,2] has emerged as a promising solution to overcome fundamental energy-efficiency limits in conventional electronics, in which internal ferroelectric order within the gate stack of a field-effect transistor can enable low-power operation. Thus far, claims of negative capacitance have been primarily demonstrated in perovskite-structure thick films or through misleading “S-curve” transient experiments in fluorite-structure thick films. However, integration into advanced semiconductor technology nodes will require stabilization at the ultrathin regime and evidence of capaci

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Reichmann, Felix, Alberto Mistroni, Yuji Yamamoto, et al. "(Invited) Advancing Si Spin Qubit Research: Process Integration of Hall Bar FETs on Si/SiGe in a 200mm BiCMOS Pilot Line." ECS Meeting Abstracts MA2024-02, no. 32 (2024): 2319. https://doi.org/10.1149/ma2024-02322319mtgabs.

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A fault-tolerant universal quantum computer will require millions of physical qubits, necessitating a highly scalable qubit platform. Si-based spin qubits emerged as a leading candidate, boasting high fidelities, straightforward tunability, and compatibility with the CMOS fabrication process. The progress in this qubit platform in the last two years was remarkable: a 6-qubit quantum processor [1], qubits manufactured in a 300 mm foundry [2] and electron shuttling over long distances [3,4] have been demonstrated. The technological basis of Si spin qubits are electrostatically defined quantum do

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Rosseel, Erik, Clement Porret, Andriy Yakovitch Hikavyy, et al. "(Digital Presentation) Properties of Selectively Grown Si:P Layers below 500°C for Use in Stacked Nanosheet Devices." ECS Meeting Abstracts MA2022-02, no. 32 (2022): 1188. http://dx.doi.org/10.1149/ma2022-02321188mtgabs.

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With the introduction of novel stacked CMOS transistor integration schemes such as sequential 3D and CFETs [1,2], there is an increasing need for highly active source/drain layers with a low overall thermal budget. For some integration schemes, processing temperatures below ~ 525°C are desired [3] and in most cases, the contacts need to be formed on the {110} surfaces of exposed Si nanosheets. In this paper, we report on selectively grown Si:P layers below 500°C targeting application in stacked nanosheet-based devices. In contrast to conventional approaches where selectivity is obtained at low

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Lee, Yao-Jen, Shu-Wei Chang, Wen-Hsi Lee, and Yeong-Her Wang. "(Invited, Digital Presentation) Heterogeneous IGZO/Si CFET Monolithic 3D Integration." ECS Meeting Abstracts MA2022-02, no. 35 (2022): 1289. http://dx.doi.org/10.1149/ma2022-02351289mtgabs.

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Monolithic 3D-IC is one of the solutions to relieve Moore’s law with vertically integrating circuits for sub-1nm technology nodes. Therefore, thin-film transistors (TFTs) play an important role in this trend because of their low fabrication temperature to realize back-end circuits. On the other hand, 3D integrating filter, duplexer, switch, and so on is necessary as antennas array requirements increase in 5G or beyond. Consequently, it is foreseeable to adopt TFTs to implement radio frequency (RF) devices. Fig. 1 shows the schematic ideal 3D SoC for sub-1nm technology. Our previous research tr

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Bogdanowicz, Janusz, Mohamed Saib, Matteo Beggiato, et al. "(Invited) Metrology Along the Gate-All-Around Logic Roadmap: From Nanosheet to Complementary Field-Effect Transistors." ECS Meeting Abstracts MA2024-02, no. 32 (2024): 2302. https://doi.org/10.1149/ma2024-02322302mtgabs.

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For over 50 years, improving the functionality per unit area has been the driving force of the semiconductor industry. Since the advent of fin field effect transistors (FETs), however, this has come at the expense of an increasingly complex device architecture. This is particularly true today as the industry is transitioning from finFETs to nanosheet (NSH) FETs. The integration of the latter devices indeed introduces the use e.g. of a modified substrate with an epitaxial SiGe/Si superlattice, of lateral etching and of size-constrained and buried gate stacks. Novel metrology concepts are theref

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Liu, Po-Tsun, Chih-Chieh Hsu, Shu-Wei Chang, and Yu Chuan Chiu. "(Invited) Study on Rram Properties Using Resistive Switching Layer with ZnO Nanostructure." ECS Meeting Abstracts MA2024-02, no. 34 (2024): 2419. https://doi.org/10.1149/ma2024-02342419mtgabs.

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Zinc oxide (ZnO) is an amorphous oxide semiconductor (AOS) material valued for its high carrier mobility, transparency to visible light, and low-temperature manufacturing process compared to silicon-based semiconductors. These desired features make ZnO-based AOSs widely popular as the channel layer in TFTs and as key dielectric layers in electronic devices like light sensors, gas detectors, resistive random-access memory (RRAM), and more. Among them, Conductive Bridge Random Access Memory (CBRAM) with a dielectric switching layer sandwiched between the electrochemically active metal (Ag, Cu) t

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Ringbeck, T., T. Möller, and B. Hagebeuker. "Multidimensional measurement by using 3-D PMD sensors." Advances in Radio Science 5 (June 12, 2007): 135–46. http://dx.doi.org/10.5194/ars-5-135-2007.

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Abstract. Optical Time-of-Flight measurement gives the possibility to enhance 2-D sensors by adding a third dimension using the PMD principle. Various applications in the automotive (e.g. pedestrian safety), industrial, robotics and multimedia fields require robust three-dimensional data (Schwarte et al., 2000). These applications, however, all have different requirements in terms of resolution, speed, distance and target characteristics. PMDTechnologies has developed 3-D sensors based on standard CMOS processes that can provide an optimized solution for a wide field of applications combined w

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Poempool, Thanavorn, Johannes Aberl, Marco Clementi, et al. "Telecom Photon Emitters Based on Isolated Group-IV Quantum Dots Deterministically Coupled to High-Q Photonic Crystal Cavities." ECS Meeting Abstracts MA2024-01, no. 22 (2024): 1318. http://dx.doi.org/10.1149/ma2024-01221318mtgabs.

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The realization of scalable telecom light emitters that can be monolithically implemented into large-scale Si integration technology has been a driving factor in the field of Si photonics for the last decades. Applications are envisioned in the short and medium-range data transfer and for realizing scalable, Si-based quantum information technology. For the latter, CMOS-compatible sources that can be controlled on the single photon level are needed. In solid-state materials, group-III-V quantum dots (QDs) are one of the leading platforms for realizing single photon emitters of excellent optical

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Renaud, Pablo, Karine Abadie, Frank Fournel, Christophe Dubarry, Floriane Baudin, and Aurelie Tauzin. "SAB-Enabled Room Temperature Hybrid Bonding." ECS Meeting Abstracts MA2023-02, no. 33 (2023): 1594. http://dx.doi.org/10.1149/ma2023-02331594mtgabs.

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3D integration is gaining more and more interest for a large panel of applications including CMOS Image Sensor, High Performance Computing, DRAM including HBM stacks and display. Image sensors based on hybrid bonding 3D stacking are the state-of-the-art in imaging applications[1]. Highest integration densities with micron-size pixels are achieved using copper-oxide hybrid bonding in advanced CMOS Image Sensor (CIS) processes. Recently, functional imagers with sub 1 µm pitch of hybrid bonding interconnection have shown great performances in term of reliability [2]. Hybrid bonding low temperatur

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Nawito, M., H. Richter, A. Stett, and J. N. Burghartz. "A programmable energy efficient readout chip for a multiparameter highly integrated implantable biosensor system." Advances in Radio Science 13 (November 3, 2015): 103–8. http://dx.doi.org/10.5194/ars-13-103-2015.

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Abstract. In this work an Application Specific Integrated Circuit (ASIC) for an implantable electrochemical biosensor system (SMART implant, Stett et al., 2014) is presented. The ASIC drives the measurement electrodes and performs amperometric measurements for determining the oxygen concentration, potentiometric measurements for evaluating the pH-level as well as temperature measurements. A 10-bit pipeline analog to digital (ADC) is used to digitize the acquired analog samples and is implemented as a single stage to reduce power consumption and chip area. For pH measurements, an offset subtrac

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Loo, Roger, Anjani Akula, Yosuke Shimura, et al. "(Keynote) Epitaxial Si/SiGe Multi-Stacks: From Stacked Nano-Sheet to Fork-Sheet and CFET Devices." ECS Meeting Abstracts MA2024-02, no. 32 (2024): 2291. https://doi.org/10.1149/ma2024-02322291mtgabs.

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The scaling evolution from stacked nano-sheet devices to fork-sheet devices and CFET architectures went together with increased complexities of the epitaxial growth schemes. This is valid for both the Si/SiGe multi-layers which define the thickness of the nano-sheet channels as well as the vertical distance between individual nano-sheets and also for the epitaxially grown source/drain (SD) layers which require a continuous increase in active doping concentration and a reduction in thermal budget without compromising material quality. Fork-sheet transistors are lateral nano-sheet devices with a

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Moustakas, Konstantinos, Leonardo Cancellara, Niccolo Pezzato, et al. "Towards Vertical Gate-All-Around Fefets: Integrating Ferroelectric 10nm Hzo for Scalable Logic-in-Memory Applications." ECS Meeting Abstracts MA2025-01, no. 31 (2025): 1591. https://doi.org/10.1149/ma2025-01311591mtgabs.

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The rapid growth of semiconductor technology over the past decades has highlighted the need to overcome the limitations of traditional computer designs. This conventional architecture faces challenges related to data transfer, caused by the separation of memory and processing units, commonly referred to as the Von Neumann bottleneck. To address this issue, the integration of non-volatility into processing devices has been explored, enabling data storage and logic operations to be performed in the same location-a concept known as Logic-in-Memory architectures. A promising solution in this direc

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Bhattacharyya, Paramita, Brahim Ahammou, Fahmida Azmi, Rafael Kleiman, and Peter Mascher. "Design and Fabrication of Multiple-Color-Generating Thin-Film Optical Filters for Photovoltaic Applications." ECS Meeting Abstracts MA2022-01, no. 19 (2022): 1064. http://dx.doi.org/10.1149/ma2022-01191064mtgabs.

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The use of electric vehicles (EVs) can reduce greenhouse gas emissions, air pollution, dependency on fossil fuels, and their adverse health effects on humans. But, we can only utilize the full environmental benefits of EVs when they are charged with renewable energy sources with zero or low carbon emissions. As a solution, Mobarak et al. [1] suggested integrating low-cost, flexible, and thin-film copper indium gallium selenide (CIGS) solar cells directly onto the steel of all the upward-facing body parts of the vehicles. But, this integration of solar cells comes with an aesthetic drawback. Pr

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Hermann, Sascha, Simon Böttger, and Martin Hartmann. "(Invited) Suspended 1D/2D Nanomaterials: Progress on a Waferlevel Technology and Applications." ECS Meeting Abstracts MA2023-02, no. 30 (2023): 1530. http://dx.doi.org/10.1149/ma2023-02301530mtgabs.

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The use of 1D and 2D nanomaterials in emerging electronics and sensor technologies is becoming increasingly important due to their unique properties. Here we would like to highlight a scalable process for suspended nanomaterials that provides additional scope for the development of device properties that can be used in advanced concepts ranging from molecular sensing to quantum applications [1]. For example those applications benefit from arrangements as CNT-based nanoresonators with extremely high quality factors [2] usable for quantum bits with long coherence time [3] or suspended sensing na

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Finnegan, Patrick Sean, Sangheon Oh, Brian Zutter, et al. "Vanadium Oxide Device with Tunable Oxygen Vacancy Concentration for Neuromorphic Computing." ECS Meeting Abstracts MA2024-02, no. 20 (2024): 1816. https://doi.org/10.1149/ma2024-02201816mtgabs.

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Analog, non-volatile memories that can enable in-memory data processing are attractive for exploring non-von-Neumann architectures to realize substantially more efficient computing for AI applications. Among the various device concepts, NVMs based on tuning of point defects via insertion of ions such as alkali metals, protons, or oxygen vacancies are attractive due to the ability to finely tune the electronic conductivity by controlling the defect concentration. Previously, oxygen vacancy concentration in vanadium oxide (VO2-x) has been linked to electronic conductivity and the insulator-to-me

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Veloso, Anabela, Geert Eneman, Eddy Simoen, et al. "(Invited, Digital Presentation) Innovations in Transistor Architecture and Device Connectivity Options for Advanced Logic Scaling." ECS Meeting Abstracts MA2022-01, no. 19 (2022): 1059. http://dx.doi.org/10.1149/ma2022-01191059mtgabs.

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CMOS scaling has been the backbone of the overall logic roadmap for decades, but it is reaching its physical limits while also imposing ever more constraining design restrictions. This has triggered a critical need for new device architectures and integration concepts to be able to continue delivering profitable node-to-node scaling gains and to help preserve the industry’s power-performance-area-cost metrics. From the transistor’s perspective, vertically stacked lateral nanosheet (NS) FETs, with a gate-all-around (GAA) configuration, are widely regarded as the most promising and mature option

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Zeinati, Aseel, Durgamadhab Misra, Bhavana Padala, et al. "A Comparative Study of H-Plasma Treated ZrO₂ and HfO₂ RRAM Devices for Low Power in-Memory Computing." ECS Meeting Abstracts MA2025-01, no. 63 (2025): 3073. https://doi.org/10.1149/ma2025-01633073mtgabs.

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The floating gate flash memories are facing their physical and scaling limitation, highlighting the need of the resistive random-access memory (RRAM) as a promising solution for in-memory computing1. Transition metal oxide (TMOs) are utilized as switching layer for RRAM devices due to their low power consumption, high density integration capability, high switching speed (<10ns), good stability, endurance, retention and their compatibility with the existing CMOS technology2-6. ZrO2 and HfO2 are two of the mature TMOs to be used as switching layer due to their high specific heat and thermal c

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Vinuesa, Guillermo, Hector Garcia, Salvador Duenas, et al. "Effect of the Temperature on the Performance and Dynamic Behavior of HfO₂-Based Rram Devices." ECS Meeting Abstracts MA2024-01, no. 21 (2024): 1297. http://dx.doi.org/10.1149/ma2024-01211297mtgabs.

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Over the past decades, the demand for semiconductor memory devices has been steadily increasing, and is currently experiencing an unprecedented boost due to the development and expansion of artificial intelligence. Among emerging high-density non-volatile memories, resistive random-access memory (RRAM) is one of the best recourses for all kind of applications, such as neuromorphic computing or hardware security [1]. Although many materials have been evaluated for RRAM development, some of them with excellent results, HfO2 is one of the established materials in CMOS domain due to its compatibil

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Ballabio, Andrea, Andrea De Iacovo, Jacopo Frigerio, Andrea Fabbri, Giovanni Isella, and Lorenzo Colace. "Electrically Tunable Ge/Si VIS-Swir Photodetector." ECS Meeting Abstracts MA2022-02, no. 32 (2022): 1171. http://dx.doi.org/10.1149/ma2022-02321171mtgabs.

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Ge-on-Si photodiodes have been firstly reported more than twenty years ago opening the way for the integration of IR photodetectors on Si. A tremendous development has been done, moving from vertically illuminated, stand-alone devices, to waveguide integrated arrays of photodetectors and CMOS integrated imagers. Usually, the Ge epilayer act as the absorbing material for the NIR radiation, while Si acts only as a substrate. Here we report on a dual-band Ge-on-Si photodetector where light detection can take place both within the Ge epilayer and the underlying Si substrate: the device responsivit

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Cressler, John D. "Silicon-Germanium Electronics and Photonics for Space Systems." ECS Meeting Abstracts MA2022-02, no. 32 (2022): 1199. http://dx.doi.org/10.1149/ma2022-02321199mtgabs.

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Space has been aptly called the “final frontier” (thank you, Star Trek!). The application needs of the global space and aerospace communities are predictably many and varied, ranging from a diverse set of communications and imaging satellites, to the GPS constellation, to microwave and millimeter-wave (mmW) remote sensing to support weather forecasting and climate science, to exploration of other worlds, which include: the mighty James Webb Space Telescope (probing the origins of the universe), the shadowed polar craters of the Moon (the search for water ice), Mars surface (colonization?), and

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Azmi, Fahmida, Paramita Bhattacharyya, and Peter Mascher. "Optical Properties of Europium-Doped Silicon-Based Thin Films." ECS Meeting Abstracts MA2024-01, no. 22 (2024): 1326. http://dx.doi.org/10.1149/ma2024-01221326mtgabs.

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The integration of a silicon-based light emitter into existing CMOS technology has long been intriguing due to its optoelectronic compatibility with microelectronics [1]. However, the indirect band gap nature of bulk silicon has hindered its effectiveness as a light emitter. In addressing this limitation, rare earth ions have emerged as significantly interesting candidates owing to their unique optical and electronic properties. Rare earth-doped silicon structures have earned special attention as they exhibit sharp light emission in different spectral regions [2] . This notable feature is attr

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Takenaka, Mitsuru, Ziqiang Zhao, Chong Pei Ho, et al. "(Digital Presentation) Ge-on-insulator Platform for Mid-infrared Photonic Integrated Circuits." ECS Meeting Abstracts MA2022-02, no. 32 (2022): 1175. http://dx.doi.org/10.1149/ma2022-02321175mtgabs.

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Since mid-infrared (MIR) wavelengths have a great potential for optical communication, sensing, and quantum information, Si-based MIR photonic integrated circuits (PICs) have been developed by leveraging Si photonics technology for near-infrared wavelengths. However, the transparency wavelength window of Si is from 1.2 µm to 8 µm, limiting the available wavelengths in the MIR spectrum. Ge is emerging as a waveguide material to overcome this difficulty because Ge is transparent in the entire MIR spectrum. A Ge-on-Si waveguide is one of the promising platform for a MIR PICs. We have also propose

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Margetis, Joe, Nico Breil, John Tolle, Abhishek Dube, and Saurabh Chopra. "Low Temperature Epitaxy Processes for Contact Resistivity Reduction." ECS Meeting Abstracts MA2024-02, no. 33 (2024): 5119. https://doi.org/10.1149/ma2024-02335119mtgabs.

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With the continued scaling of CMOS logic devices the contact resistivity at the semiconductor/silicide interface has become a limiting factor for device performance. High active dopant concentration at this interface is critical to realizing low contact resistance, and ion implantation is conventionally used to achieve this. We have previously reported [1] that contact cavity shaping to increase the contact area can be used to decrease the contact resistivity. This etching process produces convex (111) facets from a (100) starting surface in the source-drain volume, thereby increasing the cont

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Touratier-Muller, Nathalie, Karim Machat, and Jacques Jaussaud. "Government measures to reduce CO2 emissions in freight transport: What are the impacts on SMEs?" Les Cahiers Scientifiques du Transport - Scientific Papers in Transportation Unlabeled volume (April 18, 2023). http://dx.doi.org/10.46298/cst-11043.

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This article explores the behaviour of small- and medium-sized enterprises (SMEs) regarding mandatory and voluntary measures established by the French government to reduce carbon dioxide (CO2) emissions generated by freight transport operations. Through semi-structured interviews with fourteen SMEs (five shippers, eight carriers and a consultant) located throughout France, this research examines the integration of sustainable development into organizational and decision-making practices since the introduction of these programmes on the French territory. Our qualitative study suggests that acti

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Allaire, Stéphane. "Soutenir le cheminement de stage d’apprentis enseignants au secondaire par un environnement d’apprentissage hybride / Supporting the advancement of student-teachers in their practica with the use of a hybrid learning environment." Canadian Journal of Learning and Technology / La revue canadienne de l’apprentissage et de la technologie 34, no. 2 (2009). http://dx.doi.org/10.21432/t2p307.

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Résumé : Dans un contexte de pratiques éducatives en renouvellement, la recherche participative étudie l’apport d’un environnement d’apprentissage hybride pour l’analyse réflexive de stagiaires en enseignement secondaire. Des analyses qualitatives et quantitatives descriptives illustrent le potentiel des dispositifs mis en place pour soutenir l’intégration à un contexte de stage innovateur, une réflexivité diversifiée et la coélaboration de connaissances. Abstract : In the context of evolving educational practices, participatory research is used to study the contribution of a hybrid learning e

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Anas, Sofi, Laafou Mohamed, Janati-Idriss Rachid, and Madrane Mourad. "L'APPRENTISSAGE AVEC DES DISPOSITIFS MOBILES DANS L'ENSEIGNEMENT SUPERIEUR AU MAROC: CAS DE DUT GBABB DE L'ENS TETOUAN / LEARNING WITH MOBILE DEVICES IN HIGHER EDUCATION IN MOROCCO: CASE OF DUT GBABB OF ENS TETOUAN." European Journal of Education Studies 3, no. 10 (2017). https://doi.org/10.5281/zenodo.898199.

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Dans cet article, nous nous intéressons à l’intégration des dispositifs mobiles dans l’enseignement supérieur au marocain. Nous proposons une solution basée sur l’apprentissage mobile est particulièrement dans les travaux pratique de biologie de la filière DUT GBABB (Diplômes Universitaires de Technologie Génie Biologique: Analyses Biologiques et Biochimiques). Nous nous proposons cette méthode à cause de problème de la non-disponibilité des matériels chez les étudiants qui

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Soumaya, Jdidi. "INCLUSION SOCIALE DES FEMMES EN SITUATION DE HANDICAP AU MAROC." European Journal of Social Sciences Studies 11, no. 2 (2025). https://doi.org/10.46827/ejsss.v11i2.1973.

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<p>L’inclusion sociale des femmes en situation de handicap au Maroc s’est progressivement imposée comme une priorité politique et institutionnelle. Les efforts réalisés en matière d’ancrage normatif et législatifs sont indéniables et témoignent d’une volonté d’ancrer l’égalité et la solidarité dans le projet national. Toutefois, des inégalités structurelles, des pratiques discriminatoires persistantes et un déficit de mise en œuvre freinent encore l’intégration pleine et entière de cette catégorie. L’inclusion sociale des femmes en situation de handicap ne peut se réaliser pleinement san

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Letertre, Fabrice Jerome. "Formation of III-V Semiconductor Engineered Substrates Using Smart CutTM Layer Transfer Technology." MRS Proceedings 1068 (2008). http://dx.doi.org/10.1557/proc-1068-c01-01.

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ABSTRACTEngineered substrates are expected to play a dominant role in the field of modern nano-electronic and optoelectronic technologies. For example, engineered substrates like SOI (Silicon On Insulator) make possible efficient optimization of transistors' current drive while minimizing the leakage and reducing parasitic elements, thus enhancing the overall IC performance in terms of speed or power consumption. Other generations of engineered substrates like strained SOI (sSOI) provide solutions to traditional scaling for 32 nm node and beyond [1] technologies.The Smart Cutä technology, intr

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ANNOU, Amina, and Mustapha ACHIBANE. "Les Institutions de la microfinance entre approche sociale et approche de la création de valeur : Cas des associations de Micro-Crédits." International Journal of Accounting, Finance, Auditing, Management and Economics, December 6, 2024. https://doi.org/10.5281/zenodo.14289247.

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<strong>Résumé :</strong> Cette étude examine la capacité des institutions de microfinance (IMF) à concilier entre la performance financière et utilité sociale, un enjeu crucial dans le contexte de l’économie sociale et solidaire. Une approche méthodologique mixte a été adoptée, combinant une analyse conceptuelle et une enquête de terrain menée auprès de trois IMF majeures à Casablanca. Les données ont été collectées à partir de questionna

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