To see the other types of publications on this topic, follow the link: Distributed register.
Dissertations / Theses on the topic 'Distributed register'
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 21 dissertations / theses for your research on the topic 'Distributed register.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.
1
Bunchua, Santithorn. "Fully Distributed Register Files for Heterogeneous Clustered Microarchitectures." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5041.
Full textAbstract:
Conventional processor design utilizes a central register file and a bypass network to deliver operands to and from functional units, which cannot scale to a large number of functional units. As more functional units are integrated into a processor, the number of ports on a register file grows linearly while area, delay, and energy consumption grow even more rapidly. Physical properties of a bypass network scale in a similar manner.
In this dissertation, a fully distributed register file organization is presented to overcome this limitation by relying on small register files with fewer ports and localized operand bypasses. Unlike other clustered microarchitectures, each cluster features a small single-issue functional unit coupled with a small local register file. Several clusters are used, and each of them can be different. All register files are connected through a register transfer network that supports multicast communications. Techniques to support distributed register file operations are presented for both dynamically and statically scheduled processors. These include the eager and multicast register transfer mechanisms in the dynamic approach and the global data routing with multicasting algorithm in the static approach. Although this organizaiton requires additional cycles to execute a program, it is compensated by significant savings obtained through smaller area, faster operand access time, and lower energy consumption. With faster operating frequency and more efficient hardware implementation, overall performance can be improved.
Additionally, the fully distributed register file organization is applied to an ILP-SIMD processing element, which is the major building block of a massively parallel media processor array. The results show reduction in die area, which can be utilized to implement additional processing elements. Consequently, performance is improved through a higher degree of data parallelism through a larger processor array.
In summary, the fully distributed register file architecture permits future processors to scale to a large number of functional units. This is especially desirable in high-throughput processors such as wide-issue processors and multithreaded processors. Moreover, localized communication is highly desirable in the transition to future deep submicron technologies since long wire is a critical issue in processes with extremely small feature sizes.
2
Del, Pozzo Antonella. "Building distributed computing abstractions in the presence of mobile byzantine failures." Thesis, Paris 6, 2017. http://www.theses.fr/2017PA066159/document.
Full textAbstract:
Dans cette thèse on s’intéresse à un modèle de faute Byzantins Mobiles. Jusqu’à présent, seulement le problème du Consensus a été résolu en présente de faute Byzantines Mobiles et plusieurs variations de ce modèle de faute ont été proposé. Pour chacun de ces modelés ont été prouvées les bornes inferieures du nombre de processus correct nécessaire et des solutions asymptotiquement optimales ont été proposées. Notre première contribution porte sur les registres repartis dans ce modèle. Les registres repartis sont l’abstraction à la base du stockage reparti. Ces résultats préconisent donc notre deuxième contribution principale, un modèle de faute Byzantine Mobile généralisé. Notre troisième contribution est un ensemble de preuves de nécessité et d’impossibilité pour les registres repartis dans ces modèles. En particulier on prouve qu’il n’est pas possible d’implémenter la spécification plus faible des registres dans un système asynchrone. Par contre, pour les systèmes synchrones, on prouve des bornes inferieures et propose des protocoles asymptotiquement optimaux pour le registrer régulier. Pour conclure, notre dernière contribution porte sur le problème d’accord approximé, une forme affaiblie du consensus. On résout ce problème dans le modèle basé sur ronde, le même du consensus. En outre, il est intéressant de noter qua dans le modèle statique, la borne inferieure sur le nombre de répliques est la même pour le consensus et pour le problème d’accord approximé. Le même invariant s’applique avec les fautes byzantine mobiles. De plus, on accompagne ces bornes inferieures avec une solution asymptotiquement optimale pour le problème d’accord approximéIn this thesis we consider a model where Byzantine failures are not fixed, we consider the so called Mobile Byzantine failures. So far, only Consensus problem has been solved in presence of Mobile Byzantine failures and interestingly different variations of this failure model have been proposed. For each of them have been proved lower bounds on the number of required processes and have been proposed tight solutions. Our first contribution concerns distributed Registers in such strong model. Distributed Registers are the basic abstraction for Distributed Storages. This advocates our second and main contribution, a general Mobile Byzantine Failure Model. Our main focus is about Distributed Registers, so our third contribution comes, we prove necessities and impossibilities in those models. In particular we prove that is it not possible to solve the weakest register specification in an asynchronous system. On the other side we prove lower bounds for the synchronous system, with respect to the proposed hierarchy models, and tight protocols to solve the Regular Register problem. To conclude, our last contribution is about the Approximate Agreement problem, a weaker form of Consensus. We solve such problem in the same round-based models as Consensus so far. The interesting result is the following, in presence of static Byzantine failures, lower bounds on the number of correct replicas does not change between consensus and approximate agreement. The same invariant still holds in presence of Mobile Byzantine failure. Moreover, along with lower bounds we propose a tight solution to solve approximate agreement
3
Bonnin, David. "Algorithmique distribuée asynchrone avec une majorité de pannes." Thesis, Bordeaux, 2015. http://www.theses.fr/2015BORD0264/document.
Full textAbstract:
En algorithmique distribuée, le modèle asynchrone par envoi de messages et à pannes est connu et utilisé dans de nombreux articles de par son réalisme,par ailleurs il est suffisamment simple pour être utilisé et suffisamment complexe pour représenter des problèmes réels. Dans ce modèle, les n processus communiquent en s'échangeant des messages, mais sans borne sur les délais de communication, c'est-à-dire qu'un message peut mettre un temps arbitrairement long à atteindre sa destination. De plus, jusqu'à f processus peuvent tomber en panne, et ainsi arrêter définitivement de fonctionner. Ces pannes indétectables à cause de l'asynchronisme du système limitent les possibilités de ce modèle. Dans de nombreux cas, les résultats connus dans ces systèmes sont limités à une stricte minorité de pannes. C'est par exemple le cas de l'implémentation de registres atomiques et de la résolution du renommage. Cette barrière de la majorité de pannes, expliquée par le théorème CAP, s'applique à de nombreux problèmes, et fait que le modèle asynchrone par envoi de messages avec une majorité de pannes est peu étudié. Il est donc intéressant d'étudier ce qu'il est possible de faire dans ce cadre.Cette thèse cherche donc à mieux comprendre ce modèle à majorité de pannes, au travers de deux principaux problèmes. Dans un premier temps, on étudie l'implémentation d'objets partagés similaires aux registres habituels, en définissant les bancs de registres x-colorés et les α-registres. Dans un second temps, le problème du renommage est étendu en renommage k-redondant, dans ses versions à-un-coup et réutilisable, et de même pour les objets partagés diviseurs, étendus en k-diviseursIn distributed computing, asynchronous message-passing model with crashes is well-known and considered in many articles, because of its realism and it issimple enough to be used and complex enough to represent many real problems.In this model, n processes communicate by exchanging messages, but withoutany bound on communication delays, i.e. a message may take an arbitrarilylong time to reach its destination. Moreover, up to f among the n processesmay crash, and thus definitely stop working. Those crashes are undetectablebecause of the system asynchronism, and restrict the potential results in thismodel.In many cases, known results in those systems must verify the propertyof a strict minority of crashes. For example, this applies to implementationof atomic registers and solving of renaming. This barrier of a majority ofcrashes, explained by the CAP theorem, restricts numerous problems, and theasynchronous message-passing model with a majority of crashes is thus notwell-studied and rather unknown. Hence, studying what can be done in thiscase of a majority of crashes is interesting.This thesis tries to analyse this model, through two main problems. The first part studies the implementation of shared objects, similar to usual registers,by defining x-colored register banks, and α-registers. The second partextends the renaming problem into k-redundant renaming, for both one-shotand long-lived versions, and similarly for the shared objects called splitters intok-splitters
4
Del, Pozzo Antonella. "Building distributed computing abstractions in the presence of mobile byzantine failures." Electronic Thesis or Diss., Paris 6, 2017. http://www.theses.fr/2017PA066159.
Full textAbstract:
Dans cette thèse on s’intéresse à un modèle de faute Byzantins Mobiles. Jusqu’à présent, seulement le problème du Consensus a été résolu en présente de faute Byzantines Mobiles et plusieurs variations de ce modèle de faute ont été proposé. Pour chacun de ces modelés ont été prouvées les bornes inferieures du nombre de processus correct nécessaire et des solutions asymptotiquement optimales ont été proposées. Notre première contribution porte sur les registres repartis dans ce modèle. Les registres repartis sont l’abstraction à la base du stockage reparti. Ces résultats préconisent donc notre deuxième contribution principale, un modèle de faute Byzantine Mobile généralisé. Notre troisième contribution est un ensemble de preuves de nécessité et d’impossibilité pour les registres repartis dans ces modèles. En particulier on prouve qu’il n’est pas possible d’implémenter la spécification plus faible des registres dans un système asynchrone. Par contre, pour les systèmes synchrones, on prouve des bornes inferieures et propose des protocoles asymptotiquement optimaux pour le registrer régulier. Pour conclure, notre dernière contribution porte sur le problème d’accord approximé, une forme affaiblie du consensus. On résout ce problème dans le modèle basé sur ronde, le même du consensus. En outre, il est intéressant de noter qua dans le modèle statique, la borne inferieure sur le nombre de répliques est la même pour le consensus et pour le problème d’accord approximé. Le même invariant s’applique avec les fautes byzantine mobiles. De plus, on accompagne ces bornes inferieures avec une solution asymptotiquement optimale pour le problème d’accord approximéIn this thesis we consider a model where Byzantine failures are not fixed, we consider the so called Mobile Byzantine failures. So far, only Consensus problem has been solved in presence of Mobile Byzantine failures and interestingly different variations of this failure model have been proposed. For each of them have been proved lower bounds on the number of required processes and have been proposed tight solutions. Our first contribution concerns distributed Registers in such strong model. Distributed Registers are the basic abstraction for Distributed Storages. This advocates our second and main contribution, a general Mobile Byzantine Failure Model. Our main focus is about Distributed Registers, so our third contribution comes, we prove necessities and impossibilities in those models. In particular we prove that is it not possible to solve the weakest register specification in an asynchronous system. On the other side we prove lower bounds for the synchronous system, with respect to the proposed hierarchy models, and tight protocols to solve the Regular Register problem. To conclude, our last contribution is about the Approximate Agreement problem, a weaker form of Consensus. We solve such problem in the same round-based models as Consensus so far. The interesting result is the following, in presence of static Byzantine failures, lower bounds on the number of correct replicas does not change between consensus and approximate agreement. The same invariant still holds in presence of Mobile Byzantine failure. Moreover, along with lower bounds we propose a tight solution to solve approximate agreement
5
Martiš, Viktor. "Návrh distribuovaného systému pro zpracování školní matriky ZŠ, SŠ, VOŠ." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2009. http://www.nusl.cz/ntk/nusl-236735.
Full textAbstract:
One of the software success condition on the software market is permanent development to keep in condition with actual technical tools. That is the reason why SAS software is searching for a way how to fulfil customer's requirements better. The change to the distributed system architecture brings new opportunities and sets up competitive advantage for SAS concurrently. The subject of this thesis is to create the design of movement to the distributed system. The main reason is to make analysis, design and partial implementation meeting functional requirements of the new architecture.
6
Giansante, Cesare. "Ricerca su Registri Distribuiti: un Approccio Basato su Distributed Hash Tables." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021. http://amslaurea.unibo.it/22887/.
Full textAbstract:
In questo lavoro di tesi viene proposta e realizzata una Distributed Hash Table (DHT).
Una Distributed Hash Table è un sistema di archiviazione decentralizzato che fornisce schemi di ricerca e archiviazione simili a una tabella hash, permettendo la memorizzazione di dati sotto forma di coppie chiave-valore.
Gestisce i dati distribuendoli su un numero di nodi e implementando uno schema di routing che consente di cercare in modo efficiente il nodo su cui si trova l’elemento della ricerca.
La caratteristica della DHT realizzata è quella di avere una struttura ad ipercubo. È stato utilizzato un simulatore, PeerSim, con il quale è stato possibile simulare la rete di nodi su cui si appoggia la DHT. Lo scopo di questo strumento è quello di permettere a chiunque lo utilizzi, di cercare in maniera facile e veloce dei dati specifici. Questo è permesso grazie all’implementazione del meccanismo di ricerca basato su keywords.
Il lavoro proposto fa parte di una ricerca più ampia, la quale, mira a realizzare un'architettura di sistema per promuovere lo sviluppo di sistemi di trasporto intelligenti (ITS) utilizzando registri distribuiti e tecnologie correlate.
Saranno implementate due tipologie di ricerca e, infine, verranno eseguiti dei test per valutare l’efficienza di queste operazioni.
Lo scopo è quello di constatare quanto sia efficiente il meccanismo di routing implementato, andando ad analizzare il rapporto tra il numero dei nodi della rete e il numero degli scambi di informazione tra i vari nodi necessario per completare una richiesta di ricerca.
7
La, Piana Federica. "Gestione e Indicizzazione di Dati in Contesti di Smart Transportation: un Approccio basato su Registri Distribuiti." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021. http://amslaurea.unibo.it/24250/.
Full textAbstract:
Veicoli a guida autonoma, nuovi modelli di Smart Mobility e servizi sempre più personalizzati stanno trasformando il mondo automobilistico che esige sempre più in sicurezza e affidabilità. I sistemi di trasporto intelligenti (ITS) consentono di affrontare in modo innovativo i problemi legati alla mobilità, attraverso soluzioni improntate su sicurezza, efficienza, efficacia e rispetto per l’ambiente.
La loro realizzazione, però, comporta il superamento di alcuni aspetti che devono essere considerati e che sono legati alla raccolta, alla memorizzazione e al livello di affidabilità dei dati.
Lo scopo del presente lavoro è quello di presentare un sistema di crowdsourcing decentralizzato, ideato per il contesto di Smart Transportation, che fa uso di un robusto schema di indicizzazione dei dati, pensato come alternativa ai tipici schemi centralizzati, sempre più frequentemente oggetto di attacchi e uso improprio.
Interamente basato su tecnologie distribuite, oltre a fornire tracciabilità e immutabilità dei dati, il sistema in questione fa uso di una Distributed Hash Table come livello posto sopra la DLT, al fine di migliorare la gestione dei dati in un contesto in cui l'attenzione degli utenti è in progressivo incremento e dove, inoltre, efficacia e efficienza si rivelano più che importanti, necessari.
8
Sibani, Riccardo. "Applied design of distributed ledgers for real estate and land registration." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-239005.
Full textAbstract:
The recent emergence of a distributed technology named blockchain, clearly created a new point of view in the data storing and data distribution fields. If on one hand blockchain is mainly known for Bitcoin (an auto-regulated decentralized digital currency), on the other hand it has the potential to set up an auto regulated economy.In this thesis, the blockchain technology will be analyzed and described starting from P2P architecture and its origin in 2009 Satoshi Nakamoto’s whitepaper, and leading to the most up to date blockchains. The advantages and disadvantages of such architecture will be pointed out keeping in mind the security, speed and cost of such infrastructure.While Real Estate companies have often anticipated the technological innovations, land registries, instead, derive and keep a working manner which is extremely old and out of date: made of unclear procedures and wet signatures. The market needs and legislation will be researched mainly referring to other works and integrated with a technical point of view with particular focus on the decentralization of such systems.After analyzing the flow, problems and flaws of the current system, a new proposal will be researched, in particular trying to minimize the dead time in between the different steps of the mortgage, increase transparency, as well as reducing dependence on the central authorities, leading to more convenient interactions among the properties’ stakeholders. An attractive low capitalization decentralized financial product will also be proposed and implemented able to lower the interest rate and create a profitable investment with low risk, low interest and durable in time.Secure and ad-hoc algorithms will be presented and, in a later section, analyzed in combination with different blockchain technologies. Scalability and performance will also be evaluated, taking into account all the current technology limitations and the near future opportunities.
9
Zhao, Nannan. "Towards a Flexible High-efficiency Storage System for Containerized Applications." Diss., Virginia Tech, 2020. http://hdl.handle.net/10919/100315.
Full textAbstract:
Due to their tight isolation, low overhead, and efficient packaging of the execution environment,
Docker containers have become a prominent solution for deploying modern applications.
Consequently, a large amount of Docker images are created and this massive image
dataset presents challenges to the registry and container storage infrastructure and so far
has remained a largely unexplored area. Hence, there is a need of docker image characterization that can help optimize and improve the storage systems for containerized applications. Moreover, existing deduplication techniques significantly degrade the performance of registries, which will slow down the container startup time. Therefore, there is growing demand for high storage efficiency and high-performance registry storage systems. Last but not
least, different storage systems can be integrated with containers as backend storage systems
and provide persistent storage for containerized applications. So, it is important to analyze
the performance of different backend storage systems and storage drivers and draw out the
implications for container storage system design. These above observations and challenges
motivate my dissertation.
In this dissertation, we aim to improve the flexibility, performance, and efficiency of the
storage systems for containerized applications. To this end, we focus on the following three
important aspects: Docker images, Docker registry storage system, and Docker container
storage drivers with their backend storage systems. Specifically, this dissertation adopts
three steps: (1) analyzing the Docker image dataset; (2) deriving the design implications;
(3) designing a new storage framework for Docker registries and propose different optimizations
for container storage systems.
In the first part of this dissertation (Chapter 3), we analyze over 167TB of uncompressed
Docker Hub images, characterize them using multiple metrics and evaluate the potential of
le level deduplication in Docker Hub. In the second part of this dissertation (Chapter 4),
we conduct a comprehensive performance analysis of container storage systems based on the
key insights from our image characterizations, and derive several design implications. In the
third part of this dissertation (Chapter 5), we propose DupHunter, a new Docker registry
architecture, which not only natively deduplicates layers for space savings but also reduces
layer restore overhead. DupHunter supports several configurable deduplication modes, which
provide different levels of storage efficiency, durability, and performance, to support a range
of uses. In the fourth part of this dissertation (Chapter 6), we explore an innovative holistic
approach, Chameleon, that employs data redundancy techniques such as replication and
erasure-coding, coupled with endurance-aware write offloading, to mitigate wear level imbalance in distributed SSD-based storage systems. This high-performance fash cluster can be used for registries to speedup performance.Doctor of Philosophy
The amount of Docker images stored in Docker registries is increasing rapidly and present challenges for the underlying storage infrastructures. Before we do any optimizations for the storage system, we should first analyze this big Docker image dataset. To this end, in this dissertation we perform the first large-scale characterization and redundancy analysis of the images and layers stored in the Docker Hub registry. Based on the findings, this dissertation presents a series of practical and efficient techniques, algorithms, optimizations to achieve high performance and flexibility, and space-efficient storage system for containerized applications. The experimental evaluation demonstrates the effectiveness of our optimizations and techniques to make storage systems flexible and space-efficacy.
10
Ehsan, ul Haque Muhammad. "Persistence and Node FailureRecovery in Strongly Consistent Key-Value Datastore." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-121281.
Full textAbstract:
Consistency preservation of replicated data is a critical aspect for distributed databaseswhich are strongly consistent. Further, in fail-recovery model each process also needs todeal with the management of stable storage and amnesia [1]. CATS is a key/value datastore which combines the Distributed Hash Table (DHT) like scalability and selforganization and also provides atomic consistency of the replicated items. However beingan in memory data store with consistency and partition tolerance (CP), it suffers frompermanent unavailability in the event of majority failure. The goals of this thesis were twofold (i) to implement disk persistent storage in CATS,which would allow the records and state of the nodes to be persisted on disk and (ii) todesign nodes failure recovery-algorithm for CATS which enable the system to run with theassumption of a Fail Recovery model without violating consistency. For disk persistent storage two existing key/value databases LevelDB [2] and BerkleyDB[3] are used. LevelDB is an implementation of log structured merged trees [4] where asBerkleyDB is an implementation of log structured B+ trees [5]. Both have been used as anunderlying local storage for nodes and throughput and latency of the system with each isdiscussed. A technique to improve the performance by allowing concurrent operations onthe nodes is also discussed. The nodes failure-recovery algorithm is designed with a goalto allow the nodes to crash and then recover without violating consistency and also toreinstate availability once the majority of nodes recover. The recovery algorithm is based onpersisting the state variables of Paxos [6] acceptor and proposer and consistent groupmemberships. For fault-tolerance and recovery, processes also need to copy records from the replicationgroup. This becomes problematic when the number of records and the amount of data ishuge. For this problem a technique for transferring key/value records in bulk is alsodescribed, and its effect on the latency and throughput of the system is discussed.
11
Imbs, Damien. "Calculabilité et conditions de progression des objets partagés en présence de défaillances." Phd thesis, Université Rennes 1, 2012. http://tel.archives-ouvertes.fr/tel-00722855.
Full textAbstract:
Dans un système distribué, différents processus communiquent et se synchronisent pour résoudre un calcul global. La difficulté vient du fait qu'un processus ne connait pas les entrées des autres. Nous considérons ici un système asynchrone: on ne fait aucune hypothèses sur les vitesses d'exécution relatives des différents processus. De plus, pour modéliser les pannes, nous considérons que les processus peuvent crasher: ils peuvent arrêter leur exécution à n'importe quel endroit de leur programme. Dans l'étude théorique des systèmes distribués, les problèmes doivent être considérés selon deux aspects: la sûreté et la progression. La sûreté définit quand une valeur de sortie est correcte. La progression définit dans quelles conditions un processus doit terminer une opération, indépendamment de la valeur qu'il choisit comme sortie. Cette thèse se concentre sur les liens entre calculabilité et conditions de progression des objets distribués. Dans un premier temps, nous introduisons et étudions la notion de conditions de progression asymétriques: des conditions de progression qui peuvent être différentes pour différents processus du système. Nous étudions ensuite la possibilité de fournir des abstractions dans un système donné. La question de l'équivalence de modèles de systèmes est ensuite abordée, en particulier dans le cas où les processus ont accès à des objets puissants. Pour finir, la thèse traite le sujet des tâches colorées en fournissant un algorithme de renommage adapté au cas où la concurrence est réduite. Une nouvelle classe de tâches colorées est enfin introduite qui englobe, sous un formalisme unique, plusieurs problèmes considérés jusqu'ici comme indépendants.
12
Dubois, Swan. "Tolérer les fautes transitoires, permanentes et intermittentes." Phd thesis, Université Pierre et Marie Curie - Paris VI, 2011. http://tel.archives-ouvertes.fr/tel-00663317.
Full textAbstract:
Un système réparti est un système constitué d'un ensemble d'unités de calcul autonomes dotées de capacités de communication afin de résoudre une tâche globale. Ce modèle est suffisament général pour décrire tout type de réseau physique (réseau local, réseau de capteurs, ...). Lorsque la taille d'un système réparti devient importante ou lorsque ce système est déployé dans un environnement non contrôlé, la probabilité que certains éléments du système subissent des fautes (panne, corruption de mémoire, piratage, ...) devient non négligeable. Ces fautes peuvent être classifiées en fonction de leur durée, de leur étendue et de leur nature. Dans cette thèse, nous nous intéressons aux systèmes répartis capables de tolérer simultanément plusieurs types de fautes à travers l'étude de trois problèmes fondamentaux. Nous présentons ainsi un protocole réparti simulant un registre atomique mono-écrivan multi-lecteurs en présence de fautes transitoires et de fautes permanentes de type crash. Ce protocole repose sur deux outils ré-utilisables : un protocole de communication et un système d'estampillage borné. Ensuite, nous proposons une étude de la synchronisation faible d'horloges logiques en présence de fautes transitoires et de fautes intermittentes Byzantines. Nous prouvons de nombreux résultats d'impossibilité et nous fournissons un protocole optimal dans les cas non couverts par ces résultats. Finalement, nous définissons trois nouveaux concepts de tolérance pour les systèmes répartis sujets à des fautes transitoires et des fautes intermittentes Byzantines. Nous donnons un protocole de construction d'une vaste classe d'arbres couvrants optimal selon ces trois concepts.
13
Lu, Chia-Han, and 呂佳翰. "Register allocation issues on highly distributed register file architectures." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/79041638544275958381.
Full textAbstract:
博士國立清華大學
資訊工程學系
102
Embedded processors developed within the past few years have employed novel hardware designs to reduce the ever-growing complexity, power dissipation, and die area. While using distributed register file architecture is considered to have less read/write ports than using traditional unified register file structures, it presents challenges in compilation techniques to generate efficient codes for such architectures. Digital signal processors (DSPs) with very long instruction word (VLIW) data-path architectures are increasingly being deployed on embedded devices for multimedia processing applications. To reduce the power consumption and design cost of VLIW DSP processors, distributed register files and multi-bank register architectures are bein adopted to reduce the number of read and write ports associated with register files, which presents new challenges for devising compiler optimization schemes. Distributed register file architectures divide registers into multiple sets, and it leads to complicated communication and small register files. Complicated communication requires a new phase to handle it. Small register files increase spilling and reduce performance. The dissertation attempts to resolve these two issues. There are three primary results: - A heuristic method is proposed for global register file assignment making suitable decisions based on local register file assignment. The experimental results indicate that the compilation based on our proposed approach delivers performance improvements. - We address the issues of reducing the spill cost for a VLIW DSP with distributed register files. Spill code produced by register allocation is traditionally handled by memory spills, but the multibank register-file architecture provides the opportunity to spill-out register values onto different register banks. We present a framework to model the live ranges in different register banks, and treats register banks as optional spilling locations. - To reduce spilling possibly produced from the phase of register file assignment, we propose a method which attempts to improve spilling by estimating the spilling cost from two aspects: assignment and spilling. We report that the SPIFR method not only reduces spilling ratios but increases the performances. The results of all experiments performed using our optimizing compiler based on the Open64. The results of experiments showed the effectiveness of each of my methods.
14
Lin, Yen-Ting, and 林彥廷. "Communication Synthesis on Distributed Register-File Microarchitecture." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/35430434783749856897.
Full textAbstract:
碩士國立交通大學
電子工程系所
97
In deep-submicron era, global interconnect delay has become the bottleneck while pursuing higher system clock speed. Several distributed register (DR) architectures have been proposed to cope with this problem by keeping most interconnects local. The recently proposed distributed register-file microarchitecture (DRFM) is one of the DR-based architectures. On DRFM, the number of inter-island connections (IICs) is used as an evaluation metric for quality of results in early design phases. This thesis proposes a two-phase resource-constrained communication synthesis algorithm for IIC minimization targeting DRFM. First, an iterative binding-then-rescheduling procedure is used to obtain a better outcome in the expanded solution space. Then, a data detouring procedure is utilized to further minimize the number of IICs. The experimental results show that an average of 24% IIC reduction can be achieved as compared to the previous work.
15
Chen, Chia-I., and 陳嘉怡. "High-Level Synthesis on Various Distributed Register Architectures." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/xvk8sq.
Full textAbstract:
博士國立交通大學
電子研究所
101
In deep submicron era, the wire delay is no longer negligible and is becoming a dominant factor of system performance. Distributed register (DR) based architectures, which try to keep most interconnects local within a cluster and thus minimize the number of long interconnects, is one of the state-of-the-art solution to cope with the increasing wire delay. In this dissertation, various DR-based architectures and the synthesis framework, from the point views of horizontal and vertical, are discussed thoroughly. In horizontal DR-based architecture, synthesis flows targeting DR-based architectures can be classified according to interconnect delay models they adopt: zero, unit and location-aware. First, a new resource-constrained communication synthesis algorithm is proposed for optimizing both inter-island connections (IICs) and latency targeting on DR-based architecture assuming zero inter-cluster delay. Then a DR-based architecture with unit inter-island delay is proposed to be more practical; a performance-driven architectural synthesis framework targeting this architecture is also developed. Several factors for evaluating the quality of results (QoR) are adopted as the guidance while performing architectural synthesis for better optimization outcomes. The experimental results show that the latency and the number of IITs can be reduced by 27% and 38% on average; and the latter is commonly regarded as an indicator for power consumption of on-chip communication. In the third part, a fully location-aware DR-based delay model is considered. Targeting on such a platform, we propose an architectural synthesis flow, which adopts a hierarchical scheme for performance optimization as well as an iterative strategy for hardware resource minimization. The experimental results show that the work does achieve better synthesis outcomes with a 14% higher system performance and a 33% less resource requirement than the prior arts. In addition to the horizontal DR-based architectures, the vertical DR-based architecture is also covered here. In this dissertation, we discover new architectures of vertical links that can achieve a better balance between area and delay. The thermal analysis is also conducted for comparisons and evaluations among the proposed architectures since the thermal issue is considered as one of the most critical challenges in 3D designs. Finally, we recommend several configurations as generic 3D FPGA architectures, which can save up to 52% area with virtually no delay penalty.
16
關啓邦. "The Support of SIMD Optimization for Distributed Register File Architectures." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/53502455109986409481.
Full textAbstract:
博士國立清華大學
資訊工程學系
101
To sustain continuously growing performance requirement, modern digital signal processing (DSP) processors are commonly equipped with subword instructions to accelerate signal processing workloads, such as audio processing and video encoding/decoding. To further increase the computation power of VLIW DSP processors, besides subword instructions, plural functional units of very long instruction word (VLIW) DSP processors can be added to process multiple data streams in parallel. However, because of power and area concerns, many embedded VLIW DSP processors adopt distributed register file designs, which privatize register files for clusters of functional units to reduce read/write ports of register files and wire connection between register files and functional units. The distributed register file designs introduce several access constraints on register files and present great challenges to compilers and assembly programmers in distributing single instruction, multiple data (SIMD) workload to clustered functional units of VLIW processors. To support VLIW DSP processors with distributed register files, several compiler phases have to consider the register-file access constraints and minimize their impact. In this dissertation, we address the issue in supporting SIMD parallelism for VLIW DSP processors with subword instructions and distributed register files. Currently, industrial practices have adopted intrinsics to enable developers to utilize hardware resources and compete with hand-coded assembly in performance. However, it is still an open issue to provide such a solution for VLIW DSP processors with distributed register files. In this work, we propose a SIMD intrinsics design to allow programmers to write highly optimized code by following our programming guides. Our intrinsics design allows programmers to parallelize C/C++ programs with access to DSP subword instructions and clustered functional units of VLIW DSP processors. In addition, we also propose collaborative compiler optimizations to enable efficient code generation for SIMD programs written in the intrinsics. The collaborative optimizations include (1) a register-file assignment scheme prior to conventional register allocation which attempts to avoid register-file access constraints by assigning data to proper register files (2) two data replication techniques which reduce the inter-cluster communication overhead and avoid register-file constraints in the highly optimized SIMD programs with intrinsics. In our experiments, we use DSPstone benchmark and H.264 kernels to evaluate the proposed intrinsics programming and compiler optimization scheme. The intrinsics support and compiler optimizations are implemented in an Open64 compiler which has been optimized for a VLIW DSP processor with distributed register files. We rewrite the DSPstone benchmark and H.264 kernels with the SIMD intrinsics by following the programming guides. The result shows that we are able to obtain remarkable performance improvements with the intrinsics and compiler optimizations, which are speedups of 2.9 and 3.5 for DSPstone and H.264 kernels, respectively. Besides the decent performance improvement over original C programs, we also provide performance comparison between hand-coded assembly and C programs with SIMD intrinsics for H.264 kernels.
17
Wu, Chung-Ju, and 吳中如. "Global Optimizations in Compilers for VLIW DSP Processors with Distributed Register Files." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/89728810996706561122.
Full textAbstract:
博士國立清華大學
資訊工程學系
103
Abstract Digital signal processors (DSPs) with very long instruction word (VLIW) data-path architectures are increasingly being deployed on embedded devices for multimedia processing applications. While developing new VLIW DSP processors, engineers always take complexity, die size, and power dissipation into consideration. Therefore, some popular and traditional designs may not be feasible for embedded systems. Instead, distributed register files and multi-bank register architectures are being adopted to eliminate the amount of read/write ports associated with register files. Although such wide varieties of register file architectures and irregular designs achieve high performance and low power consumption criterion, they present challenges for devising compiler optimization schemes as well. Compiler optimizations, which direct code generation more efficiency, can be conceptually classified into local and global optimizations. Local optimizations only take place within small scope of code fragment, hence the impact of irregular designs is trivial. On the contrary, global optimizations usually go through entire procedure and try to utilize resources as effectively as possible, so the irregular designs and distributed scenarios make global optimizations difficult to have expected improvement. This dissertation has made contributions to the development and discussion of global optimizations on compilers for a novel VLIW DSP with distributed register files. The target DSP architecture, known as PAC DSP core, is designed with distinctively banked register files with highly restricted port access. Our experiences of developing global optimizations in compilers for the PAC DSP may also be of interest to those involved in developing compilers for the similar architectures. Experiments were also performed on the PAC VLIW DSP with distributed register files by incorporating our proposed optimization schemes into an Open64-based compiler. Several benchmarks such as EEMBC and MiBench were tested for evaluating the improvement of utilizing the features of the specific register file architectures. It shows that a VLIW DSP compiler applied by our global optimization schemes exhibits performance superior to traditional strategies.
18
Hsu, Wan-Ling, and 許婉玲. "Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/40624337872236959805.
Full text
19
(9786557), Maureen Chapman. "An exploration of leadership of registered nurses in clinical settings." Thesis, 2017. https://figshare.com/articles/thesis/An_exploration_of_leadership_of_registered_nurses_in_clinical_settings/13444769.
Full textAbstract:
Nurses provide leadership at various levels throughout healthcare organisations as Directors of Nursing, Chief Nursing Officers, as well as clinical leaders at a unit level. Existing research into nursing leadership has mainly focussed on transformational and transactional forms of leadership, which has been at the expense of exploring more contemporary forms of leadership. Furthermore there is limited research into the experiences of leadership from registered nurses working in the clinical settings.
This research explored the extent and appropriateness of four forms of leadership namely transactional, transformational, distributed and hybrid leadership as it applies in to clinical nursing.
20
Cardoso, Manuel Pedro dos Santos. "As Fintech e o direito financeiro : distribuição, encriptação e automatização." Master's thesis, 2021. http://hdl.handle.net/10400.14/36719.
Full textAbstract:
O fenómeno da Fintech é muitas vezes visto como uma fusão inédita de duas indústrias em muitos aspetos antagónicas: a industria tecnológica, rápida, inovadora e exploradora do desconhecido, e a indústria financeira, complexa, conservadora e altamente regulada. Com o desenvolvimento de tecnologias como a Tecnologia Descentralizada de Registo de Dados e a Inteligência Artificial, surgem questões sobre o enquadramento das novas figuras no atual paradigma jurídico, que nos propomos a perscrutar.The Fintech movement is often seen as a merge of two industries that differ in many ways. On one hand, the fast-paced, exploratory and innovative technology industry, on the other, the complex, conservative and highly regulated financial industry. With the development of technologies like the Distributed Ledger Technology and Artificial Intelligence, new questions about their place in the legal framework arise, which we propose to explore.
21
Macedo, Maria Joana Ribeiro de Faria Carvalho. "O regime jurídico da formação e do (in)cumprimento dos contratos inteligentes : os smart contracts." Master's thesis, 2019. http://hdl.handle.net/10400.14/30396.
Full textAbstract:
Um contrato inteligente é um protocolo computadorizado que executa cláusulas condicionais inseridas numa plataforma descentralizada. Permite que as obrigações se cumpram de forma económica e eficiente, reforça a confiança das partes no cumprimento, e garante ainda a transparência e a confidencialidade das transações. Esta dissertação estuda as características e o procedimento de formação de um contrato inteligente, e procura responder à questão de saber se este pode ser considerado um contrato civil válido
à luz do ordenamento jurídico português, não só como contrato de execução, mas como acordo de constituição das obrigações que executa. Além disso, analisa os problemas colocados pela auto-execução de um contrato inteligente e enquadra o regime jurídico do cumprimento das obrigações que nele se inserem. Propõe, por fim, uma solução que equilibre os custos da inflexibilidade dos contratos inteligentes com os benefícios gerais resultantes do seu reconhecimento.A smart contract is a computerized protocol that executes conditional clauses introduced in a decentralized platform. As such, it enables the execution of agreements in a costeffective way, enforces the trust between the parties upon the fulfilment of the obligations, whilst ensuring the transparency and confidentiality of the transactions. This dissertation explores the characteristics and procedure of formation of a smart contract, and aims to answer the question whether it can be considered a valid civil contract under Portuguese jurisdiction, not only as a contract of execution, but also as an agreement of constitution of the obligations it executes. Moreover, it analyses the problems posed by the self-execution of a smart contract and establishes the framework for the fulfilment of the obligations it contains. This dissertation proposes a solution that balances the costs of inflexibility of smart contracts with the overall benefits of its recognition.