Dissertations / Theses on the topic 'Doherty power amplifiers'

Modern wireless communication systems use spectrally efficient modulation schemes to reach high data rate transmission. These schemes are generally involved with signals with high peak-to-average power ratio (PAPR). Moreover, the development of next generation wireless communication systems requires the power amplifiers to operate over a wide frequency band or multiple frequency bands to support different applications. These wide-band and multi-band solutions will lead to reductions in both the size and cost of the whole system. This dissertation presents several advanced power amplifier solutions to provide wide-band and multi-band operations with efficiency improvement at power back-offs.

Thesis (MScIng)--Stellenbosch University, 2008.<br>ENGLISH ABSTRACT: Modern communication systems demand efficient, linear power amplifiers. The amplifiers are often operated in the backed-off power levels at which linear amplifiers such as class B amplifier are particularly inefficient. The Doherty amplifier provides an improvement as it increases efficiency at backed of power levels. Doherty amplifiers consists of two amplifiers, a carrier amplifier and a peaking amplifier, of which the output is combined in a novel way. Implementation of the Doherty amplifier with transistors is not ideal. One of the main problems is the insufficient current production of the peaking amplifier at peak envelope power (PEP) if it is implemented as a class C amplifier. A suggested solution to this problem is a bias adaption system that controls the peaking amplifier gate voltage dynamically depending on the input power levels. The design and evaluation of such a adaptive Doherty amplifier is the main goal of this thesis. A classical Doherty amplifier with and an uneven Doherty amplifier with unequal power division between the carrier and peaking amplifiers are also evaluated and compared with the adaptive Doherty amplifier. The amplifiers are designed using a 10 W LDMOS FET device, the MRF282. The adaptive Doherty amplifier and the uneven Doherty amplifier show significant improvements in efficiency and output power over the even Doherty amplifier. At PEP the adaptive Doherty delivers 42.4 dBm at 39.75 % power added efficiency (PAE), the uneven Doherty amplifier 41.9 dBm at 40.75 % PAE and the even Doherty amplifier 40.8 dBm at 38.6 % PAE. At 3dB backed-off input power the adaptive Doherty amplifier has an efficiency of 34.3%, compared to 34.9 5% for the uneven Doherty amplifier and 29.75 % for the even Doherty amplifier.<br>AFRIKAANSE OPSOMMING: Moderne kommunikasie stelsels vereis effektiewe, linieêre drywing versterkers. Die versterkers word dikwels in laer drywings vlakke bedryf waar linieêre versterkers soos ’n klas B versterker besondere lae effektiwiteit het. Die Doherty versterker bied ’n uitweg omdat dit verbeterde effektiwiteit by lae drywings vlakke bied. ’n Doherty versterker bestaan uit twee versterkers, die hoof versterker en die aanvullende versterker, waarvan die uittrees met ’n spesiale kombinasie netwerk bymekaar gevoeg word. Die implementasie van Doherty versterkers met transistors is nie ideaal nie. Een van die hoof probleme is die onvoldoende stroom wat deur die aanvullings versterker gebied word by piek omhulsel drywing (POD). ’n Oplossing vir die probleem is om ’n aanpassings sisteem te gebruik wat die aanvullende versterker se hekspanning dinamies beheer afhangende van die intree drywings vlakke. Die ontwerp en evaluasie van so ’n aanpassings Doherty versterker is die hoof doel van hierdie tesis. ’n Klassieke Doherty versterke met gelyke drywings verdeling en ’n ongelyke Doherty versterker wat gebruik maak van ongelyke drywings verdeling tussen die hoof-en aanvullende versterkers is ook gevalueer en vergelyk met die aanpassings Doherty versterker. Die versterkers was ontwerp met ’n 10 W LDMOS FET, die MRF282. Die aanpassings Doherty versterker en die ongelyke Doherty versterker het aanmerklike verbeteringe in effektiwiteit en uittree drywing gebring in vergelyking met die ewe Doherty versterker. By POD het die aanpassings versterker 42.4 dBm teen 39.75 % drywing toegevoegde effektiwiteit (DTE) gelewer, die ongelyke Doherty versterker 41.9 dBm teen 40.75 % DTE, en die ewe Doherty versterker 40.8 dBm teen 38.6 DTE. By ’n intree drywingsvlak 3 dB laer as POD het die aanpassings Doherty versterker ’n effektiwiteit van 34.3 % getoon, in vergelyking met die onewe Doherty versterker se 34.9 % en die ewe Doherty versterker se 29.75 % DTE.

Power amplifiers (PAs) are one of the most crucial elements in wireless standards becasue they are the most power hungry subsystems. These elements have to face an important issue, which is the power efficiency, a fact related with the output back-off (OBO). But the OBO depends on the kind of modulated signal, in proportion to the modulated signal peak-to-average power ratio (PAPR). The higuer is the data rate, the higer is the OBO, and consequently the lower is the efficiency. A low efficiency of PAs causes the waste of energy as heat. Furthermore, the trade-off between linearity and efficiency in PAs is another major issue. To cope with the undesired circumstances producing efficiency degradation, the Doherty power amplifier (DPA) is one of the useful techniques which provide high efficiency for high PAPR of modern communication signals. Nevertheless, the limited bandwidth (BW) of this kind of PAs (about 10% of fractional bandwidth) and its importance (in modern wireless systems such as LTE, WiMAX, Wi-Fi and satellite systems) have encouraged the researchers to improve this drawback in recent years. Some typical BW limiting factors effect on the performance of DPAs: i) quarter-wave length transformers, ii) phase compensation networks in/output matching circuits, iii) offset lines and device non-idealities; The quarter-wave length transformers performs as an inverter impedance in the load modulation technique of DPAs. The future objective in designing DPAs is to decrease the impact of these issues. In this context, this PhD-thesis is focused on improving fractional bandwidth of DPAs using the new methods that are related to impedance transformers instead of impedance inverters in the load modulation technique. This study is twofold. First, it is presented a novel DPA where a wideband GaN DPA in the 2.5 GHz band with an asymmetrical Wilkinson splitter. The impedance transformer of the proposed architecture is based on a matching network including a tapered line with multi-section transformer in the main stage. The BW of this DPA has ranged from 1.8 to 2.7 GHz. Plus, the obtained power efficiency (drain) is higher than 33% in the whole BW at both maximum and OBO power levels. Second, based on the benefits of the Klopfenstein taper, a promising DPA design is proposed where a Klopfenstein taper replaces the tapered line. In fact, this substitution results on reducing the reflection coefficient of the transformer. From a practical prototype realization of this novel Doherty-like PA in the 2.25 GHz band, this modification has demonstrated that the resulting DPA BW is increased in comparison to the conventional topology while keeping the efficiency figures. Moreover, this study also shows that the Klopfenstein taper based design allows an easy tuning of the group delay through the output reactance of the taper, resulting in a more straightforward adjustments than other recently published designs where the quarter-wave transformer is replaced by multi-section transmission lines (hybrid or similar). Experimental results have shown 43-54% of drain efficiency at 42 dBm output power, in the range of 1.7 to 2.75 GHz. Concretely, the results presented in this novel Doherty-like PA implies an specific load modulation technique that uses the mixed Klopfenstein tapered line together with a multi-section transformer in order to obtain high bandwidth with the usual efficiency in DPAs.<br>Los amplificadores de potencia (PAs) son uno de los elementos más importantes para los transmisores inalámbricos desde el punto de vista del consumo energético. Un aspecto muy importante es su eficiencia energética, un concepto relacionado con el back-off de salida (OBO), que a su vez viene condicionadpo por el PAPR de la señal modulada a amplificar. Una baja eficiencia de los PA hace que la pérdida de energía se manifieste en forma de calor. De hecho, esta cuestión conduce al incremento de los costes y tamaño, esto último por los radiadores. Además, el compromiso entre la linealidad y la eficiencia en los PA es otro problema importante. Para hacer frente a las circunstancias que producen la degradación de la eficiencia, el amplificador de potencia tipo Doherty (DPA) es una de las técnicas más útiles que proporcionan una buena eficiencia incluso para los altos PAPR comunes en señales de comunicación modernos. Sin embargo, el limitado ancho de banda (BW) de este tipo de PA (alrededor del 10% del ancho de banda fraccional) y su importancia (en los sistemas inalámbricos modernos, tales como LTE, WiMAX, Wi-Fi y sistemas de satélites) han animado a los investigadores para mejorar este inconveniente en los últimos años. Algunos aspectos típicos que limitan el BW en los DPA son: i) transformadores de longitud de cuarto de onda, ii) redes de compensación de fase y circuitos de adaptación de salida, iii) compensación de las líneas y los dispositivos no ideales. Los transformadores de cuarto de onda actuan como un inversor de impedancia en la técnica de modulación de carga de la DPA "("load modulation"). Concretamente, el objetivo futuro de diseño de DPA es disminuir el impacto de estos problemas. En este contexto, esta tesis doctoral se centra en mejorar el ancho de banda fraccional de DPA utilizando los nuevos métodos que están relacionados con el uso de transformadores de impedancias en vez de inversores en el subcircuito de modulación de carga. Este estudio tiene dos niveles. En primer lugar, se presenta una novedosa estructura del DPA de banda ancha usándose dispositivos de GaN en la banda de 2,5 GHz con un divisor Wilkinson asimétrico. El transformador de impedancias de la arquitectura propuesta se basa en una red de adaptación, incluyendo una línea cónica con múltiples secciones del transformador en la etapa principal. El BW de este DPA ha sido de 1,8 a 2,7 GHz. Además, se obtiene una eficiencia de drenador de más del 33% en todo el BW, tanto a nivel de potencia máxima como a nivel del OBO. En segundo lugar, aprovechando los beneficios de un adaptador de Klopfenstein, se propone un nuevo diseño del DPA. Con la sustitución de la lina conica por el Klopfenstein se reduce el coeficiente de reflexión de transformador de impedancias. Sobre un prototipo práctico de esta nueva estructura del Doherty, en la banda de 2,25 GHz, se ha demostrado que el BW resultante se incrementa en comparación con la topología convencional mientras se mantienen las cifras de eficiencia. Por otra parte, en este estudio se demuestra que el diseño basado en el Klopfenstein permite una afinación fácil del retardo de grupo a través de la reactancia de salida del taper, lo que resulta en un ajuste más sencillo que otros diseños publicados recientemente en el que el transformador de cuarto de onda se sustituye por multi-líneas de transmisión de la sección (híbridos o similar). Los resultados experimentales han mostrado un 43-54% de eficiencia de drenador sobre 42 dBm de potencia de salida, en el intervalo de 1,7 a 2,75 GHz. Concretamente, los resultados presentados en esta nueva estructura tipo-Doherty implican una técnica de modulación de carga que utiliza una combinación de un Klopfenstein junto con un transformador de múltiples secciones con el fin de obtener un alto ancho de banda con la eficiencia habitual en DPAs.<br>Els amplificadors de potència (PA) són un dels elements més importants per els sistemes ràdio ja que sone ls principals consumidors d'energía. Un aspecte molt important és l'eficiència de l'amplificador, aspecte relacionat amb el back-off de sortida (OBO) que a la seva vegada ve condicionat pel PAPR del senyal modulat. Una baixa eficiència dels PA fa que la pèrdua d'energia en manifesti en forma de calor. De fet, aquesta qüestió porta a l'increment dels costos i grandària, degut als dissipadors de calor. A més, el compromís entre la linealitat i l'eficiència en els PA es un altre problema important. Per fer front a les circumstàncies que porten a la degradació de l'eficiència, l'amplificador de potència Doherty (DPA) és una de les tècniques més útils i que proporcionen una bona eficiència per als alts PAPR comuns en senyals de comunicació moderns. No obstant això, l'ample de banda limitat (BW) d'aquest tipus de PA (al voltant del 10% de l'ample de banda fraccional) i la seva importància (en els sistemes moderns, com ara LTE, WiMAX, Wi-Fi i sistemes de satèl·lits) han animat els investigadors per millorar aquest inconvenient en els últims anys. Alguns aspectes tipicament limitadors del BW en els DPA son: i) transformadors de longitud d'quart d'ona, ii) xarxes de compensació de fase en circuits / adaptacions de sortida, iii) compensació de les línies i els dispositius no ideals. Els transformadors de quart d'ona s'utilitzen com a inversors d'impedàncies en la tècnica de modulació de càrrega del DPA ("load modulation"). Concretament, l'objectiu futur de disseny d'DPA és disminuir l'impacte d'aquests problemes. En aquest context, aquesta tesi doctoral es centra en millorar l'ample de banda fraccional dels DPA utilitzant nous mètodes que estan relacionats amb l'ús de transformadors d'impedàncies, en comptes d'inversors, en el subcircuit de modulació de càrrega. Aquest treball té dos nivells. En primer lloc, es presenta un DPA novedós que fa servir dispositus GaN DPA a la banda de 2,5 GHz amb un divisor Wilkinson asimètric. El transformador d'impedàncies de l'arquitectura proposada es basa en una xarxa d'adaptació, incloent una línia cònica amb múltiples seccions del transformador en l'etapa principal. El BW d'aquest DPA ha mostrat ser d'1,8 a a 2,7 GHz. A més, s'obté una eficiència de drenador de més del 33% en tot el BW, tant a nivell de potència màxima com de OBO. En segon lloc, sobre la base dels beneficis del adaptador de Klopfenstein, un proposa un nou disseny on un Klopfenstein substitueix la anterior línia cònica. Aquesta substitució repercuteix en la reducció del coeficient de reflexió de transformador d'impedàncies.Des d'una realització pràctica (prototipus) d'aquest nou amplificador tipus Doherty a la banda de 2,25 GHz, s'ha demostrat que el BW resultant s'incrementa en comparació amb la topologia convencional mentre es mantenen les xifres d'eficiència. D'altra banda, en aquest estudi es demostra que el disseny basat en el Klopfenstein permet una afinació fàcil del retard de grup a través de la reactància de sortida de la forma cònica, el que resulta en un ajust més senzill que altres dissenys publicats recentment en què el transformador de quart d'ona es substitueix per multi-línies de transmissió de la secció (híbrids o similar). Els resultats experimentals han mostrat un 43-54% d'eficiència de drenador en 42 dBm de potència de sortida, en l'interval de 1,7-2,75 GHz. Concretament, els resultats presentats en aquest nou amplificador tipus Doherty impliquen una tècnica de modulació de càrrega específic que utilitza una combinació del Klopfenstein juntament amb un transformador de múltiples seccions per tal d'obtenir un alt ample de banda amb la usual eficiència en DPAs.

The power amplifiers are typically the most power-consuming block in wireless communication systems. Spectrum is expensive, and newer technologies demand transmission of maximum amount of data with minimum spectrum usage. This requires sophisticated modulation techniques, leading to wide, dynamic signals that require linear amplification. Although linear amplification is achievable, it always comes at the expense of efficiency. Most of the modern wireless applications such as WCDMA use non-constant envelope modulation techniques with a high peak to average ratio. Linearity being a critical issue, power amplifiers implemented in such applications are forced to operate at a backed off region from saturation. Therefore, in order to overcome the battery lifetime limitation, a design of a high efficiency power amplifier that can maintain the efficiency for a wider range of radio frequency input signal is the obvious solution. A new technique that improves the drain efficiency of a linear power amplifier such as Class A or AB, for a wider range of output power, has been investigated in this research. The Doherty technique consists of two amplifiers in parallel; in such a way that the combination enhances the power added efficiency of the main amplifier at 6dB back off from the maximum output power. The classes of operation of power amplifier (A, AB, B, C etc), and the design techniques are presented. Design of a 2.14 GHz Doherty power amplifier has been provided in chapter 4. This technique shows a 15% increase in power added efficiency at 6 dB back off from the compression point. This PA can be implemented in WCDMA base station transmitter.<br>Master of Science

Doutoramento em Engenharia Electrotécnica<br>Nowadays, wireless communications systems demand for greater mobility and higher data rates. Moreover, the need for spectral efficiency requires the use of non-constant envelope modulation schemes. Hence, power amplifier designers have to build highly efficient, broadband and linear amplifiers. In order to fulfil these strict requirements, the practical Doherty amplifier seems to be the most promising technique. However, due to its complex operation, its nonlinear distortion generation mechanisms are not yet fully understood. Currently, only heuristic interpretations are being used to justify the observed phenomena. Therefore, the main objective of this work is to provide a model capable of describing the Doherty power amplifier nonlinear distortion generation mechanisms, allowing the optimization of its design according to linearity and efficiency criteria. Besides that, this approach will allow a bridge between two different worlds: power amplifier design and digital pre-distortion since the knowledge gathered from the Doherty operation will serve to select the most suitable pre-distortion models.<br>Presentemente, os sistemas de comunicações sem fios exigem uma maior mobilidade e elevadas taxas de transferência. Para além disso, a necessidade de eficiência espectral obriga ao uso de esquemas de modulação de envolvente variável. Consequentemente, o desenvolvimento de amplificadores de elevada eficiência, com uma elevada largura de banda e, ao mesmo tempo, lineares, tornou-se num dos maiores desafios para os engenheiros de projeto de amplificadores de potência. Por forma a cumprir estes requisitos muito rigorosos, o amplificador em configuração Doherty parece ser a técnica mais promissora. Contudo, devido à sua complexa operação, os seus mecanismos de geração de distorção não linear não são ainda completamente conhecidos. Atualmente, apenas interpretações heurísticas estão a ser usadas para justificar os fenómenos observados. Nesse sentido, o principal objetivo deste trabalho é desenvolver um modelo capaz de descrever os mecanismos de geração da distorção não linear em amplificadores Doherty, permitindo assim, a optimização do seu projeto, tendo em conta as especificações de linearidade e eficiência. Para além disso, esta abordagem permitirá uma ponte entre dois mundos diferentes: projecto de amplificadores de potência e pré-distorção digital, uma vez que o conhecimento recolhido da operação do Doherty ajudará na escolha de modelos de pré-distorção mais adequados.

This manuscript describes the design, development, and implementation of a linear high efficiency power amplifier. The symmetrical Doherty power amplifier utilizes TriQuint's 2nd Generation Gallium Nitride (GaN) on Silicon Carbide (SiC) High Electron Mobility Transistor (HEMT) devices (T1G6001032-SM) for a specified design frequency of 3.6 GHz and saturated output power of 40 dBm. Advanced Design Systems (ADS) simulation software, in conjunction with Modelithic's active and passive device models, were used during the design process and will be evaluated against the final measured results. The use of these device models demonstrate a successful first-pass design, putting less dependence on classical load pull analysis, thereby decreasing the design-cycle time. The Doherty power amplifier is a load modulated amplifier containing two individual amplifiers and a combiner network which provides an impedance inversion on the path between the two amplifiers. The carrier amplifier is biased for Class-AB operation and works as a conventional linear amplifier. The second amplifier is biased for Class-C operation, and acts as the peaking amplifier that turns on after a certain instantaneous power has been reached. When this power transition is met the carrier amplifier's drain voltage is already approaching saturation. If the input power is further increased, the peaking amplifier modulates the load seen by the carrier amplifier, such that the output power can increase while maintaining a constant drain voltage on the carrier amplifier. The Doherty power amplifier can improve the efficiency of a power amplifier when the input power is backed-off, making this architecture particularly attractive for high peak-to-average ratio (PAR) environments. The design presented in this manuscript is tuned to achieve maximum linearity at the compromise of the 6dB back-off efficiency in order to maintain a carrier-to- intermodulation ratio greater than 30 dB under a two-tone intermodulation distortion test with 5 MHz tone spacing. Other key figures of merit (FOM) used to evaluate the performance of this design include the power added efficiency (PAE), transducer power gain, scattering parameters, and stability. The final design is tested with a 20 MHz LTE waveform without digital pre-distortion (DPD) to evaluate its linearity reported by its adjacent channel leakage ratio (ACLR). The dielectric substrate selected for this design is 15 mil Taconic RF35A2 and was selected based on its low losses and performance at microwave frequencies. The dielectric substrate and printed circuit board (PCB) design were also modeled using ADS simulation software, to accurately predict the performance of the Doherty power amplifier. The PCB layout was designed so that it can be mounted to an existing 4" x 4" aluminum heat sink to dissipate the heat generated by the transistors while the part is being driven. The performance of the 3.6 GHz symmetrical Doherty power amplifier was measured in the lab and reported a maximum PAE of 55.1%, and a PAE of 48.5% with the input power backed-off by 6dB. These measured results closely match those reported by design simulations and demonstrate the models' effectiveness for creating a first-pass functional design.

In this thesis we introduce a two-way Doherty amplifier architecture with multiple feedbacks for digital predistortion based on impedance-inverting directional coupler (transcoupler). The tunable two-way Doherty amplifier with a tuned circulator-based impedance inverter is presented. Compact N-way Doherty architectures that subsume impedance inverter and offset line functionality into output matching networks are derived. Comprehensive N-way Doherty amplifier design and analysis techniques based on load-pull characterization of active devices and impedance modulation effects are developed. These techniques were then applied to the design of a two-way Doherty amplifier and a three-way Doherty amplifier which were manufactured and their performance measured and compared to the amplifier performance specifications and simulated results.

Next generation mobile communication systems require the use of linear RF power amplifier for higher data transmission rates. However, linear RF power amplifiers are inherently inefficient and usually require additional circuits or further system adjustments for better efficiency. This dissertation focuses on the development of new efficiency enhancement schemes for linear RF power amplifiers. The multistage Doherty amplifier technique is proposed to improve the performance of linear RF power amplifiers operated in a low power level. This technique advances the original Doherty amplifier scheme by improving the efficiency at much lower power level. The proposed technique is supported by a new approach in device periphery calculation to reduce AM/AM distortion and a further improvement of linearity by the bias adaptation concept. The device periphery adjustment technique for efficiency enhancement of power amplifier integrated circuits is also proposed in this work. The concept is clearly explained together with its implementation on CMOS and SiGe RF power amplifier designs. Furthermore, linearity improvement technique using the cancellation of nonlinear terms is proposed for the CMOS power amplifier in combination with the efficiency enhancement technique. In addition to the efficiency enhancement of power amplifiers, a scalable large-signal MOSFET model using the modified BSIM3v3 approach is proposed. A new scalable substrate network model is developed to enhance the accuracy of the BSIM3v3 model in RF and microwave applications. The proposed model simplifies the modeling of substrate coupling effects in MOS transistor and provides great accuracy in both small-signal and large-signal performances.

Mobile communication technologies are becoming increasingly sophisticated and have experienced rapid evolution over the last few decades, and this is especially true for the base station transmitter. In response to the ever increasing demand in communication traffic and data throughput, largely driven by video based social media platforms, both spectral and power efficient device and systems are needed to fulfil the requirements. In terms of energy consumption, the power amplifier is an important component, and although developing efficient technologies for handset equipment is important, it is the base station element of the communications system that poses the greater challenge, having to deal with many channels simultaneously, resulting in the need to linearly and efficiently amplify highly dynamic phase and amplitude modulated signals possessing very large peak-to-average power ratios, at high power levels. This unique set of challenges has led to continuous research to improve the efficiency of amplifiers that can accommodate such signals, and the Doherty architecture has now become the architecture-of-choice. However, most of the previous research studies demonstrate Doherty performance enhancement through a ‘conventional’ design approach that uses one input source and a passive power splitter to deliver power to each half of the Doherty structure. They do not emphasize the additional efficiency and other performance improvements that are possible in Doherty amplifiers when using two different, independent and phase coherent input sources, attached to the input path of both main and auxiliary amplifiers. IV The novel research work presented in this thesis introduces an optimised design approach for Doherty amplifier architectures with individual input sources, as well as detailing a measurement architecture that is necessary to characterise such structures, using separate, phase-coherent input sources in a realistic measurement scenario. Finally, following extensive characterisation of a number of promising architectures, investigations around efficiency enhancement are focused around the adaption of gate bias applied to the auxiliary amplifier device, and identifying, for the first time, what is possible by generating different shaping functions that relate bias voltage to the magnitude of the input signal. One completely new area of research and novelty introduced in this work for example shows how choosing the right shaping function can give improved linearity and importantly linearisability by producing a flat gain over dynamic range. Note that linearisability is important, and is defined here as the term used to describe the ease with which the non-linearities of a device or power amplifier can be corrected. It is often assumed in power amplifier design that efficiency and power are the most important parameters, and that modern digital pre-distortion (DPD) techniques can easily correct any non-linearity that may result. Industry is now finding that this is not the case however, and the type and nature of the non-linearity in terms to AM-AM and AM-PM distortion is very important in determining of the degree of linearization possible.

Power amplifiers are an indispensible part of the wireless communication systems. Conventional PAs provide peak efficiency at peak output power which is obtained at a certain fixed optimum resistance. These kind of amplifiers are normally called switched-mode power amplifiers (SMPAs) and are used for constant envelope signals. However, there is low efficiency at low output power which is the linear operation of a PA and is used for the amplification of non-constant envelope signals. For an optimum PA design, linearity and efficiency are the requirements. There are efficiency  enhancement techniques and Doherty architecture is one such approach. Classical Doherty (symmetric) approach entertains the signals that have peak to average power ratio (PAPR) of 6 dB. Applications like Long Term Evolution (LTE) having high PAPR of nearly 9 dB demand efficiency throughout the back-off range. Therefore the challenge is to design and implement an asymmetric Doherty power amplifier that ensures high efficiency in the back-off range greater than 6 dB. This work presents the design and implementation of an Asymmetric Doherty Power Amplifier (ADPA) for 12 dB back-off at 2.65 GHz in Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) technology. The carrier and peaking amplifiers are biased in class-B and C mode of operations, respectively. A branchline coupler is used to divide the input signal equally to amplifiers input. A 10 W GaN HEMT transistor is used as an active device for both amplifiers. The design has been implemented with ideal transmission lines and then shifted to microstrip lines using 508 um substrate. The measurement results of the ADPA prototype, when drain of carrier and peaking devices are biased at 24 V and 28 V  respectively, showed an input power back of (IPBO) of 9.68 dB with almost same power added efficiency (PAE) of 44% throughout the entire back-off range. The simulations are done with Agilent ADS and Momentum is used for Electromagnetic (EM) simulation.

Linearity and efficiency are both critical parameters for radio frequency transmitter applications. In theory, a Doherty amplifier is a linear amplifier that is significantly more efficient than comparable conventional linear amplifiers. It comprises two amplifiers, connected at their outputs by a quarter-wave transformer. The main amplifier is always on, while the peaking amplifier is off during low power levels. Load modulation of the main amplifier occurs when the peaking amplifier is on due to the quarter-wave transformer, ensuring the main amplifier never enters saturation. This results in an efficiency characteristic that increases with respect to input power at twice the normal rate at low power levels, and plateaus to a high value at high power levels. However, in much of the research that has been done to-date, less-than-ideal results have been achieved (although efficiency was better than a conventional amplifier). It was decided to investigate the cause of the discrepancy between theoretical and practical results, and devise a method to counteract the problem. It was discovered that the main cause of the discrepancy was non-ideal transistor gate-voltage to drain-current characteristics. The implementation of a gate bias control scheme based upon measured transistor transfer characteristics, and the desired main and peaking amplifier output currents, resulted in a robust method to ensure near-ideal results. A prototype amplifier was constructed to test the control scheme, and theoretical, simulated and measured results were well matched. The amplifier had a region of high efficiency in the high power levels (over 34% for the last 6 dB of input power), and the gain was nearly constant with respect to input power (between 4 and 5 dB over the dynamic range). Furthermore, it was decided to investigate the role harmonics play within the Doherty amplifier. A classical implementation shunts unwanted harmonics to ground within the main and peaking amplifiers. However, odd harmonics generated by the peaking amplifier can be used to operate the main amplifier like a class F amplifier. This means its supply voltage can be lowered, without the amplifier entering saturation, and the efficiency of the Doherty amplifier can be increased without a detrimental effect on the its linearity. A prototype amplifier was constructed to test this theory, and gave good results, with better efficiency than that of a conventional amplifier, and a constant gain with respect to input power (between 6.4 dB and 6.5 dB over the dynamic range).

With the growth of smart phones, the demand for more broadband, data centric technologies are being driven higher. As mobile operators worldwide plan and deploy 4th generation (4G) networks such as LTE to support the relentless growth in mobile data demand, the need for strategically positioned pico-sized cellular base stations known as ‘pico-cells’ are gaining traction. In addition to having to design a transceiver in a much compact footprint, pico-cells must still face the technical challenges presented by the new 4G systems, such as reduced power consumptions and linear amplification of the signals. The RF power amplifier (PA) that amplifies the output signals of 4G pico-cell systems face challenges to minimize size, achieve high average efficiencies and broader bandwidths while maintaining linearity and operating at higher frequencies. 4G standards as LTE use non-constant envelope modulation techniques with high peak to average ratios. Power amplifiers implemented in such applications are forced to operate at a backed off region from saturation. Therefore, in order to reduce power consumption, a design of a high efficiency PA that can maintain the efficiency for a wider range of radio frequency signals is required. The primary focus of this thesis is to enhance the efficiency of a compact RF amplifier suitable for a 4G pico-cell base station. For this aim, an integrated two way Doherty amplifier design in a compact 10mm x 11.5mm monolithic microwave integrated circuit using GaN device technology is presented. Using non-linear GaN HFETs models, the design achieves high effi-ciencies of over 50% at both back-off and peak power regions without compromising on the stringent linearity requirements of 4G LTE standards. This demonstrates a 17% increase in power added efficiency at 6 dB back off from peak power compared to conventional Class AB amplifier performance. Performance optimization techniques to select between high efficiency and high linearity operation are also presented. Overall, this thesis demonstrates the feasibility of an integrated HFET Doherty amplifier for LTE band 7 which entails the frequencies from 2.62-2.69GHz. The realization of the layout and various issues related to the PA design is discussed and attempted to be solved.

Yes<br>This work develops a novel dynamic load modulation Power Amplifier (PA) circuity that can provide an optimum compromise between linearity and efficiency while covering multiple cellular frequency bands. Exploiting monolithic microwave integrated circuits (MMIC) technology, a fully integrated 1W Doherty PA architecture is proposed based on 0.1 µm AlGaAs/InGaAs Depletion- Mode (D-Mode) technology provided by the WIN Semiconductors foundry. The proposed wideband DPA incorporates the harmonic tuning Class-J mode of operation, which aims to engineer the voltage waveform via second harmonic capacitive load termination. Moreover, the applied post-matching technique not only reduces the impedance transformation ratio of the conventional DPA, but also restores its proper load modulation. The simulation results indicate that the monolithic drive load modulation PA at 4 V operation voltage delivers 44% PAE at the maximum output power of 30 dBm at the 1 dB compression point, and 34% power-added efficiency (PAE) at 6 dB power back-off (PBO). A power gain flatness of around 14 ± 0.5 dB was achieved over the frequency band of 23 GHz to 27 GHz. The compact MMIC load modulation technique developed for the 5G mobile handset occupies the die area of 3.2.<br>This research was funded by the European Regional Development Fund (FEDER), through COMPETE 2020, POR ALGARVE 2020, Fundação para a Ciência e a Tecnologia (FCT) under i-Five Project (POCI-01-0145-FEDER-030500). This work is also part of the POSITION-II project funded by the ECSEL joint Undertaking under grant number Ecsel-345 7831132-Postitio-II-2017-IA. This work is supported by FCT/MCTES through national funds and when applicable co-funded EU funds under the project UIDB/50008/2020-UIDP/50008/2020. The authors would like to thank the WIN Semiconductors foundry for providing the MMIC GaAs pHEMT PDKs and technical support. This work is supported by the Project TEC2017-88242-C3-2-R- Spanish Ministerio de Ciencia, Innovación e Universidades and EU-FEDER funding.

This thesis presents a novel synthesis that generalizes the Doherty power amplifier theory of operation with regard to the combiner parameters. This analysis introduces, through a new parameter "x", simple formulae that re-define the relationships between the combiner parameters for a load modulation process over wide bandwidth and efficient usage at the combiner elements.

The signals of the new communication standards (LTE) show a great difference between the peak and its average power (PAPR) being unsuitable for use with conventional power amplifiers because they present maximum efficiency only when working with maximum power. Doherty power amplifiers for presenting a constant efficiency for a wide power range represent a favorable solution to this problem. This work presents the design methodology and measurements results of a fully integrated Doherty Power Amplifier in 65 nm CMOS technology with constant PAE over a 7 dB backoff. Measurements from 2.4 GHz to 2.6 GHz show constant PAE performance starting in 20% level up to 24% with a maximum output power of 23.4 dBm.The circuit was designed with special attention to low cost.

Tese (doutorado)—Universidade de Brasília, Faculdade de Tecnologia, Departamento de Engenharia Elétrica, 2013.<br>Submitted by Alaíde Gonçalves dos Santos (alaide@unb.br) on 2014-01-30T12:15:27Z No. of bitstreams: 1 2013_MarcosLajovicCarneiro.pdf: 9569833 bytes, checksum: d5a887ec15c4c2ecec643bcbe8f39b27 (MD5)<br>Approved for entry into archive by Guimaraes Jacqueline(jacqueline.guimaraes@bce.unb.br) on 2014-02-25T14:06:29Z (GMT) No. of bitstreams: 1 2013_MarcosLajovicCarneiro.pdf: 9569833 bytes, checksum: d5a887ec15c4c2ecec643bcbe8f39b27 (MD5)<br>Made available in DSpace on 2014-02-25T14:06:29Z (GMT). No. of bitstreams: 1 2013_MarcosLajovicCarneiro.pdf: 9569833 bytes, checksum: d5a887ec15c4c2ecec643bcbe8f39b27 (MD5)<br>Os sinais dos novos padrões de comunicação (LTE/LTE-Advanced) apresentam uma elevada diferença entre o pico e a média de sua potência (PAPR), sendo inadequados para o uso com os amplificadores de potência convencionais por apresentarem eficiência máxima apenas quando trabalham com sua potência máxima. Os novos sinais, na maior parte do tempo, demandam médias e baixas potências, concentrando a operação dos amplificadores de potência em uma região de baixa eficiência, o que provoca excessiva dissipação de energia em forma de calor e redução do tempo da bateria. Os amplificadores de potência Doherty por apresentarem uma eficiência constante por uma larga faixa de potências representam uma solução favorável para o problema da PAPR. Devido à tendência atual de redução dos dispositivos e integração completa da cadeia de RF em um único chip, decidiu-se implementar esse amplificador de potência na tecnologia CMOS 65nm por ela já ser adequada à implementação de circuitos digitais, o que permite a integração de um sistema completo. Este trabalho apresenta a metodologia de projeto e medições de um amplificador de potência Doherty totalmente integrado em tecnologia CMOS 65nm com desempenho de eficiência de potência adicionada (PAE) constante ao longo de uma retração de potência de 7dB. Medidas feitas de 2.4GHz à 2.6GHz mostram o desempenho constante de PAE começando no nível de 20% até 24%, com uma potência máxima de 23,4dBm. O circuito é totalmente descrito com todos os valores de componentes e detalhes de leiaute para posterior reprodução. As curvas que mostram o efeito de modulação ativa de carga, as correntes dos sub-amplificadores e o comportamento constante de PAE demonstram a implementação de um autêntico amplificador de potência Doherty. O circuito foi projetado com atenção especial para o baixo custo, utiliza apenas componentes discretos, cada sub-amplificador possui topologia cascode de saída simples e suas redes de entrada/saída são otimizadas para economizar área de chip e produzir um desempenho constante de PAE. _______________________________________________________________________________________ ABSTRACT<br>The signals of the new communication standards (LTE / LTE-Advanced) show a great difference between the peak and its average power (PAPR) being unsuitable for use with conventional power amplifiers because they present maximum efficiency only when working with maximum power. These signals demands low and medium power for most part of the time, which concentrates the operation of power amplifiers in a region of low efficiency, resulting in excessive heat dissipation and reduction of battery time. Doherty power amplifiers for presenting a constant efficiency for a wide power range represent a favorable solution to this problem. Given the current trend of reducing devices and full integration of RF chain on a single chip, it was decided to implement this power amplifier in 65nm CMOS technology due to its performance for digital circuits, allowing the integration of a whole system. This work presents the design methodology and measurements results of a fully integrated Doherty Power Amplifier in 65 nm CMOS technology with constant PAE over a 7 dB backoff. Measurements from 2.4 GHz to 2.6 GHz show constant PAE performance starting in 20% level up to 24% with a maximum output power of 23.4 dBm. The circuit is fully described with all components values and layout details for further reproduction. Curves showing the active load-pull effect, sub-amplifiers behavior and constant PAE prove that it is a genuine Doherty Power Amplifier. The circuit was designed with special attention to low cost, it is composed by only lumped components, each sub-amplifier has single-ended cascode topology and their input/output networks are optimized to save die area and to produce a constant PAE. _______________________________________________________________________________________ RESUMÉ<br>L’amplificateur de puissance (PA) est l’élément qui consomme le plus d’énergie dans les architectures d’émission-réception RF des terminaux mobiles. Les PAs conventionnels ont un rendement maximum seulement au niveau de puissance maximum, tandis que pour des niveaux de puissance plus bas, le rendement des PAs est très faible. Or les nouveaux standards de communications à haut débit (4G/LTE advanced) utilisent des modulations à enveloppe non-constante. Ainsi, le rapport entre la puissance maximum et la puissance moyenne du signal (PAPR – Peak to Average Power Ratio) est élevé. C’est le cas également pour l’OFDM qui possède un fort PAPR avec les porteuses multiples. Ainsi, lorsqu’un signal a un fort PAPR, cela signifie que le rendement moyen du PA utilisé est faible. La conséquence directe est la rapide décharge des batteries des terminaux mobiles. L’Amplificateur de Puissance Doherty (APD) est une technique connue d'amélioration du rendement. Cette technique permet d’augmenter le rendement moyen des amplificateurs en améliorant le rendement aux faibles niveaux de puissance, tout en maintenant le rendement maximum sur une plus grande plage de puissance de sortie. Cette technique est bien adaptée pour résoudre le problème de rendement pour les signaux à forts PAPR. De nombreux travaux proposent des solutions intégrées des APD dans une technologie à faible coût, mais au détriment du maintien d’un rendement à puissance ajoutée (Power Added-Efficiency, PAE) constant sur une grande plage de puissance. Nos travaux de recherche proposent un APD totalement intégré en technologie 65nm CMOS de STMicroelectronics à 2,535 GHz avec une PAE constante sur une plage de recul en puissance de sortie de 8 dB. Pour la conception de cet amplificateur, nous avons utilisé sept niveaux de métaux sur les dix couches de métaux de la technologie, les capacités sont de type MOM afin de respecter des contraintes faible coût. Le principe de l’APD est d’utiliser l’effet connu sous le nom de « load-pull actif » : une charge vue par une source de courant peut être modifiée par l’application d’un courant provenant d’une deuxième source. Pour atteindre cet objectif, l’architecture Doherty utilise deux amplificateurs de classes différentes en parallèle. Le PA principal (classiquement polarisé en classe B ou AB) fonctionne pour tous les niveaux de puissance et le PA auxiliaire (classiquement en classe C) ne fonctionne que pour les niveaux de puissance moyens et forts. L’augmentation de rendement s’explique par la transformation d’impédance de drain du PA principal, à cause de la combinaison de deux facteurs en même temps, la charge inversée vue par la ligne de transmission d’un quart d’onde et le courant du PA auxiliaire qui augmente. En effet, lorsque le courant du PA auxiliaire augmente, l’impédance vue par le PA principal se réduit. L’APD a été conçu avec les transistors à drain étendu haute tension pour soutenir une grande excursion de tension et produire des niveaux de puissance de sortie plus élevés. Les limites de Vdd et Vgs du transistor sont de 2.75V et de 5.5V, respectivement. Chaque sous-amplificateur a été conçu avec une topologie cascode pour donner au PA une meilleure isolation vis-à-vis des effets de désadaptation d’impédances entre la sortie et l’entrée. De plus, cette topologie permet d’avoir une plus grande tension d’alimentation Vdd par rapport à la topologie source commune. Les deux amplificateurs, principal et auxiliaire, ne sont cependant pas identiques. En effet, les dimensions des transistors dépendent du courant traversant chaque amplificateur. Ainsi, le transistor grille commune du PA principal est constitué de 28 transistors en parallèle, tandis que le transistor source commune du PA principal est composé de 26 transistors en parallèle. Pour le PA auxiliaire, le transistor grille commune est composé de 26 transistors en parallèle et son transistor source commune est composé de 14 transistors en parallèle. Chaque sous-amplificateur a été conçu et optimisé individuellement en prenant en compte les réseaux d'adaptation, l’inductance d’arrêt, les impédances d'entrée prévues par le diviseur de puissance et l’impédance de sortie prévue pour avoir l’effet loadpull actif de l’APD. Tout au long du travail de conception, les performances des deux PAs ont été tracées sur le même graphique pour équilibrer correctement le point de compression de chacun. Les courbes de PAE de chacun ont été optimisées dans le but de produire un APD avec une PAE constante sur une large gamme de puissance. Après la connexion des sous-amplificateurs dans le même schéma électrique, les lignes de transmission à éléments localisés ont été ajoutées, puis la topologie a été ré-optimisée pour réduire le nombre d'inductances et ainsi réduire l’espace utilisé dans la puce. À l'entrée, le diviseur de Wilkinson, la ligne de transmission déphasage et les réseaux d’adaptation d’entrée des PAs principal et auxiliaire ont été fusionnés et optimisés. À la sortie de l’APD, les réseaux d’adaptation de sortie des deux PAs et la ligne de transmission d’inversion de charge ont aussi été fusionnés et optimisés. Pour atteindre l'objectif d’avoir une PAE constante, une méthodologie d'optimisation séquentielle a été appliquée pour bien équilibrer tous les éléments dans le schéma de l’APD en respectant toutes les limites de tensions des transistors. Le circuit a été implémenté dans une surface de 1,72x1,68mm². Il a été conçu pour être mesuré avec des sondes directement positionnées sur les trois différents types de plots. Ce travail présente la méthodologie de conception et des résultats de mesure d'un amplificateur de puissance Doherty entièrement intégré dans la technologie 65 nm CMOS avec une PAE constante sur 7 dB de plage de puissance. Les mesures de 2,4 GHz à 2,6 GHz montrent des performances constantes en PAE de 20% jusqu'à 24% avec une puissance de sortie maximale de 23,4 dBm. Le circuit est entièrement décrit avec les valeurs des composants et les détails de layout pour permettre sa reproduction. Ce travail montre l'effet de modulation active de charge, le comportement en courant des sous-amplificateurs et la performance constante en PAE, ce qui démontre l’implémentation d’un véritable amplificateur de puissance Doherty. Le circuit est composé uniquement d'éléments localisés, et les réseaux d’entrée et de sortie sont optimisés pour réduire la taille de la puce et pour produire une PAE constante. L’amplificateur de puissance Doherty présenté est le premier APD totalement intégré en technologie 65 nm CMOS avec une PAE constante sur une large gamme de puissance. Il respecte de ce point de vue la théorie de Doherty. La comparaison avec un amplificateur de puissance classique polarisé en classe AB montre une amélioration de la PAE pour les niveaux de faible et moyenne puissance, permettant ainsi d’augmenter nettement le rendement moyen de l’amplificateur. Aucun autre APD publié ne présentait ce type de caractéristique en rendement dans cette technologie. La technologie 65nm CMOS est généralement plus appropriée pour les applications numériques, par conséquent, l’utilisation de cette technologie s'inscrit dans la tendance actuelle du développement d’un système complet sur une seule puce, où les étages numérique et analogique sont intégrés sur la même puce silicium.

Yes<br>RF power amplifiers in mobile WiMAX transceivers operate in an inherently nonlinear manner. It is possible to amplify the signal in the linear region, and avoid distortion, using output power back-off; however, this approach may suffer significant reduction in efficiency and power output. This paper investigates the use of Doherty techniques instead of back-off, to simultaneously achieve good efficiency and acceptable linearity. A 3.5 GHz Doherty RFPA has been designed and optimized using a large signal model simulation of the active device, and performance analysis under different drive levels. However, the Doherty EVM is generally poor for mobile WiMAX. Linearity may be improved by further digital pre-distortion, and a simple pre-distortion method using forward and reverse AM-AM and AM-PM modeling. Measurements on the realized amplifier show that this approach satisfies the EVM requirements for WiMAX base stations. It exhibits a PAE over 60%, and increases the maximum linear output power to 43 dBm, whilst improving the EVM.

This work is focused on design of L band power amplifier. First, the design of the amplifier is substantiated by necessary theoretical basics of RF power amplifiers. Then, after comparsion of availible RF power amplifiers concepts, the doherty power amplifier is chosen as a suitable type. Design of the amplifier is focused on the linearity and efficiency. AWR design program is used for simulation of the amplifier. Amplifier is then realized and parameters are measured. Measured results are then discussed and evaluated. This work proposes design of the linear doherty amplifier for modern communications systems.

The number of mobile wireless devices on the market has increased substantially over the last decade. The frequency spectrum has become crowded due to the number of devices demanding radio traffic and new modulation schemes have been developed to accommodate the number of users. These new modulation schemes have caused very poor efficiencies in power amplifiers for wireless transmission systems due to high peak-to-average power ratios (PAPR). This thesis first presents the issue with classical power amplifiers in modern modulation systems. A brief overview of current attempts to mitigate this issue is provided. A new RF power amplifier topology is then presented with supporting simulations. The presented amplifier topology utilizes the concept of negative conductance and load modulation. The amplifier operates in two stages, a low power stage and a high power stage. A negative conductance amplifier is utilized during peak power transmission to modulate the load presented to the input amplifier. This topology is shown to greatly improve the power added efficiency of power amplifiers in systems with high PAPR.

Over the last decade, the number of mobile wireless devices on the market has increased substantially. New “multi-carrier” modulation schemes, such as OFDM, WCDMA, and WiMAX, have been developed to accommodate the increasing number of wireless subscribers and the demand for faster data rates within the limited commercial frequency spectrum. These complex modulation schemes create signals with high peak-to-average power ratios (PAPR), exhibiting rapid changes in the signal magnitude. To accommodate these high-PAPR signals, RF power amplifiers in mobile devices must operate under backed-off gain conditions, resulting in poor power efficiency. Various efficiency-enhancement solutions have been realized for backed-off devices to combat this issue. A brief overview of one of the more extensively researched solutions, the Doherty amplifier, is given, and its inherent limitations are discussed. A recently proposed amplifier topology that provides the efficiency benefits of the Doherty amplifier, while overcoming some of the fundamental problems that plague the standard Doherty architecture, is investigated. A step-by-step design methodology is presented and confirmed by extensive simulation in Agilent ADS. A design example, tuned for maximum efficiency at peak output power, is implemented on a PCB and tested to verify the validity of the proposed circuit configuration.

Ce travail répond à un besoin industriel accru en termes d’amplification des signaux sur porteuses à enveloppes variables utilisés par les systèmes de télécommunications actuels. Ces signaux disposent d’un fort PAPR et d’une distribution statistique d’enveloppe centrée en-deçà de la valeur crête d’enveloppe. La raison pour laquelle les industriels télécoms requièrent alors des amplificateurs de très fortes puissances de sortie, robustes, fiables et ayant une dépense énergétique optimale le long de la dynamique d’enveloppe associée à un niveau de linéarité acceptable. Ce document expose les résultats d’étude et de réalisation de deux Amplificateurs de Puissance Doherty (APD) à haut rendement encapsulés en boîtiers plastiques QFN. Le premier est un amplificateur Doherty symétrique classique (APD-SE) et le second est un amplificateur à deux entrées RF (APD-DE). Ces démonstrateurs fonctionnant en bande C sont fondés sur l’utilisation de la technologie Quasi-MMIC associant des barrettes de puissance à base des transistors HEMTs AlGaN/GaN sur SiC à des circuits d’adaptation en technologie ULRC. L’approche Quasi-MMIC associée à la solution d’encapsulation plastique QFN permettant une meilleure gestion des comportements thermiques offre des performances électriques similaires à celles de la technologie MMIC avec des coûts et des cycles de fabrication très attractifs. Durant ces travaux, une nouvelle méthode d’évaluation des transistors dédiés à la conception d’amplificateurs Doherty a été développée et mise en oeuvre. L’utilisation intensive des simulations électromagnétiques 2.5D et 3D a permis de bien prendre en compte les effets de couplages entre les différents circuits dans l’environnement du boîtier QFN. Les résultats des tests des amplificateurs réalisés fonctionnant sur une bande de 1GHz ont permis de valider la méthode de conception et ont montré que les concepts avancés associés à l’approche Quasi-MMIC ainsi qu’à des technologies d’encapsulation plastique, peuvent générer des fonctions micro-ondes innovantes. Les caractérisations de l’APD-DE ont relevé l’intérêt inhérent à la préformation des signaux d’excitation et des points de polarisation de chaque étage de l’amplificateur<br>This work responds to an increased industrial need for on carrier signals with variable envelope amplification used by current telecommunications systems. These signals have a strong PAPR and an envelope statistical distribution centred below the envelope peak value, the reason why the telecom industrialists then require a robust and reliable high power amplifiers having an energy expenditure along of the envelope dynamics associated with an acceptable level of linearity. This document presents the results of the study and realization of two, high efficiency, Doherty Power Amplifiers (DPA) encapsulated in QFN plastic packages. The first is a conventional Doherty power Amplifier (DPA-SE) and the second is a dual-input Doherty power amplifier (DPA-DE). These C-band demonstrators are based on the use of Quasi-MMIC technology combining power bars based on the AlGaN/GaN transistors on SiC to matching circuits in ULRC technology. The Quasi-MMIC approach combined with Quasi-MMIC approach combined with QFN plastic package solution for better thermal behaviour management offers electrical performances similar to those of MMIC technology with very attractive coasts and manufacturing cycles. During this work, a new evaluation method for the transistors dedicated to the design of DPA was developed and implemented. The intensive use of 2.5D and 3D electromagnetic simulations made it possible to take into account the coupling effects existing between the different circuits in the QFN package environment. The results of the tests of the amplifiers realised and operating on 1GHz bandwidth validated the design method and showed that the advanced concepts associated with the Quasi-MMIC approach as well as plastic encapsulation technologies can generate innovative microwave functions. The characterizations of the DPA-DE have noted the interest inherent in the preformation of the excitation signals and the bias points of each stage of the amplifier

ITC/USA 2005 Conference Proceedings / The Forty-First Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2005 / Riviera Hotel & Convention Center, Las Vegas, Nevada<br>A conventionally designed radio frequency amplifier operated in its linear region exhibits low DC to RF conversion efficiency. Typically, for a power amplifier designed for digital modulation applications, the amplifier is operated “backed-off” from its P1dB point by a factor of 10 or -10 dB. The typical linear amplifier is biased for either Class A or Class A/B operation depending on the acceptable design trade-offs between efficiency and linearity between these two methods. A novel design approach to increasing the efficiency of a linear RF power amplifier using a modified Odd-Way Doherty technique is presented in this paper. The design was simulated, built and then tested. The design yields improvements in efficiency and linearity.

In today´s digital world, information and communication technology accounts for 3% and 2% of the global power consumption and CO2 emissions respectively. This alarming figure is on an upward trend, as future telecommunications systems and handsets will become even more power hungry since new services with higher bandwidth requirements emerge as part of the so called ¿future internet¿ paradigm. In addition, the mobile handset industry is tightly coupled to the consumer need for more sophisticated handsets with greater battery lifetime. If we cannot make any significant step to reducing the energy gap between the power hungry requirements of future handsets, and what battery technology can deliver, then market penetration for 4G handsets can be at risk. Therefore, energy conservation must be a design objective at the forefront of any system design from the network layer, to the physical and the microelectronic counterparts. In fact, the energy distribution of a handset device is dominated by the energy consumption of the RF hardware, and in particular the power amplifier design. Power amplifier design is a traditional topic that addresses the design challenge of how to obtain a trade-off between linearity and efficiency in order to avoid the introduction of signal distortion, whilst making best use of the available power resources for amplification. However, the present work goes beyond this by investigating a new line of amplifiers that address the green initiatives, namely green power amplifiers. This research work explores how to use the Doherty technique to promote efficiency enhancement and thus energy saving. Five different topologies of RF power amplifiers have been designed with custom-made signal splitters. The design core of the Doherty technique is based on the combination of a class B, class AB and a class C power amplifier working in synergy; which includes 90-degree 2-way power splitter at the input, quarter wavelength transformer at the output, and a new output power combiner. The frequency range for the amplifiers was designed to operate in the 3.4 - 3.6 GHz frequency band of Europe mobile WiMAX. The experimental results show that 30dBm output power can be achieved with 67% power added efficiency (PAE) for the user terminal, and 45dBm with 66% power added efficiency (PAE) for base stations which marks a 14% and 11% respective improvement over current stateof- the-art, while meeting the power output requirements for mobile WiMAX applications.

In today's digital world, information and communication technology accounts for 3% and 2% of the global power consumption and CO2 emissions respectively. This alarming figure is on an upward trend, as future telecommunications systems and handsets will become even more power hungry since new services with higher bandwidth requirements emerge as part of the so called 'future internet' paradigm. In addition, the mobile handset industry is tightly coupled to the consumer need for more sophisticated handsets with greater battery lifetime. If we cannot make any significant step to reducing the energy gap between the power hungry requirements of future handsets, and what battery technology can deliver, then market penetration for 4G handsets can be at risk. Therefore, energy conservation must be a design objective at the forefront of any system design from the network layer, to the physical and the microelectronic counterparts. In fact, the energy distribution of a handset device is dominated by the energy consumption of the RF hardware, and in particular the power amplifier design. Power amplifier design is a traditional topic that addresses the design challenge of how to obtain a trade-off between linearity and efficiency in order to avoid the introduction of signal distortion, whilst making best use of the available power resources for amplification. However, the present work goes beyond this by investigating a new line of amplifiers that address the green initiatives, namely green power amplifiers. This research work explores how to use the Doherty technique to promote efficiency enhancement and thus energy saving. Five different topologies of RF power amplifiers have been designed with custom-made signal splitters. The design core of the Doherty technique is based on the combination of a class B, class AB and a class C power amplifier working in synergy; which includes 90-degree 2-way power splitter at the input, quarter wavelength transformer at the output, and a new output power combiner. The frequency range for the amplifiers was designed to operate in the 3.4 - 3.6 GHz frequency band of Europe mobile WiMAX. The experimental results show that 30dBm output power can be achieved with 67% power added efficiency (PAE) for the user terminal, and 45dBm with 66% power added efficiency (PAE) for base stations which marks a 14% and 11% respective improvement over current stateof- the-art, while meeting the power output requirements for mobile WiMAX applications.

Ces travaux de recherche concernent la conception, la réalisation et la mesure des circuits d’amplification Doherty LDMOS intégrés large-bande pour stations de base, nécessaires au développement de la 5G. Suite à la recherche des techniques pour l’amélioration du rendement électrique pour des signaux à forte dynamique d’amplitude et les possibilités d’intégration, la technique Doherty a été choisie. Des études sur les structures Doherty à deux puis trois voies montrent que l’amélioration de rendement pourra être renforcée et étendue par l’ajout d’un troisième étage avec des tailles de transistors calculées en prenant en compte un fonctionnement en classe C des étages auxiliaires. Des limitations d’utilisation de la technique Doherty sont montrées par la prise en compte des différentes non-linéarités des transistors LDMOS. La recherche des architectures large-bandes montre que la technique d’absorption du CdS et l’utilisation de circuits de répartition de type mixte en entrée présentent des avantages pour l’intégration. A partir des différentes études, des amplificateurs de puissance Doherty MMIC à trois voies ont été réalisés avec un ratio d’asymétrie de 1 :3 :3 dans la bande de 1805 MHz à 2170 MHz. Les performances expérimentales montrent les potentialités du Doherty et notamment une nette amélioration du rendement sur toute la bande de fréquence. Des considérations spécifiques d’adaptation sont présentées dans le but de réduire les produits de distorsions d’ordre 3, 10 et 12 (IMD 10 /12). Les mesures de linéarité à différentes largeurs de bande instantanées sont très encourageantes et valident la nouvelle architecture du Doherty à trois voies asymétriques<br>This work presents the design, realization and measurement result of integrated broadband Doherty amplification circuits for base stations, required for 5G. Initially, based on the research for techniques to improve electrical efficiency for signals with high dynamic range, the Doherty technique is chosen to continue the work. Studies on different Doherty architectures showed that performance can be improved and extended by adding a third stage (3-way Doherty) with calculated auxiliary transistors’ sizes for which are operated in class C mode. Limitations on the practical use of the Doherty technique is demonstrated by the considerations of various non linearities of the LDMOS transistors. The research of wideband architectures shows simultaneous advantages of integration and broadband capability by the CdS absorption technique and the use of mixed type of input splitters. Based on the results of various studies, three-way Doherty MMIC power amplifiers were designed and realized using the CdS absorption technique with an asymmetry ratio of 1 : 3 : 3 in the band of 1805 MHz to 2170 MHz. Experimental performances have shown the potentialities of the 3-way Doherty and a clear efficiency improvement over the entire frequency band. Specific wideband operating conditions are presented to reduce distortion products of third (IMD 3), 10th and 12th (IMD 10/12). The linearity measurements at different instantaneous bandwidths are very encouraging and validate the new asymmetric three-way Doherty architecture

Les fortes capacités actuelles et envisagées des futurs liens satellites de communication pour la 5G conduisent les signaux traités dans les charges utiles à présenter simultanément d'importantes variations d'amplitude (PAPR&gt;10dB) et de très larges bandes passantes instantanées (BW&gt;1GHz). A l'intérieur du sous-système d'émission hyperfréquence, le fonctionnement du module d'amplification de puissance se trouve très contraint par les formes d'ondes véhiculées, il se présente comme l'un des postes de consommation énergétique des plus importants, et ayant le plus d'impact sur l'intégrité du signal émis. Dans ce contexte, les fonctions dédiées au traitement numérique des signaux et couramment implémentées par le processeur numérique (telles que le filtrage, la canalisation, et éventuellement la démodulation et la régénération des signaux bande de base) embarquées dans les charges utiles, représentent une solution à fort potentiel qui permettrait de relâcher les contraintes reportées sur la fonction d'amplification de puissance afin de gérer au mieux la ressource électrique allouée. Ces travaux de thèse proposent d'étudier les potentialités d'amélioration du fonctionnement en rendement et linéarité d'un amplificateur de type Doherty à double entrée de gamme 20W en technologie GaN et fonctionnant en bande C. La combinaison des signaux de puissance sur la charge RF est optimisée par une distribution optimale des signaux en amplitude et phase à l'entrée par des moyens numériques de génération. Dans un premier temps une méthodologie de conception large bande d'un amplificateur Doherty est introduite et validée par la conception d'un démonstrateur en bande C. Dans un second temps, l'outil expérimental permettant l'extraction des lois optimales de distribution d'amplitude et de phase RF est présenté en détail, et la caractérisation expérimentale du dispositif en double entrée est réalisée puis comparée aux simulations. Finalement, en perspective à ces travaux, une étude préliminaire des potentialités de l'architecture Doherty à double entrée pour la gestion d’une désadaptation de la charge de sortie (gestion de TOS) est menée et des résultats sont mis en avant<br>The high capabilities of current and future 5G communication satellite links lead the processed signals in the payloads to simultaneously exhibit large amplitude variations (PAPR&gt;10dB) and wide instantaneous bandwidths (BW&gt;1GHz). Within the microwave transmission subsystem, the operation of the power amplification stage is highly constrained by the transmitted waveforms, it is one of the most energy-consuming module of the payload affecting as well the integrity of the transmitted signal. In this context, the functions dedicated to digital signal processing and currently implemented by the digital processor (such as filtering, channeling, and possibly the demodulation and regeneration of baseband signals) embedded in the payloads, represent a potential solution that would reduce the constraints reported on the power amplification function and help to manage the allocated power ressource. This work proposes a study on the capability of dual input power amplifier architectures in order to manage the efficiency-linearity trade-off over a wide bandwidth. This study is carried out on a 20W GaN Doherty demonstrator operating in C band. The combination of the output signals on the RF load is managed by an optimal amplitude and phase distribution that is digitally controlled at the input. Firstly, a wideband design methodology of Doherty amplifier is introduced and validated on a C band demonstrator. In a second time the experimental tool allowing the extraction of amplitude and phase input distributions is presented, the dual input characterization is achieved and compared with simulation results. Finally, in perspective of this work, a preliminary study of the capabilities of the digital Doherty for the management of an output load mismatch (VSWR management) is carried out and the results are put forward

Les communications futures pour les applications civiles et militaires utilisent des signaux modulés complexes large bande qui seront émis à travers des amplificateurs de puissance multivoie de type DOHERTY qui devront avoir des performances en puissance, rendement, OBO et largeur de bande qui constituent aujourd’hui un véritable défi à relever. Pour ce faire les concepteurs ont besoin d’outils de caractérisation temporelle permettant la mesure normalisées et l’optimisation des tensions et courants aux accès des dispositifs non linéaires sous pointes ou connectorisés. Ce travail de thèse a permis de mettre en œuvre cet outil de caractérisation temporelle qui a été utilisé pour répondre à des besoins spécifiques pour la modélisation de transistor, pour l’optimisation de leur fonctionnement en termes de stabilité impulsion à impulsion, pour la recherche des conditions optimales de leur fonctionnement dans un amplificateur de type Doherty. Pour cette mise en œuvre une modélisation mathématique des échantillonneurs a été réalisée pour évaluer leurs performances et choisir le mieux adapté à la mesure temporelle RF. Des procédures d’étalonnages rigoureuses ont été développées pour obtenir simultanément des formes d’ondes temporelles calibrées à spectre très large (Basse fréquences jusqu’aux Hyperfréquences)<br>The future communications for civil and military applications will use complex wideband modulated signals to be transmitted through multi-channel DOHERTY power amplifiers which should have high performance in terms of power, efficiency, OBO, and bandwidth. In order to meet these stringent requirements, designers need time-domain characterization tools for calibrated measurements and for optimizing voltages and currents at both ports of non-linear connectorized or on-wafer devices. This work successfully implements time-domain characterization tools used to meet specific needs for transistor modeling, to optimize their operation in terms of pulse to pulse stability, and to search optimal conditions of their operation modes in a Doherty power amplifier. For this implementation, mathematical modeling is performed to evaluate sampler’s performances in terms of time-domain sampling efficiency in order to choose the best suited sampling architecture for RF time-domain measurements. Rigorous calibration procedures have been developed to obtain simultaneously full time-domain calibrated waveforms (from low Frequencies to Microwave frequencies)

The conventional Doherty architecture is commonly used in wireless transmitters for its ability to boost the average efficiency of a traditional single-ended class B amplifier. It consists of two parallel single-ended amplifying branches (named carrier and peaking amplifiers) which are linked, at the output, through a /4 combiner. This output combiner commonly has a significant impact on the overall bandwidth, as it is usually built from a transmission line structure with tuned dimensions. Other non-conventional combining structures could be designed, targeting a wider bandwidth, contributing to an overall increase of the Doherty amplifier’s bandwidth. Being this an high relevance research topic for the development of high efficient and broadband amplifiers, it is highly desirable to have a laboratory setup that implements a Doherty power amplifier to which distinct output combiner structures can be connected and tested. In that sense, the design of two single-ended amplifiers (the carrier and the peaking) was performed in a circuit simulator (ADS, from Keysight) together with the input power divider that compose the Doherty architecture. The Doherty amplifier main board was designed to incorporate the carrier and peaking amplifiers, and also the power splitter at the input, and it was prepared so that it could be connected to any desired combiner to be tested. A traditional Doherty power combiner was designed and both boards (Doherty amplifier and the combiner) were produced, connected and tested in the RF laboratory. The measured amplifier presented the typical caractheristics of a Doherty amplifier with nearly 75% of drain efficiency at full-power, and nearly 50% at the output back-off level. In addition, a second combiner unit was designed with two purposes. The first was to demonstrate the operation of the designed Doherty amplifier with a distinct output combiner, showing that, as intended in this work, it is suited to test multiple combiner structures. The second objective was to serve as preliminary test to evaluate the possibility of merging the output combiner with the antenna element. Taking advantage of the electromagnetic coupling between antennas, this second combiner structure uses two antenna elements that were tuned to simultaneously behave as output combiner of the Doherty amplifier and a radiating element.<br>A arquitetura Doherty convencional é tipicamente utilizada em transmissores sem fios pela sua capacidade de aumentar a eficiência média de um tradicional amplificador em classe B. O amplificador Doherty consiste em dois amplificadores em paralelo (chamados de amplificadores carrier e peaking) que são ligados, na saída, através de um combinador de /4. Este combinador de saída geralmente tem um impacto significativo na largura de banda do amplificador, pois é tipicamente construído a partir de uma estrutura de linhas de transmissão com dimensões ajustadas para uma frequência. Outras estruturas de combinadores não convencionais podem ser projetadas, visando uma largura de banda maior, contribuindo para um aumento geral da largura de banda do amplificador Doherty. Sendo este um tópico de investigação de elevada relevância para o desenvolvimento de amplificadores de alta eficiência e largura de banda, seria interessante ter um setup de laboratório que implemente um amplificador de potência Doherty para o qual estruturas combinadoras distintas possam ser ligadas à saída do amplificador e testadas. Nesse sentido, o projeto de dois amplificadores (carrier e peaking) foi realizado num simulador de circuitos (ADS, da Keysight) junto com o divisor de potência de entrada que compõe a arquitetura Doherty. A placa principal do amplificador Doherty foi projetada para incorporar os amplificadores carrier e peaking, e também o divisor de potência na entrada, e foi preparada de modo que pudesse ser ligada a qualquer combinador desejado a ser testado. Um combinador de potência Doherty tradicional foi projetado e ambas as placas (amplificador Doherty e o combinador) foram produzidas, soldadas e testadas no laboratório de RF. O amplificador medido apresentou as características típicas de um amplificador Doherty com aproximadamente 75% de eficiência de dreno na potência máxima e aproximadamente 50% no ponto de output back-off. Além disso, foi projetado um segundo combinador com dois objetivos. O primeiro foi demonstrar o funcionamento do amplificador Doherty projetado com um combinador de saída distinto, mostrando que, como pretendido neste trabalho, o amplificador desenhado é adequado para testar múltiplas estruturas combinadoras. O segundo objetivo foi servir como teste preliminar para avaliar a possibilidade de fundir o combinador de saída com a antena. Aproveitando o acoplamento eletromagnético entre antenas, esta segunda estrutura combinadora utiliza duas antenas que foram projetadas para se comportarem simultaneamente como combinador de saída do amplificador Doherty e como elemento radiante.<br>Mestrado em Engenharia Eletrónica e Telecomunicações

碩士<br>國立中央大學<br>電機工程學系<br>105<br>The power amplifier is a critical building block in the RF transmitter. The efficiency、bandwidth and the ability of providing the stable output are essential issues for the power amplifiers. This thesis focuses on the efficiency and back-off power efficiency enhancement and the power amplifiers with automatic gain control loop to provide a stable output. The reactance compensation method is applied to the VHF class-E power amp lifers in chapter 2, and two 10 W and a 100 W broadband power amplifiers were implemented using Freescale laterally diffused metal oxide semiconductor (LDMOS) transistors. The 3 dB fractional bandwidth of 10 W and 100 W power amplifiers reaches 45–175 MHz (123%) and 75–135 MHz (60%) respectively, and the highest efficiency of 10 W and 100 W class-E power amplifiers in the 3 dB fractional bandwidth is 63% at 130 MHz and 76% at 110 MHz respectively, and the highest power gain in the 3 dB fractional bandwidth is 20.8 dB at 105 MHz and 20.4 dB at 100 MHz Gain control range of 10 W class E power amplifier is from 16.6 to 21.4 dB when DC drain voltage varying from 20–50 V. In chapter 3, the automatic gain control loop is applied to the power amplifiers implemented in chapter 2. The automatic gain control loop can alleviate the effect of input power variation on the output power. The output power of the loops are over 10 W and 100 W respectively, and the input dynamic ranges are 4.5 dB at 105 MHz and 4.4 dB at 120 MHz respectively. In chapter 4, the design of Doherty power amplifier is introduced, and a 10 W VHF Doherty power amplifier is implemented by using laterally diffused metal oxide semiconductor (LDMOS). The highest efficiency of the power amplifier measured at 180 MHz reaches 69%, and the efficiency at 6–dB back-off power is 41%, and the 3 dB fractional bandwidth is 50% (130–220 MHz), and the highest power gain in the 3 dB fractional bandwidth is 21.6 dB at 180 MHz, and the output power at 1 dB gain compression point is 30.8 dBm (at 180 MHz), and the output power at third-order intercept point is 46.6 dBm. A K-band Doherty power amplifier is also implemented by PHEMT technology in chapter 4, and the highest small signal gain reaches 7 dB at 26 GHz, but the negligence during the EM simulation results in the difference between simulation and measurement results, and the difference will be discussed in chapter 4. Lastly, the future work and the conclusions are made in chapter 5.

Emerging wireless standards are designed to be spectrally efficient to address the high cost of licensing wireless spectra. Unfortunately, the resulting signals have a high peak-to-average ratio that reduces the base station power amplifier efficiency at the back-off power level. The wasted energy is converted to heat that degrades the device reliability and increases the base-station’s carbon footprint and cooling requirements. In addition, these new standards place stringent re- quirements on the amplifier output power, linearity, efficiency, and bandwidth. To improve the back-off efficiency, a Doherty amplifier, which uses two device in parallel for back-off efficiency enhancement, is deployed in a typical base station. Unfortunately, the conventional Doherty amplifier is narrowband and thus cannot satisfy the bandwidth requirement of the modern base station that needs to support multiple standards and backward compatibility. In this thesis, we begin by studying the class F/F−1 high efficiency mode of operation. To this end, we designed a narrowband, harmonically-tuned 3.3 GHz, 10 W GaN high efficiency amplifier. Next, we investigate how to simultaneously achieve high efficiency and broad bandwidth by harnessing the simplified real frequency technique for the broadband matching network design. A 2 to 3 GHz, 45 W GaN amplifier and a 650 to 1050 MHz, 45 W LDMOS amplifier were designed. Finally, we analyze the conventional Doherty amplifier to determine the cause of its narrow bandwidth. We find that the narrow bandwidth can be attributed to the band-limited quarter-wave transformer as well as the widely adopted traditional design technique. As an original contribution to knowledge, we propose a novel Doherty amplifier configuration with intrinsically broadband characteristics by analyzing the load modulation concept and the conventional Doherty amplifier. The proposed amplifier uses asymmetrical drain voltage biases and symmetrical devices and it does not require a complex mixed-signal setup. To demonstrate the proposed concept in practice, we designed a 700 to 1000 MHz, 90 W GaN broadband Doherty amplifier. Moreover, to show that the proposed concept is applicable to high power designs, we designed a 200 W GaN broadband Doherty amplifier in the same band. In addition, to show that the technique is independent of the device technology, we designed a 700 to 900 MHz, 60 W LDMOS broadband Doherty amplifier. Using digital pre-distortion, the three prototypes were shown to be highly linearizable when driven with wideband 20 MHz LTE and WCDMA modulated signals and achieved excellent back-off efficiency. Lastly, using the insights from the previous analyses, we propose a novel mixed-technology Doherty amplifier with an extended and reconfigurable back-off level as well as an improved power utilization factor. The reconfigurability of the proposed amplifier makes it possible to customize the back-off level to achieve the highest average efficiency for a given modulated signal without redesigning the matching networks. A 790 to 960 MHz, 180 W LDMOS/GaN Doherty amplifier demonstrated the extended bandwidth and reconfigurability of the back-off level. The proposed amplifier addresses the shortcomings of the conventional Doherty amplifier and satisfies the many requirements of a modern base station power amplifier.

随着无线通信的蓬勃发展，新的通信标准不断出现，频谱利用率和数据传输速率提高的同时，传输信号的带宽和均峰比也不断增加。此外，多种通信标准共存的现状要求收发机能够在多个载波频率，高效率地传输不同格式的信号。因此，宽带运行和高效的放大高均峰比信号成为了基站功率放大器设计的基本要求。<br>Doherty 功率放大器结构简单，增加效率的同时能保持中等线性度，故而受到了广泛关注。本文囊括了三个有关增加Doherty 放大器工作带宽、延展高效率区或提高功率利用因子的创新设计。<br>第一个设计中，复数合路阻抗被用于扩宽Doherty 放大器的高效率区。关于动态阻抗范围，电流比因子和漏极效率的理论分析说明，复数合路阻抗可以当作新的自由度来增加放大器的高效率区。为了验证有关理论，以2GHz 为工作频点，我们使用了相同的基于GaN 工艺的晶体管，分别设计了使用复数合路阻抗和纯实数合路阻抗的Doherty 放大器。连续波测试结果显示，使用复数合路阻抗的Dohety 放大器能够提高9.1dB 的输出回退范围，比基于纯实数合路阻抗的传统设计要高3.6dB。此外，使用单载波、均峰比9.6dB 的WCDMA 信号的测试显示，基于复数合路阻抗的设计在输出功率为33.2dBm 时，其平均漏极效率高达57.4%。<br>第二个设计中使用了随频率变化的复数合路阻抗，通过控制漏极电流，来同时增加Doherty 放大器的工作带宽和高效率区。为了验证有关理论，我们设计了输出功率42dBm、工作带宽1.8-2.2GHz、输出回退区9dB 的Doherty 放大器。连续波测试结果显示，在8.5dB 回退点处，该设计在8.5dB 回退点和饱和输出点的漏极效率分别高达55-59%和69-73%。使用单载波、均峰比9.6dB 的WCDMA 信号的测试显示，该设计在输出功率为33.5dBm 时，其平均漏极效率高达53-58%，邻道抑制比也能保持在-30dBc。<br>最后一个设计中，一种在辅助支路加入变换器的Doherty 结构被用于宽带放大。理论分析显示了该结构能够增加功率利用因子，并提供宽带Doherty 特性。为了验证有关理论，我们设计了输出功率20W、工作带宽1.6-2.4GHz、功率利用因子得到改善的Doherty 放大器。连续波测试结果显示，该设计的功率利用因子高达0.94，所有频点均可得到良好的Doherty 效率特性，该设计在6dB回退点和饱和输出点的漏极效率分别高达55-64%和68-76%。在2GHz 处，使用单载波、均峰比6.6dB 的WCDMA 信号的测试显示，该设计在输出功率为37dBm时，其平均漏极效率高达56%，邻道抑制比低于-37dBc。<br>As modern communication system demands higher spectrum efficiency and data rate, new communication standard using complex modulation scheme has emerged and led to transmitting signal with ever-increasing Peak-to-Average Power Ratio (PAPR). Moreover, the co-existence of different standards requires RF transceivers to support signal transmission at multiple carrier frequencies. Therefore, wideband operation and efficient amplification of high PAPR signal are prime requirements for base-station PA design.<br>For efficiency enhancement, the Doherty Power Amplifier (DPA) [1] has been regarded as the most popular approach due to its circuit simplicity and moderate linearity. Three innovative DPA design techniques relating to the enhancement of operating bandwidth, high efficiency range and power utilization factor (PUF) are proposed in this work.<br>In the first demonstration, a novel DPA configuration with Complex Combining Load (CCL) is presented to extend the high efficiency range of the amplifier. Theoretical analysis of dynamic load span, current ratio and drain efficiency reveals that complex combining load can offer a new degree of freedom to boost the Output Back-off (OBO) of DPA. For verification, a 2GHz, equal-cell, GaN HEMT-based DPA is simulated, prototyped and measured with both complex and resistive combining loads. Under Continuous Wave (CW) excitation, measurement results show that the CCL DPA can attain an OBO of 9.1 dB which is 3.6 dB higher than that of the RCL design. In addition, by the use of single-carrier WCDMA signal with PAPR of 9.6 dB and at an average output power of 33.2 dBm, the CCL design is found to deliver an average drain efficiency of 57.4%.<br>The second design presents a novel technique to extend the bandwidth and efficiency range of DPA by the adoption of frequency-varying Complex Combining Load and proper input current control strategy. For verification, a 42 dBm, 1.8-2.2 GHz DPA with OBO of 8.5 dB was designed, built and characterized. Under CW stimulation, a back-off efficiency (8.5 dB) of 55-59% and saturation efficiency of 69-73% were observed over the entire bandwidth. With single carrier WCDMA signal excitation (PAPR of 9.6 dB), an average drain efficiency of 53-58% was obtained at 33.5 dBm average output power and Adjacent Channel Leakage Power Ratio (ACLR) of around -30 dBc.<br>In the last technique, a novel DPA configuration with auxiliary transformer is presented for broadband operation. Theoretical analysis reveals that the presented design can offer enhanced PUF and wideband Doherty behavior. Based on the proposed theory, a 1.6-2.4 GHz, 20 W DPA with improved PUF is designed, simulated and measured. Under CW excitation, measurement results indicate that the presented DPA can achieve a PUF of 0.94, good Doherty behavior over the entire frequency band with a 6 dB back-off efficiency of 55-64% and saturated efficiency of 68-76%. In addition, by the use of single-carrier WCDMA signal (centered at 2 GHz) with PAPR of 6.6 dB and at an average output power of 37 dBm, an average drain efficiency of 56% is obtained with ACLR of better than -37 dBc.<br>Detailed summary in vernacular field only.<br>Detailed summary in vernacular field only.<br>Detailed summary in vernacular field only.<br>Detailed summary in vernacular field only.<br>Detailed summary in vernacular field only.<br>Fang, Xiaohu.<br>Thesis (Ph.D.) Chinese University of Hong Kong, 2015.<br>Includes bibliographical references.<br>Abstracts also in Chinese.

Solid state power amplifiers (SSPAs) evolved significantly over the last few decades, mainly, due to the use of new transistor technologies, such as gallium nitride (GaN) high-electron-mobility transistors (HEMTs), very advanced computer-aided design (CAD) software, and very effective digital pre-distortion (DPD) algorithms. This led to a considerable performance improvement, in terms of energy efficiency, output power, and linearity. To achieve this performance, power amplifier (PA) designers normally push the used transistors very close to their physical safe operating limits, and consider them to operate for a fixed output load. However, the designed PAs are used for many different industrial and/or telecommunication applications, and, in some cases, such as, for example, microwave cooking or massive multiple-input multiple-output (MIMO) fifth generation (5G) base stations (BSs), the output load of these amplifiers can change. Under this nonoptimal scenario, the used transistors will operate for non-nominal loads, and the PAs performance can be severely degraded. Moreover, in highly optimized designs, where the transistors are operated close to their safe limits, their reliability can be reduced or, in extreme cases, they can even be permanently damaged. Therefore, load insensitive PA architectures, and/or techniques that aim at reducing the load variation seen by the PA, are necessary to improve the performance under load varying scenarios. This thesis presents various strategies to improve load insensitiveness of PAs. The presented techniques are based on tunable matching networks (TMNs) and on the amplifiers’ drain supply voltage (VDS) variation. The developed TMNs successfully reduced the load variation seen by the PA, and its performance was greatly improved, for non-optimal loading, by also using the derived load dependent VDS variation. These different approaches were tested and validated on single-ended PAs and then, based on their advantages and disadvantages, the most promising technique – the supply voltage modulation – was selected for the design of a Doherty power amplifier (DPA), which is of paramount importance for telecommunication applications. Moreover, since in some applications the output load variation can be unpredictable, we also developed a complete quasi-load insensitive (QLI) PA system that includes an impedance tracking circuit and an automatic real-time compensation of the amplifier performance.<br>Os amplificadores de potência de estado sólido (SSPAs) evoluíram significativamente nas últimas décadas, principalmente devido à utilização de novas tecnologias de transístores, como os transístores de alta mobilidade (HEMTs) de nitreto de gálio (GaN), de ferramentas muito avançadas de projeto assistido por computador (CAD) e de algoritmos de pré-distorção digital (DPD) muito evoluídos. Isto levou a uma melhoria de desempenho considerável, em termos de eficiência energética, potência de saída e linearidade. Normalmente, para obter estes níveis de desempenho, os engenheiros projetam os amplificadores permitindo que os transístores utilizados operem muito perto do seu limite físico de funcionamento seguro e considerando que vão operar para uma carga fixa. No entanto, os amplificadores projetados são utilizados em diversas aplicações industriais e/ou telecomunicações e, em alguns casos, como por exemplo fornos micro-ondas ou estações base 5G, a sua carga de saída pode variar devido a várias causas, que podem ser previsíveis ou imprevisíveis. Neste cenário não ideal, os transístores utilizados operam para cargas não ótimas e o desempenho dos amplificadores pode ser muito degradado. Além disso, em projetos muito otimizados, onde os transístores são operados perto do seu limite de funcionamento seguro, a sua durabilidade pode ser reduzida ou, em casos extremos, podem até ser permanentemente danificados. Portanto, para melhorar o desempenho dos amplificadores em cenários de carga variável, são necessárias novas arquiteturas e/ou técnicas que visam reduzir a variação da carga vista pelos transístores utilizados. Esta tese apresenta várias estratégias para melhorar a insensibilidade dos amplificadores em relação à variação de carga. As técnicas apresentadas são baseadas em malhas de adaptação dinâmicas (TMNs) e na variação da tensão de alimentação dos amplificadores. As malhas de adaptação desenvolvidas permitiram reduzir a variação de carga vista pelo amplificador e a variação da sua tensão de alimentação permitiu melhorar o desempenho para operação com cargas não ótimas. Estas abordagens foram testadas e validadas em amplificadores baseados num só transístor, e, posteriormente, com base nas suas vantagens e desvantagens, a técnica mais promissora – a modulação da tensão de alimentação – foi selecionada para o projeto de um amplificador Doherty, que é imprescindível para telecomunicações. Além disso, como em algumas aplicações a variação da carga de saída pode ser imprevisível, também desenvolvemos um sistema completo que inclui um circuito de medida de impedância e compensação do desempenho do amplificador em tempo real.<br>Programa Doutoral em Engenharia Eletrotécnica

abstract: The continuing advancement of modulation standards with newer generations of cellular technology, promises ever increasing data rate and bandwidth efficiency. However, these modulation schemes present high peak to average power ratio (PAPR) even after applying crest factor reduction. Being the most power-hungry component in the radio frequency (RF) transmitter, power amplifiers (PA) for infrastructure applications, need to operate efficiently at the presence of these high PAPR signals while maintaining reasonable linearity performance which could be improved by moderate digital pre-distortion (DPD) techniques. This strict requirement of operating efficiently at average power level while being capable of delivering the peak power, made the load modulated PAs such as Doherty PA, Outphasing PA, various Envelope Tracking PAs, Polar transmitters and most recently the load modulated balanced PA, the prime candidates for such application. However, due to its simpler architecture and ability to deliver RF power efficiently with good linearity performance has made Doherty PA (DPA) the most popular solution and has been deployed almost exclusively for wireless infrastructure application all over the world. Although DPAs has been very successful at amplifying the high PAPR signals, most recent advancements in cellular technology has opted for higher PAPR based signals at wider bandwidth. This lead to increased research and development work to innovate advanced Doherty architectures which are more efficient at back-off (BO) power levels compared to traditional DPAs. In this dissertation, three such advanced Doherty architectures and/or techniques are proposed to achieve high efficiency at further BO power level compared to traditional architecture using symmetrical devices for carrier and peaking PAs. Gallium Nitride (GaN) based high-electron-mobility (HEMT) technology has been used to design and fabricate the DPAs to validate the proposed advanced techniques for higher efficiency with good linearity performance at BO power levels.<br>Dissertation/Thesis<br>Doctoral Dissertation Electrical Engineering 2018

碩士<br>國立中央大學<br>電機工程學系<br>106<br>The thesis developed five power amplifiers that were designed in tsmcTM 0.18-µm CMOS, tsmcTM 90-nm CMOS and WINTM 0.25-µm GaN for both X-band and Ka-band operations. The best transistor size and biasing current density of the used transistors were chosen by simulating in different processes. The wideband matching was realized by the magnetically coupling transformer and the enhanced efficiency was realized by using Doherty architecture. Finally, the circuit performance was verified by the measuring small and large signal parameters, such as S-parameters, output power, linearity and modulated signals, etc., The first power amplifier was fabricated in tsmcTM 0.18-µm CMOS technology for X-band operation. This two-stage power amplifier adopted the unilateralization technique which was constructed by a class A amplifier in parallel with class B one to increase the overall output 1-dB compression power (OP1dB) and power added efficiency (PAE). The wide operating bandwidth was achieved by using magnetically coupling Balun for the output matching and T-type matching for the inter-stage matching. The measurement results showed a small signal gain of 20.1 dB, the saturated output power (Psat) and OP1dB are 20.1 dBm and 18.4 dBm, respectively. The peak output power and PAE are improved by the amount of 3.8 dB and 3.4%, respectively, while adopted this composited power amplifier architecture. The chip area is 1.78 (1.95×1.13) mm2. The second and third chips were fabricated in tsmcTM 90-nm CMOS technology for Ka-band operation. Two amplifiers were realized by using unilateralization technique in common-source topology. The input and output matching design followed the previous work and the inter-stage matching was realizes by magnetic transformer. The third power amplifier applied a pre-matching design to minimize the chip size and increase the operating bandwidth. These power amplifiers displayed the gains of 17.43 dB and 14.5dB, respectively. The saturated output powers were measured to 14.73 dBm and 18.4 dBm. The OP1dB were 10.7dBm and 14.5 dBm, respectively. The chip areas are 0.73 (1.41×0.405) mm2 and 0.67 (1.01×0.67) mm2. The fourth chip presents an X-band monolithic microwave integrated circuit (MMIC) binary-combining power amplifier in WINTM 0.25-µm GaN technology. The output of the two-stage CS power amplifiers combined two circuit paths to double the output power and the low impedance combiner reduced the power loss. The measured results exhibited a peak gain of 16.35 dB, a saturation output power of 33.2dBm and an OP1dB of 24.5dBm. The chip area is 3.47 (1.98×1.75) mm2. The fourth chip presents an X-band monolithic microwave integrated circuit (MMIC) binary-combining power amplifier in WINTM 0.25-µm GaN technology. The output of the two-stage CS power amplifiers combined two circuit paths to double the output power and the low impedance combiner reduced the power loss. The measured results exhibited a peak gain of 16.35 dB, a saturation output power of 33.2dBm and an OP1dB of 24.5dBm. The chip area is 3.47 (1.98×1.75) mm2. The last power amplifier also was fabricated in WINTM 0.25-µm GaN technology. A Doherty power amplifier (DPA) adopted a T-type network for the output matching to reduce the chip size and a Lange-coupler for the input matching. The DPA achieved a peak gain of 11.8 dB, a saturation output power of 35.9 dBm, a PAE at 6-dB power back-off of 39.9% and a peak PAE 41.5%. The chip area is 3.03 (1.73×1.75) mm2.

In this thesis, novel designs for adaptive power amplifiers, capable of maintaining excellent performance at dissimilar signal parameters, are presented. These designs result in electronically reconfigurable, single-ended and Doherty power amplifiers (DPA) that efficiently sustain functionality at different driving signal levels, highly varying time domain characteristics and wide-spread frequency bands. The foregoing three contexts represent those dictated by the diverse standards of modern communication systems. Firstly, two prototypes for a harmonically-tuned reconfigurable matching network using discrete radio frequency (RF) microelectromechanical systems (MEMS) switches and semiconductor varactors will be introduced. Following that is an explanation of how the varactor-based matching network was used to develop a high performance reconfigurable Class F-1 power amplifier. Afterwards, a systematic design procedure for realizing an electronically reconfigurable DPA capable of operating at arbitrary centre frequencies, average power levels and back-off efficiency enhancement power ranges is presented. Complete sets of closed-form equations are outlined which were used to build tunable matching networks that compensate for the deviation of the Doherty distributed elements under the desired deployment scenarios. Off-the-shelf RF MEMS switches are used to realize the reconfigurability of the adaptive Doherty amplifiers. Finally, based on the derived closed-form equations, a tri-band, monolithically integrated DPA was realized using the Canadian Photonics Fabrication Centre (CPFC??) GaN500 monolithic microwave integrated circuit (MMIC) process. Successful integration of high power, high performance RF MEMS switches within the MMIC process paved the way for the realization of the frequency-agile, integrated version of the adaptive Doherty amplifier.

碩士<br>國立臺灣大學<br>電信工程學研究所<br>99<br>This research proposes two circuits, one is a Doherty Power Amplifier (DPA), and the other one is a transformer-coupled fully differential power amplifier, both operating at 24 GHz. Although the DPA has been extensively investigated, the effects of DPA at high frequency DPA is still relatively unexplored. Test results, suggest it is hard to achieve high power-added-efficiency (PAE) using DPA construction at higher frequencies. A single-stage 24 GHz DPA fabricated in the TSMC 130-nm CMOS process presented in this thesis, has a measured gain of 6.9 dB, delivered output power is 10 dBm, measured bandwidth is 22.73 % and the chip area is 0.57 mm². However, measured PAE is only 8.3 %, and this single-stage PA consumes 25 mA from a bias voltage of 1.2V. In order to achieve higher PAE and gain without compromising power consumption, I intend to present a differential amplifier with cross-coupled capacitors. To verify this proposed method, a differential circuit and a transformer-coupled fully differential amplifier have been designed for comparison. A simulation test strongly supports the argument that using neutralization technique improves stability. A single-stage PA using this kind of circuit configuration obtains an outstanding bandwidth of 69.6 % vi with same supply voltage, simulated gain is 11.059 dB, PAE is 24.244 % .

碩士<br>國立中山大學<br>通訊工程研究所<br>102<br>This thesis presents a fully integrated transformer-based Doherty power amplifier in a standard 90 nm CMOS process. Doherty architecture has been proposed to enhancement the average efficiency of the transmitter, and improve efficiency under the back-off. There are two parts of this thesis, the first part is to introduce a traditional linearly power amplifier, and realize a fully integrated class A power amplifier at 2.4 GHz. The cascode structure is used in the power cells since the power amplifier is a fully differential design, a balun is utilized to convert between single-ended and differential signals, and to serve as an impedance matching network. The second part is to realize a fully integrated 2.4 GHz Doherty power amplifier. A main amplifier and an auxiliary amplifier are integrated to have a combined output power. A asymmetrical series combining transformer is used to achieve uneven Doherty operation. The Doherty architecture demonstrates efficiency enhancement under back-off, which is important for high peak-to-average-power-ratio communication systems.

碩士<br>國立中正大學<br>電機工程研究所<br>106<br>In this study, a power amplifier is designed for efficiency and linearity by using gallium nitride high electron mobility transistors. The gain of this power amplifier is about 13 dB and the output power is 38 dBm. The architecture of this power amplifier is based on Doherty topology of which having the advantages of high linearity and efficiency. Doherty architecture uses active load modulation technology at output port and combines the characteristics with class AB and class C operations to implement high linearity and efficiency. The final result is that the third-order intermodulation distortion being reduced to be lower than -30 dBc when the output power of the two-tone measurement is 36 dBm and the one-tone input power is 25 dBm. The output power is 38.2 dBm as the efficiency being 41.9 % at 3.2 GHz. The second part of this study is focused on the power amplifier combined with baseband digital pre-distortion methods to improve linearity. This study improves the linearity of power amplifier by taking the memory effects into considerations during employing baseband digital pre-distortion methods. In wireless communication systems, the power amplifier is a crucial component in transmitter. Because of its inherent nonlinear and memory properties, causing signal distorted not only in-band , but also regrowing out-of-band. It affects the power efficiency at the same time. The baseband digital pre-distortion is one of the most effective ways to compensate for distortion. In this study, via Ethernet, Keysight’s SystemVue software was used to control the signal generator and capture the output signals of the power amplifier with the signal analyzer by the software of VSA89600. The resulted power amplifier performance behaves with a EVM value of 1.06% (-39.5 dB) through the assistance of digital pre-distortion.

abstract: This work covers the design and implementation of a Parallel Doherty RF Power Amplifier in a GaN HEMT process for medium power macro-cell (16W) base station applications. This work improves the key parameters of a Doherty Power Amplifier including the peak and back-off efficiency, operational instantaneous bandwidth and output power by proposing a Parallel Doherty amplifier architecture. As there is a progression in the wireless communication systems from the first generation to the future 5G systems, there is ever increasing demand for higher data rates which means signals with higher peak-to-average power ratios (PAPR). The present modulation schemes require PAPRs close to 8-10dB. So, there is an urgent need to develop energy efficient power amplifiers that can transmit these high data rate signals. The Doherty Power Amplifier (DPA) is the most common PA architecture in the cellular infrastructure, as it achieves reasonably high back-off power levels with good efficiency. This work advances the DPA architecture by proposing a Parallel Doherty Power Amplifier to broaden the PAs instantaneous bandwidth, designed with frequency range of operation for 2.45 – 2.70 GHz to support WiMAX applications and future broadband signals.<br>Dissertation/Thesis<br>Masters Thesis Electrical Engineering 2018

碩士<br>國立臺灣大學<br>電信工程學研究所<br>106<br>In wireless communication system, when the microwave signal transmits in the air, the receiver could encounter the signal distortion which causes the decoding error due to the noise interference. Therefore, if we can strengthen the transmitting signal and make better signal-to-noise ratio (SNR) of the signal, we can improve the propability of correct decoding for the reason that how to make the power amplifier deliver more output power in wireless transmitter. Besides the high output power, the demand for high efficiency of power amplifier in wireless communication system has increased because power amplifier consumes the most dc power in the transmitter. Therefore, the optimization of the efficiency becomes a key issue. In this thesis, a 38 GHz power amplifier, a 38 GHz quasi-Doherty power amplifier in 0.15-μm depletion mode GaAs pHEMT MMIC process and a 10 GHz 0.25-μm GaN HEMT Doherty power amplifier are proposed. In chapter 2, a 38 GHz power amplifier in 0.15-μm GaAs pHEMT process is proposed to achieve high power and gain. The proposed PA consists of two stage common-source architecture. However, the device size of the power stage and the driver stage are both selected larger than the traditional design. However, the simulated results also achieve high efficiency and gain. In the measurement, due to the lack of thermal consideration, the S-parameter and power performance is lower than the simulated results. In chapter 3, a 10 GHz 0.25-μm GaN HEMT Doherty power amplifier is proposed to improve the back-off efficiency. The main path consists of common source topology and is biased at class-AB to provide enough gain at small-signal. The auxiliary path also consists of common source topology and is biased at class-C to provide high gain at large-signal and to save dc power consumption for small-signal operation. In addition, the PA module is also simulated and measured in this chapter. However, the output power is the watt-level, so the design should be cared about the thermal effect and measured surrounding. Therefore, we set up the environment as cool as possible. In chapter 4, a 38 GHz quasi-Doherty power amplifier in 0.15-μm is used to improve the back-off efficiency. The major drawbacks of the symmetrical DPA architecture is the low current of the class-C peak amplifier at millimeter wave frequency (MMW). Therefore, the main path and auxiliary path both consist of common source topology, which are biased at class-A and class-AB, respectively. The different to chapter 2 are the load impedance and the bias condition choice of each amplifier and the compensation line of the main path. Besides, the input return loss is different from simulated result. The debug result is provided.