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Relevant bibliographies by topics / Domain-specific hardware accelerator

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Journal articles
Dissertations / Theses
Conference papers

Academic literature on the topic 'Domain-specific hardware accelerator'

Author: Grafiati

Published: 4 June 2021

Last updated: 14 February 2022

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Journal articles on the topic "Domain-specific hardware accelerator"

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Cong, Jason, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, and Glenn Reinman. "Architecture Support for Domain-Specific Accelerator-Rich CMPs." ACM Transactions on Embedded Computing Systems 13, no. 4s (2014): 1–26. http://dx.doi.org/10.1145/2584664.

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Sotiriou-Xanthopoulos, Efstathios, Sotirios Xydis, Kostas Siozios, George Economakos, and Dimitrios Soudris. "A Framework for Interconnection-Aware Domain-Specific Many-Accelerator Synthesis." ACM Transactions on Embedded Computing Systems 16, no. 1 (2016): 1–26. http://dx.doi.org/10.1145/2983624.

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Sunny, Febin P., Asif Mirza, Mahdi Nikdast, and Sudeep Pasricha. "ROBIN: A Robust Optical Binary Neural Network Accelerator." ACM Transactions on Embedded Computing Systems 20, no. 5s (2021): 1–24. http://dx.doi.org/10.1145/3476988.

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Domain specific neural network accelerators have garnered attention because of their improved energy efficiency and inference performance compared to CPUs and GPUs. Such accelerators are thus well suited for resource-constrained embedded systems. However, mapping sophisticated neural network models on these accelerators still entails significant energy and memory consumption, along with high inference time overhead. Binarized neural networks (BNNs), which utilize single-bit weights, represent an efficient way to implement and deploy neural network models on accelerators. In this paper, we pres

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Fang, Jian, Yvo T. B. Mulder, Jan Hidders, Jinho Lee, and H. Peter Hofstee. "In-memory database acceleration on FPGAs: a survey." VLDB Journal 29, no. 1 (2019): 33–59. http://dx.doi.org/10.1007/s00778-019-00581-w.

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Abstract While FPGAs have seen prior use in database systems, in recent years interest in using FPGA to accelerate databases has declined in both industry and academia for the following three reasons. First, specifically for in-memory databases, FPGAs integrated with conventional I/O provide insufficient bandwidth, limiting performance. Second, GPUs, which can also provide high throughput, and are easier to program, have emerged as a strong accelerator alternative. Third, programming FPGAs required developers to have full-stack skills, from high-level algorithm design to low-level circuit impl

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Hosseini, Morteza, and Tinoosh Mohsenin. "Binary Precision Neural Network Manycore Accelerator." ACM Journal on Emerging Technologies in Computing Systems 17, no. 2 (2021): 1–27. http://dx.doi.org/10.1145/3423136.

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This article presents a low-power, programmable, domain-specific manycore accelerator, Binarized neural Network Manycore Accelerator (BiNMAC), which adopts and efficiently executes binary precision weight/activation neural network models. Such networks have compact models in which weights are constrained to only 1 bit and can be packed several in one memory entry that minimizes memory footprint to its finest. Packing weights also facilitates executing single instruction, multiple data with simple circuitry that allows maximizing performance and efficiency. The proposed BiNMAC has light-weight

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Reinehr Gobatto, Leonardo, Pablo Rodrigues, Mateus Saquetti Pereira de Carvalho Tirone, Weverton Luis da Costa Cordeiro, and José Rodrigo Furlanetto Azambuja. "Programmable Data Planes meets In-Network Computing: A Review of the State of the Art and Prospective Directions." Journal of Integrated Circuits and Systems 16, no. 2 (2021): 1–8. http://dx.doi.org/10.29292/jics.v16i2.497.

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Improving network traffic in networks is one of the concerns between networking researchers and network operators since the architecture of modern networks still faces challenges to process large data traffic without the cost of consuming a significant amount of resources not related to computing specifically. On the other hand, network programmability has enabled the development of new applications and network services, from software-defined networking to domain-specific languages created to program network devices and specify their behavior. The development of programmable hardware and hardw

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Schmitt, Christian, Moritz Schmid, Sebastian Kuckuk, Harald Köstler, Jürgen Teich, and Frank Hannig. "Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution." Parallel Processing Letters 28, no. 04 (2018): 1850016. http://dx.doi.org/10.1142/s0129626418500160.

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Not only in the field of high-performance computing (HPC), field programmable gate arrays (FPGAs) are a soaringly popular accelerator technology. However, they use a completely different programming paradigm and tool set compared to central processing units (CPUs) or even graphics processing units (GPUs), adding extra development steps and requiring special knowledge, hindering widespread use in scientific computing. To bridge this programmability gap, domain-specific languages (DSLs) are a popular choice to generate low-level implementations from an abstract algorithm description. In this wor

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Dally, William J., Yatish Turakhia, and Song Han. "Domain-specific hardware accelerators." Communications of the ACM 63, no. 7 (2020): 48–57. http://dx.doi.org/10.1145/3361682.

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Parravicini, Daniele, Davide Conficconi, Emanuele Del Sozzo, Christian Pilato, and Marco D. Santambrogio. "CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching." ACM Transactions on Embedded Computing Systems 20, no. 5s (2021): 1–24. http://dx.doi.org/10.1145/3476982.

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Regular Expression (RE) matching is a computational kernel used in several applications. Since RE complexity and data volumes are steadily increasing, hardware acceleration is gaining attention also for this problem. Existing approaches have limited flexibility as they require a different implementation for each RE. On the other hand, it is complex to map efficient RE representations like non-deterministic finite-state automata onto software-programmable engines or parallel architectures. In this work, we present CICERO , an end-to-end framework composed of a domain-specific architecture and a

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Soldavini, Stephanie, and Christian Pilato. "A Survey on Domain-Specific Memory Architectures." Journal of Integrated Circuits and Systems 16, no. 2 (2021): 1–9. http://dx.doi.org/10.29292/jics.v16i2.509.

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The never-ending demand for high performance and energy efficiency is pushing designers towards an increasing level of heterogeneity and specialization in modern computing systems. In such systems, creating efficient memory architectures is one of the major opportunities for optimizing modern workloads (e.g., computer vision, machine learning, graph analytics, etc.) that are extremely data-driven. However, designers demand proper design methods to tackle the increasing design complexity and address several new challenges, like the security and privacy of the data to be elaborated.This paper ov

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Dissertations / Theses on the topic "Domain-specific hardware accelerator"

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Babecki, Christopher. "A Memory-Array Centric Reconfigurable Hardware Accelerator for Security Applications." Case Western Reserve University School of Graduate Studies / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=case1427381331.

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Ouedraogo, Ganda Stéphane. "Automatic synthesis of hardware accelerator from high-level specifications of physical layers for flexible radio." Thesis, Rennes 1, 2014. http://www.theses.fr/2014REN1S183/document.

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L'internet des objets vise à connecter des milliards d'objets physiques ainsi qu'à les rendre accessibles depuis le monde numérique que représente l'internet d'aujourd'hui. Pour ce faire, l'accès à ces objets sera majoritairement réalisé sans fil et sans utiliser d'infrastructures prédéfinies ou de normes spécifiques. Une telle technologie nécessite de définir et d'implémenter des nœuds radio intelligents capables de s'adapter à différents protocoles physiques de communication. Nos travaux de recherches ont consisté à définir un flot de conception pour ces nœuds intelligents partant de leur mo

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Conference papers on the topic "Domain-specific hardware accelerator"

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Heyn, Toby, Andrew Seidl, Hammad Mazhar, David Lamb, Alessandro Tasora, and Dan Negrut. "Enabling Computational Dynamics in Distributed Computing Environments Using a Heterogeneous Computing Template." In ASME 2011 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2011. http://dx.doi.org/10.1115/detc2011-48347.

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This paper describes a software infrastructure made up of tools and libraries designed to assist developers in implementing computational dynamics applications running on heterogeneous and distributed computing environments. Together, these tools and libraries compose a so called Heterogeneous Computing Template (HCT). The heterogeneous and distributed computing hardware infrastructure is assumed herein to be made up of a combination of CPUs and GPUs. The computational dynamics applications targeted to execute on such a hardware topology include many-body dynamics, smoothed-particle hydrodynam

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Solis, Angel I., and Patrica Nava. "Domain specific architectures, hardware acceleration for machine/deep learning." In Disruptive Technologies in Information Sciences III, edited by Misty Blowers, Russell D. Hall, and Venkateswara R. Dasari. SPIE, 2019. http://dx.doi.org/10.1117/12.2519554.

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Menotti, Ricardo, Joao M. P. Cardoso, Marcio M. Fernandes, and Eduardo Marques. "Automatic generation of FPGA hardware accelerators using a domain specific language." In 2009 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2009. http://dx.doi.org/10.1109/fpl.2009.5272485.

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Reiche, Oliver, Moritz Schmid, Frank Hannig, Richard Membarth, and Jürgen Teich. "Code generation from a domain-specific language for C-based HLS of hardware accelerators." In ESWEEK'14: TENTH EMBEDDED SYSTEM WEEK. ACM, 2014. http://dx.doi.org/10.1145/2656075.2656081.

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