Academic literature on the topic 'Double pass transistor technology'

Abstract In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.

The paper presents a novel 5.15[Formula: see text]GHz–5.825[Formula: see text]GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-[Formula: see text]m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843[Formula: see text]mm2. The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14[Formula: see text]dB power conversion gain, [Formula: see text]6[Formula: see text]dBm input third-order intercept point (IIP3), 6.85[Formula: see text]dB double side band (DSB) noise figure. The total mixer current is about 1.54[Formula: see text]mA from 1.4[Formula: see text]V supply voltage including output buffer. The total dc power consumption is 2.15[Formula: see text]mW.

This paper presents a wideband 4-bit true time delay IC using a 0.25 μm GaN HEMT (High-Electron-Mobility Transistor) process for the beam-squint-free phased array antennas. The true time delay IC is implemented with a switched path circuit topology using DPDT (Double Pole Double Throw) with no shunt transistor in the inter-stages to improve the bandwidth and SPDT (Single Pole Single Throw) switches at the input and the output ports. The delay lines are implemented with CLC π-networks with the lumped element to ensure a compact chip size. A negative voltage generator and an SPI controller are implemented in the PCB (Printed Circuit Board) due to the lack of digital control logic in GaN technology. A maximum time delay of ~182 ps with a time delay resolution of 10.5 ps is achieved at DC–6 GHz. The RMS (Root Mean Square) time delay and amplitude error are <5 ps and <0.6 dB, respectively. The measured insertion loss is <6.8 dB and the input and output return losses are >10 dB at DC–6 GHz. The current consumption is nearly zero with a 3.3 V supply. The chip size including pads is 2.45 × 1.75 mm2. To the authors’ knowledge, this is the first demonstration of a true time delay IC using GaN HEMT technology.

This paper proposes three types of single stage low-power RF front-end, called double-balanced LMVs, by merging LNA, mixer, and voltagecontrolled oscillator (VCO) exploiting a series LC (SLC) network. The low intermediate frequency (IF) or baseband signal can be directly sensed at the drain nodes of the VCO switching transistors by adding a simple resistorcapacitor (RC) low-pass filter (LPF). By adopting a double-balanced mixer topology, the strong leakage of the local oscillator (LO) at the IF output is effectively suppressed. Using a 65 nm CMOS technology, the proposed double-balanced LMVs (DB-LMVs) are designed. Oscillating at around 2.4 GHz ISM band, the phase noise of the proposed three DB-LMVs is −111 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain is larger than 36 dB and the double-side band (DSB) noise figure (NF) is less than 7.7 dB. The DB-LMVs consume only 0.2 mW dc power from 1-V supply voltage.

A high data rate RF-DAC and a power detector (PD) are designed and fabricated in a 250 nm indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. A communication link using the Tx-Rx over polymer microwave fiber (PMF) is measured. The link consists of a pulse amplitude modulation (PAM) modulator and a PD as a demodulator, as well as a one-meter-long dielectric waveguide. The working frequency range of the complete link is verified to be 110–150 GHz. The peak output power of the PAM modulator is 5 dBm, and it has a −3 dB bandwidth of 43 GHz. The PD consists of a parallel connected common emitter configured transistor and a common base configured transistor to suppress the odd-order harmonics at the PD’s output, as well as a stacked transistor to amplify the output signal. Tx and Rx chips, including pads, occupy a total area of only 0.83 mm2. The PMF link can support a PAM-4 signal with 22 Gbps data transmission, and a PAM-2 signal with 30 Gbps data transmission, with a bit error rate (BER) of <10−12, with demodulation performed in real time. Furthermore, the energy efficiency for the link (Tx + Rx) is 4.1 pJ/bit, using digital data input and receiving PAM-2 output (5.6 pJ/bit for PAM-4).

AbstractThis paper presents a fully-integrated direct-conversion fundamentally-operated mixer-first quadrature receiver module with a tunable LO in the 219–266 GHz band. It has been implemented in a 0.13-μm SiGe heterojunction bipolar transistor technology. It includes an on-chip LO path driven externally from the printed circuit board (PCB) connector level at 13.6–16.7 GHz. A hybrid coupler generates the quadrature LO signal, which drives a pair of double-balanced fundamentally-operated down-conversion mixers, whose RF ports are connected to a wideband lens-integrated on-chip ring antenna. The chip-on-lens assembly is placed in the recess of a high-speed PCB and wire-bonded. To compensate the inductive behavior of the wire-bond interconnection between the chip and the PCB at the high-speed IF outputs, an on-board 8-section step-impedance low-pass filter has been implemented. The module shows a 47 GHz 3-dB radio frequency/local oscillator operation bandwidth (BW), a peak conversion gain of 7.8 dB, a single-side-band noise figure of 11.3 dB, and a 3-dB IF BW of 13 GHz. The in-phase and quadrature amplitude imbalance stays below 1.58 dB for the 210–280 GHz band. The down-conversion and the baseband stages consume together 75.5 mW, while the LO path 378 mW. The maximum data-rate achieved with this receiver in combination with the transmitter presented in [1–3] is 60 Gbps for quadrature phase shift keying modulation.

This paper proposes three types of single stage low-power RF front-end, called double-balanced LMVs, by merging LNA, mixer, and voltage-controlled oscillator (VCO) exploiting a series <em>LC </em>(SLC) network. The low intermediate frequency (IF) or baseband signal can be directly sensed at the drain nodes of the VCO switching transistors by adding a simple resistor-capacitor (<em>RC</em>) low-pass filter (LPF). By adopting a double-balanced mixer topology, the strong leakage of the local oscillator (LO) at the IF output is effectively suppressed. Using a 65 nm CMOS technology, the proposed double-balanced LMVs (DB-LMVs) are designed. Oscillating at around 2.4 GHz ISM band, the phase noise of the proposed three DB-LMVs is −111 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain is larger than 36 dB and the double-side band (DSB) noise figure (NF) is less than 7.7 dB. The DB-LMVs consume only 0.2 mW <em>dc</em> power from 1-V supply voltage.

Electrical double-layer (EDL) synaptic transistors based on organic materials exhibit low thermal and chemical stability and are thus incompatible with complementary metal oxide semiconductor (CMOS) processes involving high-temperature operations. This paper proposes organic–inorganic hybrid synaptic transistors using methyl silsesquioxane (MSQ) as the electrolyte. MSQ, derived from the combination of inorganic silsesquioxanes and the organic methyl (−CH3) group, exhibits exceptional thermal and chemical stability, thus ensuring compatibility with CMOS processes. We fabricated Al/MSQ electrolyte/Pt capacitors, exhibiting a substantial capacitance of 1.89 µF/cm2 at 10 Hz. MSQ-based EDL synaptic transistors demonstrated various synaptic behaviors, such as excitatory post-synaptic current, paired-pulse facilitation, signal pass filtering, and spike-number-dependent plasticity. Additionally, we validated synaptic functions such as information storage and synapse weight adjustment, simulating brain synaptic operations through potentiation and depression. Notably, these synaptic operations demonstrated stability over five continuous operation cycles. Lastly, we trained a multi-layer artificial deep neural network (DNN) using a handwritten Modified National Institute of Standards and Technology image dataset. The DNN achieved an impressive recognition rate of 92.28%. The prepared MSQ-based EDL synaptic transistors, with excellent thermal/chemical stability, synaptic functionality, and compatibility with CMOS processes, harbor tremendous potential as materials for next-generation artificial synapse components.

This paper presents a broadband amplifier MMIC based on 0.5 µm InP double-heterojunction bipolar transistor (DHBT) technology. The proposed common-emitter amplifier contains five stages, and bias circuits are used in the matching network to obtain stable high gain in a broadband range. The measurement results demonstrate a peak gain of 19.5 dB at 146 GHz and a 3 dB bandwidth of 56–161 GHz (relative bandwidth of 96.8%). The saturation output power achieves 5.9 and 6.5 dBm at 94 and 140 GHz, respectively. The 1 dB compression output power is −4.7 dBm with an input power of −23 dBm at 94 GHz. The proposed amplifier has a compact chip size of 1.2 × 0.7 mm2, including DC and RF pads.

This paper proposes three kinds of single stage RF front-end, called quadrature LMVs (QLMVs), by merging LNA, single-balanced mixer, and quadrature voltage-controlled oscillator (VCO) exploiting a series LC (SLC) network. The low intermediate frequency (IF) or baseband signal near dc can be directly sensed at the drain nodes of the VCO switching transistors by adding a simple resistor-capacitor (RC) low-pass filter (LPF). Using a 65 nm CMOS technology, the proposed QLMVs are designed. Oscillating at around 2.4 GHz band, the proposed QLMVs achieve the phase noise below ‒107 dB/Hz at 1 MHz offset frequency. The simulated voltage conversion gain is larger than 30 dB. The double-side band (DSB) noise figure (NF) of the proposed QLMVs is below 10 dB. The QLMVs consume less than 0.51 mW dc power from a 1-V supply.

L'objet de notre travail etait de developper et d'etudier une architecture de transistors bipolaires double-polysilicium integrables dans une technologie bicmos 0,35 m. La fabrication des transistors bipolaires double-polysilicium sur plaquette de 200 mm a ete realisee pour la premiere fois en france lors de notre etude, au sein de l'equipe mixte st/cnet/leti. Un important travail de mise au point technologique, couple a une optimisation des performances electriques a ete effectue. L'objectif est de fabriquer des transistor bipolaires performants (le cahier des charges precise une frequence de transition atteignant 25 ghz) tout en restant compatible avec une integration dans une filiere bicmos. Ce travail se situe en amont de l'industrialisation. Differentes etudes ont ete menees : tout d'abord, la mise au point de la structure proprement dite car la topologie des dispositifs est un element cle du bon fonctionnement des transistors. Ensuite, une optimisation des dispositifs a ete realisee dans le but d'ameliorer les resultats electriques : les trois regions du transistor (emetteur, base et collecteur) ont ete etudiees. Deux phenomenes physiques, que sont les courants de fuite et le vieillissement des transistors, ont ete egalement analyses. Enfin, une comparaison des performances de deux architectures, auto-alignee et quasi-auto-alignee, a ete proposee.

Cette these a pour but de mettre en evidence et de mieux comprendre a l'aide de la simulation numerique et de la modelisation analytique les principaux phenomenes physiques pouvant se produire dans les transistors mos-soi sub-0. 1 m. Le premier chapitre est une introduction sur les phenomenes existant dans les transistors mos-soi partiellement et completement desertes et/ou a film extremement mince de silicium. Dans ce chapitre, on detaille aussi le fonctionnement du logiciel (atlas) ainsi que les differents modeles existants. Le deuxieme chapitre est une etude approfondie des effets lies a l'introduction de l'oxyde enterre (effets d'auto-echauffement, kink et transistor bipolaire parasite). Par ailleurs, un modele d'auto-echauffement, valide par l'experience, est propose pour les transistors mos-soi partiellement et completement desertes. Le chapitre 3 donne des solutions pour minimiser les effets de canaux courts (dibl et partage de charges) et les effets de porteurs chauds dans les transistors mos-soi descendant jusqu'a 0. 05 m de longueur de grille. Enfin, l'optimisation des performances des transistors mos-soi sub-0. 1 m est effectuee dans le chapitre 4. La tension de seuil est amelioree en utilisant une grille mid-gap. Par ailleurs, le fonctionnement des composants soi a film ultra-mince de silicium et/ou faiblement dope est etudie. L'accumulation de l'interface arriere permet aussi d'ameliorer les performances electriques tels que la pente en faible inversion ou l'effet dibl. Finalement, le composant donnant les meilleures proprietes electriques dans le domaine sub-0. 1 m (pente sous le seuil ideale, courant de fuite reduit, courant de fonctionnement important, effets de canaux courts et de porteurs chauds reduits,) est le transistor mos-soi a double grille a inversion volumique.

La forte demande et le besoin d’intégration hétérogène de nouvelles fonctionnalités dans les systèmes mobiles et autonomes, tels que les mémoires, capteurs, et interfaces de communication doit prendre en compte les problématiques d’hétérogénéité, de consommation d’énergie et de dissipation de chaleur. Les systèmes mobiles intelligents sont déjà dotés de plusieurs composants de type capteur comme les accéléromètres, les thermomètres et les détecteurs infrarouge. Cependant, jusqu’à aujourd’hui l’intégration de capteurs chimiques dans des systèmes compacts sur puce reste limitée pour des raisons de consommation d’énergie et dissipation de chaleur principalement. La technologie actuelle et fiable des capteurs de gaz, les résistors à base d’oxyde métallique et les MOSFETs (Metal Oxide Semiconductor- Field Effect Transistors) catalytiques sont opérés à de hautes températures de 200–500 °C et 140–200 °C, respectivement. Les transistors à effet de champ à grille suspendu (SG-FETs pour Suspended Gate-Field Effect Transistors) offrent l’avantage d’être sensibles aux molécules gazeuses adsorbées aussi bien par chemisorption que par physisorption, et sont opérés à température ambiante ou légèrement au-dessus. Cependant l’intégration de ce type de composant est problématique due au besoin d’implémenter une grille suspendue et l’élargissement de la largeur du canal pour compenser la détérioration de la transconductance due à la faible capacité à travers le gap d’air. Les transistors à double grilles sont d’un grand intérêt pour les applications de détection de gaz, car une des deux grilles est fonctionnalisée et permet de coupler capacitivement au canal les charges induites par l’adsorption des molécules gazeuses cibles, et l’autre grille est utilisée pour le contrôle du point d’opération du transistor sans avoir besoin d’une structure suspendue. Les transistors monoélectroniques (les SETs pour Single Electron Transistors) présentent une solution très prometteuse grâce à leur faible puissance liée à leur principe de fonctionnement basé sur le transport d’un nombre réduit d’électrons et leur faible niveau de courant. Le travail présenté dans cette thèse fut donc concentré sur la démonstration de l’intégration 3D monolithique de SETs sur un substrat de technologie CMOS (Complementary Metal Oxide Semiconductor) pour la réalisation de la fonction capteurs de gaz très sensible et ultra basse consommation d’énergie. L’approche proposée consiste à l’intégration de SETs métalliques à double grilles dans l’unité de fabrication finale BEOL (Back-End-Of-Line) d’une technologie CMOS à l’aide du procédé nanodamascene. Le système sur puce profitera de la très élevée sensibilité à la charge électrique du transistor monoélectronique, ainsi que le traitement de signal et des données à haute vitesse en utilisant une technologie de pointe CMOS disponible. Les MOSFETs issus de la technologie FD-SOI (Fully Depleted-Silicon On Insulator) sont une solution très attractive à cause de leur pouvoir d’amplification du signal quand ils sont opérés dans le régime sous-le-seuil. Ces dispositifs permettent une très haute densité d’intégration due à leurs dimensions nanométriques et sont une technologie bien mature et modélisée. Ce travail se concentre sur le développement d’un procédé de fonctionnalisation d’un MOSFET FD-SOI comme démonstration du concept du capteur de gaz à base de transistor à double grilles. La sonde Kelvin a été la technique privilégiée pour la caractérisation des matériaux sensibles par le biais de mesure de la variation du travail de sortie induite par l’adsorption de molécules de gaz. Dans ce travail, une technique de caractérisation des matériaux sensibles alternative basée sur la mesure de la charge de surface est discutée. Pour augmenter la surface spécifique de l’électrode sensible, un nouveau concept de texturation de surface est présenté. Le procédé est basé sur le dépôt de réseaux de nanotubes de carbone multi-parois par pulvérisation d’une suspension de ces nanotubes. Les réseaux déposés servent de «squelettes» pour le matériau sensible. L’objectif principal de cette thèse de doctorat peut être divisé en 4 parties : (1) la modélisation et simulation de la réponse d’un capteur de gaz à base de SET à double grilles ou d’un MOSFET FD-SOI, et l’estimation de la sensibilité ainsi que la puissance consommée; (2) la caractérisation de la sensibilité du Pt comme couche sensible pour la détection du H[indice inférieur 2] par la technique de mesure de charge de surface, et le développement du procédé de texturation de surface de la grille fonctionnalisée avec les réseaux de nanotubes de carbone; (3) le développement et l’optimisation du procédé de fabrication des SETs à double grilles dans l’entité BEOL d’un substrat CMOS; et (4) la fonctionnalisation d’un MOSFET FD-SOI avec du Pt pour réaliser la fonction de capteur de H[indice inférieur 2].<br>Abstract : The need of integration of new functionalities on mobile and autonomous electronic systems has to take into account all the problematic of heterogeneity together with energy consumption and thermal dissipation. In this context, all the sensing or memory components added to the CMOS (Complementary Metal Oxide Semiconductor) processing units have to respect drastic supply energy requirements. Smart mobile systems already incorporate a large number of embedded sensing components such as accelerometers, temperature sensors and infrared detectors. However, up to now, chemical sensors have not been fully integrated in compact systems on chips. Integration of gas sensors is limited since most used and reliable gas sensors, semiconducting metal oxide resistors and catalytic metal oxide semiconductor- field effect transistors (MOSFETs), are generally operated at high temperatures, 200–500 °C and 140–200° C, respectively. The suspended gate-field effect transistor (SG-FET)-based gas sensors offer advantages of detecting chemisorbed, as well as physisorbed gas molecules and to operate at room temperature or slightly above it. However they present integration limitations due to the implementation of a suspended gate electrode and augmented channel width in order to overcome poor transconductance due to the very low capacitance across the airgap. Double gate-transistors are of great interest for FET-based gas sensing since one functionalized gate would be dedicated for capacitively coupling of gas induced charges and the other one is used to bias the transistor, without need of airgap structure. This work discusses the integration of double gate-transistors with CMOS devices for highly sensitive and ultra-low power gas sensing applications. The use of single electron transistors (SETs) is of great interest for gas sensing applications because of their key properties, which are its ultra-high charge sensitivity and the ultra-low power consumption and dissipation, inherent to the fundamental of their operation based on the transport of a reduced number of charges. Therefore, the work presented in this thesis is focused on the proof of concept of 3D monolithic integration of SETs on CMOS technology for high sensitivity and ultra-low power gas sensing functionality. The proposed approach is to integrate metallic double gate-single electron transistors (DG-SETs) in the Back-End-Of-Line (BEOL) of CMOS circuits (within the CMOS interconnect layers) using the nanodamascene process. We take advantage of the hyper sensitivity of the SET to electric charges as well from CMOS circuits for high-speed signal processing. Fully depleted-silicon on insulator (FD-SOI) MOSFETs are very attractive devices for gas sensing due to their amplification capability when operated in the sub-threshold regime which is the strongest asset of these devices with respect to the FET-based gas sensor technology. In addition these devices are of a high interest in terms of integration density due to their small size. Moreover FD-SOI FETs is a mature and well-modelled technology. We focus on the functionalization of the front gate of a FD-SOI MOSFET as a demonstration of the DGtransistor- based gas sensor. Kelvin probe has been the privileged technique for the investigation of FET-based gas sensors’ sensitive material via measuring the work function variation induced by gas species adsorption. In this work an alternative technique to investigate gas sensitivity of materials suitable for implementation in DG-FET-based gas sensors, based on measurement of the surface charge induced by gas species adsorption is discussed. In order to increase the specific surface of the sensing electrode, a novel concept of functionalized gate surface texturing suitable for FET-based gas sensors are presented. It is based on the spray coating of a multi-walled-carbon nanotubes (MW-CNTs) suspension to deposit a MW-CNT porous network as a conducting frame for the sensing material. The main objective of this Ph.D. thesis can be divided into 4 parts: (1) modelling and simulation of a DG-SET and a FD-SOI MOSFET-based gas sensor response, and estimation of the sensitivity as well as the power consumption; (2) investigation of Pt sensitivity to hydrogen by surface charge measurement technique and development of the sensing electrode surface texturing process with CNT networks; (3) development and optimization of the DG-SET integration process in the BEOL of a CMOS substrate, and (4) FD-SOI MOSFET functionalization with Pt for H[subscript 2] sensing.

Ce travail a pour but d'etudier les problemes associes a la realisation de circuits cmos analogiques destines a des applications haute frequence (freq. Echant. Sup. Un mhz). La premiere partie traite de la modelisation dynamique du transistor mos. La caracterisation du tmos en hf a l'aide des parametres s a permis de valider un modele petit signal valable pour des frequences atteignant les quelques ghz. La deuxieme partie examine les principaux problemes associes aux structures echantillonnees, telles les capacites commutees (cc). Le probleme de l'injection de charges a pu etre quantifie pour differents interrupteurs par des mesures experimentales. La derniere partie traite de l'amplification et du filtrage a cc a haute frequence. Un filtre elliptique d'ordre cinq a cc, utilisant le principe du double echantillonnage et des nouvelles structures d'interface a ete concu dans une technologie cmos 2

Specifically designed to help candidates revise for the MRCS exam, this book features 250 extended matching questions divided into 96 themes, covering the whole syllabus. Containing everything candidates need to pass the MRCS Part A EMQ section of the exam, the book focuses intensively on topics relating to principles of surgery-in-general, including peri-operative care, post-operative management and critical care, surgical technique and technology, management and legal issues in surgery, clinical microbiology, emergency medicine and trauma management, and principles of surgical oncology. The high level of detail included within the questions and their explanations allows effective self-assessment of knowledge and quick identification of key areas requiring further attention. Varying approaches to extended matching questions are used, giving effective exam practice and guidance through revision and exam technique. This includes clinical case questions, positively-worded questions, requiring selection of the most appropriate of relatively correct answers; 'two-step' or 'double-jump' questions, requiring several cognitive steps to arrive at the correct answer; as well as factual recall questions, prompting basic recall of facts.

AbstractAluminum and alloy tubes are widely used in industrial fields because of the advantage of good corrosion resistance, high thermal conductivity and light weight. Due to the stress corrosion cracking (SCC) and fatigue corrosion cracking (FCC), both inner and outer cracks generates in the aluminum tube. It is still a challenge to inspect all inner and outer surface cracks in the thick-wall aluminum tube in real time by one scan using the nondestructive testing (NDT) method. A double frequency circumferential current field testing (CCFT) method is presented for the inspection of both inner and outer cracks in the aluminum tube in a one pass scan. A simulation model is proposed to extract characteristic signals of inner and outer cracks at two excitation frequencies. The bobbin-type probe is developed and excited by the synthetic double frequency excitation signal. Both inner and outer cracks are tested by the double frequency CCFT system. Results show that both inner and outer cracks can be identified, distinguished and evaluated by the double frequency CCFT method in a one pass scan.

This is the story of the birth of the transistor and of the growing understanding of the theory and technology of solid state devices. The transistor was invented at Bell Laboratories by William Shockley, John Bardeen and Walter Brattain. They received the Nobel Prize in 1956.The next advance was putting more and more units on a substrate, initiating the age of integrated circuits. Moore’s Law in its original form states that the number of transistors on a substrate will double every year. As the price of computers using transistors plummeted, the number of computers sold rose fast.

Abstract This is the first of three chapters devoted to the new physics that has been made accessible with the advent of semiconductor multilayers. We shall be concerned with the quantum-mechanical phenomenon that an electron of total energy less than that of a thin potential barrier might not be reflected, as would always happen classically, but rather might pass through the barrier with an exponentially small but finite probability. Tunnelling has been an exploitable phenomenon in solid state physics for some time, and Josephson junction technology makes intimate use of superconducting tunnel junctions. In a wider sense, many of the leakage currents that plague high-performance devices have, in fact, come from carriers tunnelling through barriers that are undesirably thin. We are now able to control the tunnel barrier thickness precisely and to engineer the current-voltage characteristics. The subject has received an added boost through the discovery of resonant tunnelling involving two potential barriers: for certain. well-defined energies the tunnelling probability is not exponentially small, but approaches unity. Application of a suitable bias to a double-barrier structure can establish the condition of resonant tunnelling with a high current density. A further increase in bias takes the structure off resonance, and the current falls. This gives rise to a new form of negative differential resistance with attractive attributes that we shall describe below. Although it has taken some time, the device spin-offs are now becoming apparent. In the mean time, many physicists have explored nearly every conceivable aspect of resonant tunnelling.

The city of Kuala Lumpur, lying at the junction of the hills of the Main Range (Banjaran Titiwangsa) of Peninsular Malaysia and the coastal plain, has many of the environmental problems that beset the urban areas of Southeast Asia. It has to cope with heavy, intense rainfalls, frequent local nuisance flooding, unstable hillsides, complex foundation conditions, and the impacts of mining and construction activities. The citizens, engineers, and planners of Kuala Lumpur have had to find ingenious solutions in order to live in harmony with their environment. While careful investigation and skilful applications of science and technology has overcome many of the problems, others remain unresolved. The persistent problems arise because the links, and thus responsibilities, associated with changes in one place and impacts elsewhere are not acknowledged and the available understanding of hydrologic and geomorphic systems is not applied. Founded by Kapitan China Yap Ah Loy at the confluence of the Gombak and Klang Rivers in 1857 as a tin-mining settlement (Gullick 1983), Kuala Lumpur quickly outgrew its floodplain and fluvial terrace site to spread onto the adjacent hills. The British resident, Captain Bloomfield Douglas, moved his headquarters to Kuala Lumpur from Klang in 1880 and soon after built his official residence on the hill to the west of the Gombak River, where the prime minister’s residence now stands. So began a tradition of the elite living on the hills which has persisted to the present day. In December 1881 the new township and the surrounding tin mines were hit by floodwaters (Gullick 1983), so establishing the problem of living with fluvial extremes which still besets the city. Virtually every wet season in the first eighty years of Kuala Lumpur’s existence brought some flooding to the town. The river channels became choked with silt carried down from the mines upstream (Gullick 1983). Record rainfall in December 1926 led to a flood 1 m deep in the town centre. After the floods, a new, wider channel, with a double trapezoidal cross-section was built through the town centre. These works enabled a major flood in 1930 to pass through the town without causing any damage (Gullick 1983).

The double-pass configuration of the erbium-doped ZBLAN fiber amplifier is achieved for the first time. The amplification efficiency is ~40% higher than that of the single-pass amplifier, which is significant for compact mid-infrared fiber amplifiers.

We obtain analytical results for the input and output temporal-modes of three different waveguided twin-beam squeezers. Double-pass configurations give perfect inline squeezers where the input and output modes are identical while single-pass configurations do not.