Journal articles: 'Double pass transistor technology'

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Kumar, Raushan, Sahadev Roy, and C. T. Bhunia. "Low-Power High-Speed Double Gate 1-bit Full Adder Cell." International Journal of Electronics and Telecommunications 62, no. 4 (2016): 329–34. http://dx.doi.org/10.1515/eletel-2016-0045.

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Abstract In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.

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Chen, Jun-Da, та Song-Hao Wang. "A Low-Power, High-Gain, and Low-Noise 802.11a Down-Conversion Mixer in 0.35-μm SiGe Bi-CMOS Technology". Journal of Circuits, Systems and Computers 26, № 09 (2017): 1750134. http://dx.doi.org/10.1142/s0218126617501341.

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The paper presents a novel 5.15[Formula: see text]GHz–5.825[Formula: see text]GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-[Formula: see text]m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843[Formula: see text]mm2. The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14[Formula: see text]dB power conversion gain, [Formula: see text]6[Formula: see text]dBm input third-order intercept point (IIP3), 6.85[Formula: see text]dB double side band (DSB) noise figure. The total mixer current is about 1.54[Formula: see text]mA from 1.4[Formula: see text]V supply voltage including output buffer. The total dc power consumption is 2.15[Formula: see text]mW.

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Kim, Jeong-Geun, and Donghyun Baek. "A Wideband True Time Delay Circuit Using 0.25 µm GaN HEMT Technology." Sensors 23, no. 15 (2023): 6827. http://dx.doi.org/10.3390/s23156827.

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This paper presents a wideband 4-bit true time delay IC using a 0.25 μm GaN HEMT (High-Electron-Mobility Transistor) process for the beam-squint-free phased array antennas. The true time delay IC is implemented with a switched path circuit topology using DPDT (Double Pole Double Throw) with no shunt transistor in the inter-stages to improve the bandwidth and SPDT (Single Pole Single Throw) switches at the input and the output ports. The delay lines are implemented with CLC π-networks with the lumped element to ensure a compact chip size. A negative voltage generator and an SPI controller are implemented in the PCB (Printed Circuit Board) due to the lack of digital control logic in GaN technology. A maximum time delay of ~182 ps with a time delay resolution of 10.5 ps is achieved at DC–6 GHz. The RMS (Root Mean Square) time delay and amplitude error are <5 ps and <0.6 dB, respectively. The measured insertion loss is <6.8 dB and the input and output return losses are >10 dB at DC–6 GHz. The current consumption is nearly zero with a 3.3 V supply. The chip size including pads is 2.45 × 1.75 mm2. To the authors’ knowledge, this is the first demonstration of a true time delay IC using GaN HEMT technology.

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Nam-Jin, Oh. "A Single-Stage Low-Power Double-Balanced Mixer Merged with LNA and VCO." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 1 (2017): 152–59. https://doi.org/10.11591/ijece.v7i1.pp152-159.

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This paper proposes three types of single stage low-power RF front-end, called double-balanced LMVs, by merging LNA, mixer, and voltagecontrolled oscillator (VCO) exploiting a series LC (SLC) network. The low intermediate frequency (IF) or baseband signal can be directly sensed at the drain nodes of the VCO switching transistors by adding a simple resistorcapacitor (RC) low-pass filter (LPF). By adopting a double-balanced mixer topology, the strong leakage of the local oscillator (LO) at the IF output is effectively suppressed. Using a 65 nm CMOS technology, the proposed double-balanced LMVs (DB-LMVs) are designed. Oscillating at around 2.4 GHz ISM band, the phase noise of the proposed three DB-LMVs is −111 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain is larger than 36 dB and the double-side band (DSB) noise figure (NF) is less than 7.7 dB. The DB-LMVs consume only 0.2 mW dc power from 1-V supply voltage.

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Strömbeck, Frida, Mingquan Bao, Zhongxia Simon He, and Herbert Zirath. "Transmitter and Receiver Circuits for a High-Speed Polymer Fiber-Based PAM-4 Communication Link." Sensors 22, no. 17 (2022): 6645. http://dx.doi.org/10.3390/s22176645.

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A high data rate RF-DAC and a power detector (PD) are designed and fabricated in a 250 nm indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. A communication link using the Tx-Rx over polymer microwave fiber (PMF) is measured. The link consists of a pulse amplitude modulation (PAM) modulator and a PD as a demodulator, as well as a one-meter-long dielectric waveguide. The working frequency range of the complete link is verified to be 110–150 GHz. The peak output power of the PAM modulator is 5 dBm, and it has a −3 dB bandwidth of 43 GHz. The PD consists of a parallel connected common emitter configured transistor and a common base configured transistor to suppress the odd-order harmonics at the PD’s output, as well as a stacked transistor to amplify the output signal. Tx and Rx chips, including pads, occupy a total area of only 0.83 mm2. The PMF link can support a PAM-4 signal with 22 Gbps data transmission, and a PAM-2 signal with 30 Gbps data transmission, with a bit error rate (BER) of <10−12, with demodulation performed in real time. Furthermore, the energy efficiency for the link (Tx + Rx) is 4.1 pJ/bit, using digital data input and receiving PAM-2 output (5.6 pJ/bit for PAM-4).

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Rodriguez Vazquez, P., J. Grzyb, N. Sarmah, B. Heinemann, and U. R. Pfeiffer. "A 219–266 GHz LO-tunable direct-conversion IQ receiver module in a SiGe HBT technology." International Journal of Microwave and Wireless Technologies 10, no. 5-6 (2018): 587–95. http://dx.doi.org/10.1017/s1759078718000302.

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AbstractThis paper presents a fully-integrated direct-conversion fundamentally-operated mixer-first quadrature receiver module with a tunable LO in the 219–266 GHz band. It has been implemented in a 0.13-μm SiGe heterojunction bipolar transistor technology. It includes an on-chip LO path driven externally from the printed circuit board (PCB) connector level at 13.6–16.7 GHz. A hybrid coupler generates the quadrature LO signal, which drives a pair of double-balanced fundamentally-operated down-conversion mixers, whose RF ports are connected to a wideband lens-integrated on-chip ring antenna. The chip-on-lens assembly is placed in the recess of a high-speed PCB and wire-bonded. To compensate the inductive behavior of the wire-bond interconnection between the chip and the PCB at the high-speed IF outputs, an on-board 8-section step-impedance low-pass filter has been implemented. The module shows a 47 GHz 3-dB radio frequency/local oscillator operation bandwidth (BW), a peak conversion gain of 7.8 dB, a single-side-band noise figure of 11.3 dB, and a 3-dB IF BW of 13 GHz. The in-phase and quadrature amplitude imbalance stays below 1.58 dB for the 210–280 GHz band. The down-conversion and the baseband stages consume together 75.5 mW, while the LO path 378 mW. The maximum data-rate achieved with this receiver in combination with the transmitter presented in [1–3] is 60 Gbps for quadrature phase shift keying modulation.

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7

Oh, Nam-Jin. "A Single-Stage Low-Power Double-Balanced Mixer Merged with LNA and VCO." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 1 (2017): 152. http://dx.doi.org/10.11591/ijece.v7i1.pp152-159.

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This paper proposes three types of single stage low-power RF front-end, called double-balanced LMVs, by merging LNA, mixer, and voltage-controlled oscillator (VCO) exploiting a series LC (SLC) network. The low intermediate frequency (IF) or baseband signal can be directly sensed at the drain nodes of the VCO switching transistors by adding a simple resistor-capacitor (RC) low-pass filter (LPF). By adopting a double-balanced mixer topology, the strong leakage of the local oscillator (LO) at the IF output is effectively suppressed. Using a 65 nm CMOS technology, the proposed double-balanced LMVs (DB-LMVs) are designed. Oscillating at around 2.4 GHz ISM band, the phase noise of the proposed three DB-LMVs is −111 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain is larger than 36 dB and the double-side band (DSB) noise figure (NF) is less than 7.7 dB. The DB-LMVs consume only 0.2 mW dc power from 1-V supply voltage.

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8

Hwang, Tae-Gyu, Hamin Park, and Won-Ju Cho. "Organic–Inorganic Hybrid Synaptic Transistors: Methyl-Silsesquioxanes-Based Electric Double Layer for Enhanced Synaptic Functionality and CMOS Compatibility." Biomimetics 9, no. 3 (2024): 157. http://dx.doi.org/10.3390/biomimetics9030157.

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Electrical double-layer (EDL) synaptic transistors based on organic materials exhibit low thermal and chemical stability and are thus incompatible with complementary metal oxide semiconductor (CMOS) processes involving high-temperature operations. This paper proposes organic–inorganic hybrid synaptic transistors using methyl silsesquioxane (MSQ) as the electrolyte. MSQ, derived from the combination of inorganic silsesquioxanes and the organic methyl (−CH3) group, exhibits exceptional thermal and chemical stability, thus ensuring compatibility with CMOS processes. We fabricated Al/MSQ electrolyte/Pt capacitors, exhibiting a substantial capacitance of 1.89 µF/cm2 at 10 Hz. MSQ-based EDL synaptic transistors demonstrated various synaptic behaviors, such as excitatory post-synaptic current, paired-pulse facilitation, signal pass filtering, and spike-number-dependent plasticity. Additionally, we validated synaptic functions such as information storage and synapse weight adjustment, simulating brain synaptic operations through potentiation and depression. Notably, these synaptic operations demonstrated stability over five continuous operation cycles. Lastly, we trained a multi-layer artificial deep neural network (DNN) using a handwritten Modified National Institute of Standards and Technology image dataset. The DNN achieved an impressive recognition rate of 92.28%. The prepared MSQ-based EDL synaptic transistors, with excellent thermal/chemical stability, synaptic functionality, and compatibility with CMOS processes, harbor tremendous potential as materials for next-generation artificial synapse components.

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9

Hou, Yanfei, Weihua Yu, Qin Yu, et al. "A 56–161 GHz Common-Emitter Amplifier with 16.5 dB Gain Based on InP DHBT Process." Electronics 10, no. 14 (2021): 1654. http://dx.doi.org/10.3390/electronics10141654.

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This paper presents a broadband amplifier MMIC based on 0.5 µm InP double-heterojunction bipolar transistor (DHBT) technology. The proposed common-emitter amplifier contains five stages, and bias circuits are used in the matching network to obtain stable high gain in a broadband range. The measurement results demonstrate a peak gain of 19.5 dB at 146 GHz and a 3 dB bandwidth of 56–161 GHz (relative bandwidth of 96.8%). The saturation output power achieves 5.9 and 6.5 dBm at 94 and 140 GHz, respectively. The 1 dB compression output power is −4.7 dBm with an input power of −23 dBm at 94 GHz. The proposed amplifier has a compact chip size of 1.2 × 0.7 mm2, including DC and RF pads.

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10

Oh, Nam-Jin. "A Single-Stage Quadrature LMVs." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 1 (2018): 124. http://dx.doi.org/10.11591/ijece.v8i1.pp124-132.

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This paper proposes three kinds of single stage RF front-end, called quadrature LMVs (QLMVs), by merging LNA, single-balanced mixer, and quadrature voltage-controlled oscillator (VCO) exploiting a series LC (SLC) network. The low intermediate frequency (IF) or baseband signal near dc can be directly sensed at the drain nodes of the VCO switching transistors by adding a simple resistor-capacitor (RC) low-pass filter (LPF). Using a 65 nm CMOS technology, the proposed QLMVs are designed. Oscillating at around 2.4 GHz band, the proposed QLMVs achieve the phase noise below ‒107 dB/Hz at 1 MHz offset frequency. The simulated voltage conversion gain is larger than 30 dB. The double-side band (DSB) noise figure (NF) of the proposed QLMVs is below 10 dB. The QLMVs consume less than 0.51 mW dc power from a 1-V supply.

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11

Nam-Jin, Oh. "Single-Stage Quadrature LMVs." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 1 (2018): 124–32. https://doi.org/10.11591/ijece.v8i1.pp124-132.

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This paper proposes three kinds of single stage RF front-end, called quadrature LMVs (QLMVs), by merging LNA, single-balanced mixer, and quadrature voltage-controlled oscillator (VCO) exploiting a series LC (SLC) network. The low intermediate frequency (IF) or baseband signal near dc can be directly sensed at the drain nodes of the VCO switching transistors by adding a simple resistor-capacitor (RC) low-pass filter (LPF). Using a 65 nm CMOS technology, the proposed QLMVs are designed. Oscillating at around 2.4 GHz band, the proposed QLMVs achieve the phase noise below ‒107 dB/Hz at 1 MHz offset frequency. The simulated voltage conversion gain is larger than 30 dB. The double-side band (DSB) noise figure (NF) of the proposed QLMVs is below 10 dB. The QLMVs consume less than 0.51 mW dc power from a 1-V supply.

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12

Zhuang, N., M. V. Scotti, and P. Y. K. Cheung. "PTM: Technology mapper for pass-transistor logic." IEE Proceedings - Computers and Digital Techniques 146, no. 1 (1999): 13. http://dx.doi.org/10.1049/ip-cdt:19990244.

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13

Shubat, A. S., J. A. Pretorius, and C. A. T. Salama. "Differential pass transistor logic in CMOS technology." Electronics Letters 22, no. 6 (1986): 294. http://dx.doi.org/10.1049/el:19860200.

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Kishore Kumar, A., D. Somasundareswari, V. Duraisamy, and T. Shunbaga Pradeepa. "Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL." VLSI Design 2013 (March 21, 2013): 1–9. http://dx.doi.org/10.1155/2013/157872.

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Asynchronous adiabatic logic (AAL) is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL) is used to design a low power multiplier. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply. In this work, an 8×8 multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations. To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL) is introduced. The power results of the proposed multiplier design are compared with the conventional CMOS implementation. Simulation results show significant improvement in power for clock rates ranging from 100 MHz to 300 MHz.

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Swathi, Panchadi, and Gudla Bhanu Gupta. "Implementation of 2-bit Multiplier Circuit Using Pass Transistor Logic." International Journal for Research in Applied Science and Engineering Technology 10, no. 7 (2022): 5013–22. http://dx.doi.org/10.22214/ijraset.2022.46100.

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Abstract: In this paper, we implemented 2-bit Multiplier Circuit using Pass Transistor Logic. Pass Transistor Logic is used for high speed technology and is easy to build the basic gate structures. The developed circuit is an extension of pass transistor logic Ex-or gate. The proposed Multiplier circuit is implemented in 2x2 bit multiplier to achieve high speed, low area and less power dissipation. VLSI schematic tool and the analysis is done by using the LT Spice simulator. This paper aims at an optimization of power area and voltages of multiplier to show the better performance. The design is implemented in 0.18um CMOS technology and its functional parameters are compared and the best result is incorporated. Simulation results have been performed on LT Spice tool simulator at 1.8v and 2v supply voltage and simulations are carried out indicate the functionality of the proposed multiplier circuit compared with conventional design to verify the effectiveness and it shows the circuit has low power dissipation at high speeds.

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Yaminikumari, Jampani, and Gudla Bhanu Gupta. "Implementation of 1-bit Full Adder Circuit Using Pass Transistor Logic." International Journal for Research in Applied Science and Engineering Technology 10, no. 7 (2022): 4974–82. http://dx.doi.org/10.22214/ijraset.2022.46097.

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Abstract: In this work, we have implemented 1-bit Full Adder Circuit using Pass Transistor Logic. Pass Transistor Logic is used for high-speed technology and is easy to build the basic gate structures. The developed circuit is an extension of pass transistor logic Ex-or gate. The 1-bit Full Adder Circuit has been performed and obtained I-V characteristics and power for sum and carry were calculated. The effect of scaling on the overall performance is also analysed through the performance evaluation of 1-bit full adder circuit. Simulation results have been performed on LT Spice tool simulator at 1.8v single ended supply voltage and simulations are carried out to indicate the functionality of the proposed full adder circuit compared with conventional design to verify the effectiveness and it shows the circuit has low power dissipation at high speeds.

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Suzuki, M., N. Ohkubo, T. Shinbo, et al. "A 1.5-ns 32-b CMOS ALU in double pass-transistor logic." IEEE Journal of Solid-State Circuits 28, no. 11 (1993): 1145–51. http://dx.doi.org/10.1109/4.245595.

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Chaitanya, S.* Abhishek B. S. Harshavardhan S. Karthik S. Manju T. M. "Design and Analysis of Adders Using Pass Transistor Logic for Multipliers." International Journal of Scientific Research and Technology 2, no. 5 (2025): 326–37. https://doi.org/10.5281/zenodo.15421140.

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This paper demonstrates the design and optimization of a Multiplier using pass transistor logic with half and full adders in 90 nm and 45 nm CMOS technology. The design methodology utilizes fewer transistors and low-power pass transistor logic to improve system efficiency. Implementation and simulation proved these designs to be superior than traditional CMOS designs in terms of area, delay, power dissipation, and energy efficiency. Optimized adders in the multiplier framework thus provide compact, power efficient multiplier design. A comparison to conventional designs shows significant reductions of power consumption, transistor count and delay and is therefore attractive for low-power, high-performance applications. This work contributes to VLSI design by addressing the major speed, area, and power trade-offs in digital systems. The optimized Multiplier is best suited for modern-day applications such as image and signal processing. The application area focuses on high-performance, high-energy efficiency, and clearly points out the advantages pass transistor logic can provide during digital circuit design to innovatively develop low-power, fast multipliers.

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CHANG, ROBERT C., PO-CHUNG HUNG, and HSIN-LEI LIN. "LOW POWER ENERGY RECOVERY COMPLEMENTARY PASS-TRANSISTOR LOGIC." Journal of Circuits, Systems and Computers 15, no. 04 (2006): 491–504. http://dx.doi.org/10.1142/s0218126606003271.

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A proposed adiabatic logic called Energy Recovery Complementary Pass-transistor Logic (ERCPL) is presented in this paper. It operates with a two-phase nonoverlapping power-clock supply. It uses bootstrapping to achieve efficient power saving and eliminates any nonadiabatic losses on the charge-steering devices. A scheme is used to recover part of the energy trapped in the bootstrapping nodes. We compare the energy dissipation between ERCPL and other logic circuits by simulation. Simulation results show that a pipelined ERCPL carry look-ahead adder can achieve a power reduction of 80% over the conventional CMOS case. Operation of an 8-bit ERCPL CLA fabricated using the TSMC 0.35 μm 1P4M CMOS technology has been experimentally verified.

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Morankar, Niraj, Raj Patil, Yash Mahajan, Pranjal Patil, and Santosh Wagaj. "Simulation of Junctionless Transistor for Low Power Mix Circuit." International Journal for Research in Applied Science and Engineering Technology 10, no. 5 (2022): 3874–79. http://dx.doi.org/10.22214/ijraset.2022.43253.

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Abstract: In this work simulation of Double Gate Junction less transistor has been carried out. Comparitive study of the various parameters namely; transconductance(gm), output conductance(gd), DIBL, Subthreshold slope, Ion/Ioff, electric field and Potential. Simulation is carried out in Cogenda Visual TCAD simulator. Comparative study shows using double gate junctionless transistor reduces short channel effect such as DIBL, Subthreshold Slope, Ion/Ioff. Double Gate Junctionless transistor has higher transconductance(gm) and lower output transconductance(gd) compared to conventional junction transistor.

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Morankar, Niraj, Raj Patil, Yash Mahajan, Pranjal Patil, and Santosh Wagaj. "Simulation of Junctionless Transistor for Low Power Mix Circuit." International Journal for Research in Applied Science and Engineering Technology 10, no. 5 (2022): 3874–79. http://dx.doi.org/10.22214/ijraset.2022.43253.

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Abstract: In this work simulation of Double Gate Junction less transistor has been carried out. Comparitive study of the various parameters namely; transconductance(gm), output conductance(gd), DIBL, Subthreshold slope, Ion/Ioff, electric field and Potential. Simulation is carried out in Cogenda Visual TCAD simulator. Comparative study shows using double gate junctionless transistor reduces short channel effect such as DIBL, Subthreshold Slope, Ion/Ioff. Double Gate Junctionless transistor has higher transconductance(gm) and lower output transconductance(gd) compared to conventional junction transistor.

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Pandey, Neeta, Damini Garg, Kirti Gupta, and Bharat Choudhary. "Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style." Journal of Engineering 2016 (2016): 1–10. http://dx.doi.org/10.1155/2016/8027150.

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This paper proposes hybrid dynamic current mode logic (H-DyCML) as an alternative to existing dynamic CML (DyCML) style for digital circuit design in mixed-signal applications. H-DyCML introduces complementary pass transistors for implementation of logic functions. This allows reduction in the stacked source-coupled transistor pair levels in comparison to the existing DyCML style. The resulting reduction in transistor pair levels permits significant speed improvement. SPICE simulations using TSMC 180 nm and 90 nm CMOS technology parameters are carried out to verify the functionality and to identify their advantages. Some issues related to the compatibility of the complementary pass transistor logic have been investigated and the appropriate solutions have been proposed. The performance of the proposed H-DyCML gates is compared with the existing DyCML gates. The comparison confirms that proposed H-DyCML gates is faster than the existing DyCML gates.

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Rao Tirumalasetty, Venkata, C. V. Mohan Krishna, K. Sai Sree Tanmaie, T. Lakshmi Naveena, and Ch Jonathan. "A novel design of high performance1-bit adder circuit at deep sub-micron technology." International Journal of Engineering & Technology 7, no. 1.1 (2017): 660. http://dx.doi.org/10.14419/ijet.v7i1.1.10822.

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In this paper, the design of hybrid 1-bit full adder circuit using both pass transistor and CMOS logic was implemented. Performance pa-rameters such as power, delay, and PDP were compared with the existing designs such as complementary pass-transistor logic, transmis-sion gate adder. At 0.4V supply at 22nm technology, the average power consumption is 1. 525 uW was found to be extremely low with moderately low delay 90. 25 ps and PDP found to be 0.137 fJ. The present implementation has very good improvement in terms of delay, power and power delay product when compared to the existing hybrid 1-bit full adders. Also the number of transistors has been reduced to 13 where as the existiing hybrid full adder circuit has 16 transistors. The proposed circuit was implemented using mentor graphics tool in 45nm, 32nm and 22nm technologies with different supply voltages.

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Doi, Toshiro. "Special Issue on Innovative SiC/GaN/Diamond Single-Crystal Substrates and Planarization Processing Technologies for the Next Generation ICT Society." International Journal of Automation Technology 12, no. 2 (2018): 143–44. http://dx.doi.org/10.20965/ijat.2018.p0143.

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Since the transistor was invented at Bell Laboratories in 1947 and the concept of the integrated circuit was presented by Jack Kilby of TI in 1958, devices using silicon semiconductors have been developed with tremendous drive. Today, ultrastructural, highly dense, and high-functional ULSI devices have become a reality. Accordingly, novel, three-dimensional devices that aim at multiple functions and high performance have been proposed, and novel materials have come into existence. As Artificial Intelligence (AI) has drawn increasing attention, the concept of “Singularity,” or singular technical point, has become a focus of great attention. Singularity is a prediction put forth by American futurist Ray Kurzweil, who said, “Singularity will come in 2045, when the speed of the evolution of technology will become infinite and Artificial Intelligence will exceed human intelligence.” This prediction is said to have its roots in “Moore’s law,” formulated by Intel founder Gordon Moore, which states that “the degree of integration of transistors doubles every year and a half.” The deep learning and self-learning functions of computers can be mentioned as significant driving factors behind the dramatic development of AI studies. The processing capacity of AI has increased exponentially owing to the evolution and combination of various technologies, and the speed of development of technology now far exceeds the biological limits of humankind. As a result, it is inevitable that “Singularity” will come to pass, and the technologies behind semiconductor devices contributing to the arrival of Singularity are expected to develop much further. In the process of such semiconductor development, silicon carbide (SiC), among other materials, came to be expected as the next-generation semiconductor in the 1950s, but it could not succeed significantly as a practical device. SiC also attracted attention as the material used in green and red light-emitting elements. In the 1990s, SiC came into the spotlight, along with gallium nitride (GaN) crystal and other materials, by being put into practical use as the material used in blue light-emitting diodes. Today, as the silicon (Si) as power devices have already approached the physical limits of the material, next-generation devices focus on semiconductor substrates such as SiC and GaN, which have performance indexes tens to thousands of times higher than the Si semiconductor. Especially, high-power devices and high-frequency devices have attracted special attention, because the use of semiconductor devices in the automotive and other fields has increased dramatically. Furthermore, the single-crystal substrate of semiconducting diamond is considered to be the ultimate semiconductor device, so this topic has been vigorously researched. The above-mentioned next-generation devices are called green devices because they could reduce power consumption and carbon dioxide emissions tremendously, leading to the realization of a low-carbon and energy-saving society. Such devices are utilized not only as high-power semiconductors and light-emitting semiconductors but also as various sensors, including gas sensors and UV sensors, as well as MEMS devices. Further application of such devices is expected in the future. To actually produce the high-performance and multifunctional green devices, it will be necessary to establish the technologies for device integration and the manufacturing process. An example would be the process of growing crystals that are larger in diameter and higher in quality. The substrate materials applied in such technologies, including SiC, GaN, and diamond, are known as ultra-hard-to-process materials: their extreme mechanical and chemical stability makes the general manufacturing process much more difficult. A breakthrough is needed to solve this problem. Many challenges must be overcome systematically to produce a high-performance green device, as the device to which such crystalline materials are applied will reduce power consumption and carbon dioxide emissions extremely effectively. This special issue focuses on manufacturing processes, including the planarization processing of every kind of hard-to-process crystal substrate, involved in producing green devices, sensors, etc. And the paper on the various applications of the device are published in this issue. This issue is expected to contribute to the establishment of a process for manufacturing green devices, which is an essential industrial strategy, as well as to future intensive studies in this field.

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Blakiewicz, Grzegorz. "Low-Voltage LDO Regulator Based on Native MOS Transistor with Improved PSR and Fast Response." Energies 16, no. 12 (2023): 4825. http://dx.doi.org/10.3390/en16124825.

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In this paper, a low-voltage low-dropout analog regulator (ALDO) based on a native n-channel MOS transistor is proposed. Application of the native transistor with the threshold voltage close to zero allows elimination of the charge pump in low-voltage regulators using the pass element in a common drain configuration. Such a native pass transistor configuration allows simplification of regulator design and improved performance, with supply voltages below 1 V, compared to commonly used regulators with p-channel MOS transistors. In the presented design of ALDO regulator in 180 nm CMOS X-FAB technology, an output voltage of 0.7 V was achieved with an output current of 10 mA and a supply voltage of 0.8 V. Simulation results show that despite the low supply voltage, output voltage spikes do not exceed 70 mV at the worst technology corner when output current transients from 100 µA to 10 mA. Under such conditions, stable operation and power supply rejection PSR = 35 dB were achieved with an output capacitance of 0–500 pF. The proposed regulator allows to push the limit of ALDO regulator applications to voltages below 1 V with only slight degradation of its performance.

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Yanbin Jiang, S. S. Sapatnekar, and C. Bamji. "Technology mapping for high-performance static CMOS and pass transistor logic designs." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9, no. 5 (2001): 577–89. http://dx.doi.org/10.1109/92.953492.

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Yin, Ningyuan, Wanyuan Pan, Yihe Yu, Chengcheng Tang, and Zhiyi Yu. "Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier." Electronics 12, no. 15 (2023): 3209. http://dx.doi.org/10.3390/electronics12153209.

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With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and multiplier circuits due to the low count of transistors and low-power characteristics. In this paper, we present a novel full adder based on pass transistors. The proposed full adder consists of 18 transistors. The post-layout simulation shows a 13.78% of power reduction compared to conventional CMOS full adders. Moreover, we propose an 8-bit signed multiplier based on the proposed full adder. The post-layout simulation shows an 8% power reduction compared to the multiplier produced by the Design Compiler synthesis tool. Compared to the existing work with a similar process, our work achieved only 19.02% of the power-delay product and 3.5% of the area-power product.

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Swati, Narang. "PERFORMANCE ANALYSIS OF A LOW-POWER HIGH-SPEED HYBRID 1-BIT FULL ADDER CIRCUIT AND ITS IMPLEMENTATION." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 8 (2017): 200–208. https://doi.org/10.5281/zenodo.839170.

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In this paper, a hybrid low power and high speed 1-bit full adder design employing both complimentary metal oxide (CMOS) logic and transmission gate logic is reported. The design was implemented for 1 bit. The circuit was implemented using Mentor tanner tool in 180 and 90 nm technology. Performance parameters such as power, delay and transistor count were compared with existing designs such as complimentary pass transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS logic output drive full adder , and so on. For 1.8-V supply at 180-nm technology, the average power consumption (0.40893 uW) was found to be extremely low with moderately low delay (7.0975 ps) resulting from the incorporation of strong transmission gates. Corresponding values of the same were 0.1265uW and 13.439ps at 90-nm technology operating at 1.2-V supply voltage.. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed. The design was further extended for implementing 2 bit multiplier also as an application of our proposed design

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Lu, Bin Bin, and Jian Ping Hu. "Complementary Pass-Transistor Adiabatic Logic Using Dual Threshold CMOS Techniques." Applied Mechanics and Materials 39 (November 2010): 55–60. http://dx.doi.org/10.4028/www.scientific.net/amm.39.55.

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With rapid technology scaling down, the energy dissipation of nanometer CMOS circuits is becoming a major concern, because of the increasing sub-threshold leakage in nanometer CMOS processes. This paper introduces a dual threshold CMOS (DTCMOS) technique for CPAL (complementary pass-transistor adiabatic logic) circuits to reduce sub-threshold leakage dissipations. The method to size the transistors of the dual-threshold CPAL gates is also discussed. A full adder using dual-threshold CPAL circuits is realized using 45nm BSIM4 CMOS model. HSPICE simulation results show that leakage dissipations of the CPAL full adder with DTCMOS techniques are reduced compared with the basic CPAL one.

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Gupta, Priya, Anu Gupta, and Abhijit Asati. "Leakage Immune Modified Pass Transistor Based 8T SRAM Cell in Subthreshold Region." International Journal of Reconfigurable Computing 2015 (2015): 1–10. http://dx.doi.org/10.1155/2015/749816.

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The paper presents a novel 8T SRAM cell with access pass gates replaced with modified PMOS pass transistor logic. In comparison to 6T SRAM cell, the proposed cell achieves 3.5x higher read SNM and 2.4x higher write SNM with 16.6% improved SINM (static current noise margin) distribution at the expense of 7x lower WTI (write trip current) at 0.4 V power supply voltage, while maintaining similar stability in hold mode. The proposed 8T SRAM cell shows improvements in terms of 7.735x narrower spread in average standby power, 2.61x less in averageTWA(write access time), and 1.07x less in averageTRA(read access time) at supply voltage varying from 0.3 V to 0.5 V as compared to 6T SRAM equivalent at 45 nm technology node. Thus, comparative analysis shows that the proposed design has a significant improvement, thereby achieving high cell stability at 45 nm technology node.

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Panahifar, Ehsan, and Alireza Hassanzadeh. "A Modified Signal Feed-Through Pulsed Flip- Flop for Low Power Applications." International Journal of Electronics and Telecommunications 63, no. 3 (2017): 241–46. http://dx.doi.org/10.1515/eletel-2017-0032.

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AbstractIn this paper a modified signal feed-through pulsed flip-flop has been presented for low power applications. Signal feed-through flip-flop uses a pass transistor to feed input data directly to the output. Feed through transistor and feedback signals have been modified for delay, static and dynamic power reduction. HSPICE simulation shows 22% reduction in leakage power and 8% of dynamic power. Delay has been reduced by 14% using TSMC 90nm technology parameters. The proposed pulsed flip-flop has the lowest PDP (Power Delay Product) among other pulsed flip-flops discussed.

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Manikandan, P., and B. Bindu. "High-PSR Capacitorless LDO with Adaptive Circuit for Varying Loads." Journal of Circuits, Systems and Computers 29, no. 11 (2020): 2050178. http://dx.doi.org/10.1142/s0218126620501789.

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A capacitorless low-drop-out (LDO) regulator with an NMOS pass transistor-based adaptive network to achieve high and constant power-supply rejection (PSR) for varying loads is presented. The proposed LDO does not require an external capacitor making it suitable for System-on-Chip (SoC) applications. The low-frequency PSR of the LDO varies with load current as the transconductance and output conductance of the power transistor depend on the load current. The proposed LDO is capable of maintaining a constant and high PSR for varying loads by using an adaptive network. The NMOS pass transistor in the adaptive network tracks the power-supply noise through the power transistor and bypasses this noise current through it to the ground. This helps to avoid the flow of this noise current through the load and thus the circuit can achieve high and constant PSR for varying loads. The LDO with adaptive network achieves very high power-supply rejections of [Formula: see text][Formula: see text]dB at low frequencies and [Formula: see text][Formula: see text]dB at 1[Formula: see text]MHz, for a load current of 4[Formula: see text]mA. This LDO is implemented in 0.18-[Formula: see text]m CMOS technology and consumes 1.35-mW quiescent power over the range of 1–10[Formula: see text]mA of the load current.

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Abuishmais, Ibrahim, Fadi R. Shahroury, and Hani Ahmad. "A Design Methodology of High-Efficiency Dimmable Current Sink for Current-Regulated Drivers." Electronics 11, no. 16 (2022): 2566. http://dx.doi.org/10.3390/electronics11162566.

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This paper proposes a high-efficiency and dimmable current sink topology along with a design methodology for low node processes. The design methodology is demonstrated using a boost-based WLED driver application. In this work, the focus is on current regulation rather than voltage regulation. Therefore, the proposed topology exploits a smaller and faster NMOS pass device, replacing the conventional PMOS-based LDO arrangement. An amplifier-boosted pass-transistor current sink topology combined with a 5-bit programmable degenerated source resistor is being utilized for high-efficiency and brightness control. The realized WLED driver validates the proposed topology and the design methodology utilizing 40 nm CMOS TSMC technology. The design takes advantage of the programmability of the resistor to enhance the system’s power efficiency. This programmable resistor enables dimmability via current segmentation with a 1 mA step for a total of 25 mA. For a 500 mV voltage ripple at the DC-DC converter output driving 6 WLEDs with a 3.2 V forward voltage drop each, a worst-case current ripple of 200 µA and simulated efficiency of 97.6% is achieved for optimum pass-transistor size.

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Masud, Muhammad I., Iqbal A. Khan, Syed Abdul Moiz, and Waheed A. Younis. "Novel Second-Order Fully Differential All-Pass Filter Using CNTFETs." Micromachines 14, no. 10 (2023): 1873. http://dx.doi.org/10.3390/mi14101873.

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In this paper, a new carbon nanotube field effect transistor (CNTFET)-based second-order fully differential all-pass filter circuit is presented. The realized filter uses CNTFET-based transconductors and grounded capacitors. An active-only second-order fully differential all-pass filter circuit topology is also presented by replacing the grounded capacitance with a CNTFET-based varactor to achieve filter tunability. By controlling the varactor capacitance, active-only second-order fully differential all-pass filter tunability in the range of 15 GHz to 27.5 GHz is achieved. The proposed active-only circuit works on -oltage, low-power dissipation and high tunable pole frequency. The realized circuit operations are verified through the HPSPICE simulation tool. Deng’s CNTFET model is utilized to verify the filter performances at the 16 nm technology node. It is seen that the proposed filter simulation justifies the theoretical predictions and works efficiently in the deep-submicron technology.

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Weimann, Nils G., V. Houtsma, Y. Yang, et al. "InP double-hetero bipolar transistor technology for 130 GHz clock speed." physica status solidi (c) 3, no. 3 (2006): 452–55. http://dx.doi.org/10.1002/pssc.200564169.

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Carta, Fabio, Htay Hlaing, Hassan Edrees, Shyuan Yang, Mingoo Seok, and Ioannis Kymissis. "Co-development of complementary technology and modified-CPL family for organic digital integrated circuits." MRS Proceedings 1795 (2015): 19–25. http://dx.doi.org/10.1557/opl.2015.564.

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ABSTRACTWe present a novel logic family alternative to classic CMOS logic and its experimental demonstration for digital application of organic electronics. The proposed logic family is a modified version of the complementary pass-transistor logic (mCPL), which allows use of a stronger transistor (in our case the p-FET) to provide more of the current required to switch the capacitance in the device. We report the integration and characterization of this new class of gates and compare them with the equivalent CMOS structures. The characterization of inverters shows improved tolerance to process variation, up to 2.5× better delay, and 1.7× smaller area for the mCPL devices. Comparison of NOR and NAND gates shows 1.8× and 4.1× reduced gate delay. A 3× reduced energy consumption per operation is also simulated. The improved performance of the mCPL design makes it an alternative architecture for logic application of organic electronics.

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Abhinav, V. Deshpande. "OFFSET REDUCTION IN THE DOUBLE TAILED LATCH-TYPE VOLTAGE SENSE AMPLIFIER." International Journal of Advanced Trends in Engineering and Technology 4, no. 2 (2019): 1–5. https://doi.org/10.5281/zenodo.3336352.

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This research paper presents an improved double tailed latch type voltage sense amplifier by using a latch load in the first stage. A latch load at the first stage provides the second stage with a large input difference voltage. Thus, completely removes the offset voltage due to the mismatch in the transistor pairs in the second stage of the Sense Amplifier. The performance of the Sense Amplifier was simulated by using the LT Spice with a threshold mismatch of 10% in between the transistor pairs of the second stage, where it achieved the offset removal at 3 GHz clock rate with VDD = 1. 2 Volts in a 90 nm CMOS technology. Since the input transistors of the first stage are in parallel with the transistor pair of the latch, it does not affect the delay.

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G., S. Nimitha, G. Madan, Murthy R. Adiga Krishna, and Dhanya U. Sai. "Design of Absorptive Bandstop Filter using 180nm Bi-CMOS Technology." Journal of Advancement in Electronics Design 6, no. 3 (2023): 23–31. https://doi.org/10.5281/zenodo.10394694.

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Wideband communications, radar, and sensing applications are becoming increasingly popular due to the development of software-defined wideband amplifiers, ADCs, DACs, and radios. For these applications it is often necessary to minimize the amount and magnitude of harmonics with the spurious content of the transmitter signal while maintaining the best possible dynamic range and sensitivity in the receiver signal. It has been found that radio waves cause reflections of RF power as they pass through a notch filter, which can damage previous stages of operation. An integrated absorption/reflection notch filter is implemented in this project. Since it has both CMOS transistor and bipolar junction transistor characteristics, we use Bi-CMOS technology to achieve this. Bi-CMOS works faster and consumes less power. Using 180nm technology and LTSpice software, we will combine these technologies into a single chip. It has been determined that the bandstop filter has a center frequency of 315MHz, a bandwidth of 14MHz and a quality factor of 22.5. Close agreement between the theoretical and simulated results for this integrated absorptive bandstop filter is achieved.

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B S, Vinayashree, and Santhosh Babu K C. "Layout Design of Row Decoder using Cadence." International Journal for Research in Applied Science and Engineering Technology 10, no. 8 (2022): 461–68. http://dx.doi.org/10.22214/ijraset.2022.46214.

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Abstract: Logic circuits, data transport circuits, and analogue to digital conversions all frequently employ decoders. For the line decoders, a mixed logic design approach incorporating transmission gate logic, pass transistor logic, and complementary metaloxide semiconductor (CMOS) technology is employed to achieve the desired performance and operation. A unique topology is proposed for the 2 to 4 decoders, which calls for a topology with fourteen transistors to reduce operating power and transistor count and a topology with fifteen transistors to achieve high power and low delay performance. For a total of four new designs, standard and inverting decoders are created for each situation. All of the suggested decoders have a low transistor count in comparison to their traditional CMOS architectures. Last but not least, a number of suggested solutions demonstrate a notable improvement in operating power and propagation latency, exceeding CMOS in virtually all instances

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Zainol Murad, Sohiful Anuar, Azizi Harun, Mohd Nazrin Md Isa, Saiful Nizam Mohyar, and Jamilah Karim. "A VERY LOW-DROPOUT VOLTAGE REGULATOR IN 0.18-M CMOS TECHNOLOGY FOR POWER MANAGEMENT SYSTEM." Jurnal Teknologi 82, no. 6 (2020): 11–19. http://dx.doi.org/10.11113/jurnalteknologi.v82.15031.

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This paper proposes the design of a very low-dropout (LDO) voltage regulator in 0.18-mm CMOS technology. The proposed LDO regulator consists of voltage reference, symmetrical operational transconductance amplifier (OTA), PMOS transistor, resistive feedback network and output capacitor. The NMOS symmetrical OTA is implemented as an error amplifier and a PMOS transistor is employed as a pass device to improve gain and minimize low dropout voltage, respectively. The proposed design is simulated using Spectre simulator in Cadence software to verify its regulator performance. The simulation results show that the proposed LDO is capable to operate from a supply voltage of 1.7-2.0 V with a low dropout voltage of 19.3 mV at a maximum 50 mA load current to regulate output voltage 1.5 V. The active chip is 2.96 mm2 in size. The performance of the proposed LDO is suitable to enhance power management for system on chip (SoC) applications.

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Kumngern, Montree, Fabian Khateb, and Tomasz Kulej. "0.5 V, Low-Power Bulk-Driven Current Differencing Transconductance Amplifier." Sensors 24, no. 21 (2024): 6852. http://dx.doi.org/10.3390/s24216852.

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This paper presents a novel low-power low-voltage current differencing transconductance amplifier (CDTA). To achieve a low-voltage low-power CDTA, the BD-MOST (bulk-driven MOS transistor) technique operating in a subthreshold region is used. The proposed CDTA is designed in 0.18 µm CMOS technology, can operate with a supply voltage of 0.5 V, and consumes 1.05 μW of power. The proposed CDTA is used to realize a current-mode universal filter. The filter can realize five standard transfer functions of low-pass, band-pass, high-pass and band-stop, and all-pass from the same circuit. Neither component-matching conditions nor input signals of the inverse type are required to realize these filter functions. The current-mode filter offers low-input and high-output impedance and uses grounded capacitors. The natural frequency and quality factor of the filters can be orthogonally controlled. The proposed CDTA and its applications are simulated using SPICE to confirm the feasibility and functionality of the new circuits.

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Pavan Kumar, Chinnala, and K. Sivani. "Design of a Double Gate Tunneling Field Effect Transistor (DG-TFET) and Performance Analysis." Journal of Integrated Circuits and Systems 19, no. 2 (2024): 1–12. http://dx.doi.org/10.29292/jics.v19i2.762.

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The Double-Gate Tunnel Field-Effect Transistor (DG-TFET) has emerged as a promising contender in modern semiconductor technology, offering distinct advantages over conventional devices. This paper delves into the pivotal performance metrics of DG-TFETs: sub-threshold slope (SS), ON current (Ion), and work function modulation, which collectively contribute to heightened device functionality.Sub-threshold slope, a critical parameter for energy efficiency, sees significant enhancement in DG-TFETs owing to their inherent ability to precisely control the tunneling barrier. The incorporation of dual gates enables precise tuning of the tunneling process, resulting in steeper SS values compared to traditional devices. This attribute is crucial in minimizing leakage currents during device operation, thus ensuring superior power efficiency.Additionally, the ON current of DG-TFETs serves as a vital indicator of their switching prowess. The dual-gate architecture facilitates enhanced electrostatic control, leading to heightened ON current levels. This aspect is pivotal for achieving faster switching speeds, thereby ensuring seamless integration into high-performance circuits.Work function modulation stands out as a key feature in DG-TFETs, facilitating tailored band alignments and improved device characteristics. Through independent adjustment of the work functions of the source and drain regions, the device can be finely tuned to optimize tunneling efficiency and overall performance. This capability holds significant implications for circuit design and customization, augmenting the versatility of DG-TFETs.In essence, the Double-Gate Tunnel Field-Effect Transistor presents a compelling avenue for advancing semiconductor technology. By addressing sub-threshold slope, enhancing ON current, and modulating work functions, DG-TFETs offer a promising solution for achieving higher energy efficiency, faster switching speeds, and versatile device optimization. As the semiconductor landscape continues to evolve, DG-TFETs hold substantial potential for shaping the future of integrated circuits and electronic devices.This study involves the design and evaluation of three distinct transistor configurations: a conventional Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a Single Gate Tunnel Field-Effect Transistor (TFET), and a Double Gate TFET. The mentioned devices are simulated using Silvaco TCAD (Technology Computer Aided Design) tools. The evaluation primarily focuses on key performance metrics, specifically sub-threshold slope and ON current, to comprehensively assess the effectiveness of the Double Gate TFET.

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Othman, M. Y., B. Yatim, K. Sopian, and M. N. A. Bakar. "Double-Pass Photovoltaic-Thermal Solar Collector." Journal of Energy Engineering 132, no. 3 (2006): 121–26. http://dx.doi.org/10.1061/(asce)0733-9402(2006)132:3(121).

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Yi, Boram, Chang-Yong Lee, Jin-Hwan Oh, Boung Jun Lee, Sungkyu Seo, and Ji-Woon Yang. "Analytical Model of the Parasitic Bipolar Junction Transistor in Low-Doped Double-Gate FinFETs for Pass-Gate Circuits." IEEE Transactions on Electron Devices 63, no. 10 (2016): 3864–68. http://dx.doi.org/10.1109/ted.2016.2600625.

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Beg, Parveen. "Tunable First-Order Resistorless All-Pass Filter with Low Output Impedance." Scientific World Journal 2014 (2014): 1–6. http://dx.doi.org/10.1155/2014/219453.

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This paper presents a voltage mode cascadable single active element tunable first-order all-pass filter with a single passive component. The active element used to realise the filter is a new building block termed as differential difference dual-X current conveyor with a buffered output (DD-DXCCII). The filter is thus realized with the help of a DD-DXCCII, a capacitor, and a MOS transistor. By exploiting the low output impedance, a higher order filter is also realized. Nonideal and parasitic study is also carried out on the realised filters. The proposed DD-DXCCII filters are simulated using TSMC the 0.25 µm technology.

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Rajitha, J. "Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits." International Journal for Research in Applied Science and Engineering Technology 12, no. 2 (2024): 1042–48. http://dx.doi.org/10.22214/ijraset.2024.58495.

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Abstract: In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in turn helps in bettering the performance of the electronics circuits which follow adder circuits. The low power VLSI design is of great importance due to portable electronic products. Full adder is a type of adder circuit that adds three inputs and gives two outputs. Out of three, two will be the present inputs and the third input will be the carry from the previous stage. ‘A’ and ‘B’ are the actual inputs, ‘C’ is the carry from the previous operation. SUM and CARRY OUT are the two outputs. In this work, Design and Implementation of full adder using conventional CMOS design and Pass Transistor Logic based Full adder circuits are carried out. At last comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Cadence Virtuoso Tool is used in design and simulation conventional CMOS design and Pass Transistor Logic based Full adder circuits. The entire work is simulated in 180nm CMOS technology.

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Khateb, Fabian, Montree Kumngern, Tomasz Kulej, and Jiri Vavra. "A 328 nW, 0.45 V Current Differencing Transconductance Amplifier and Its Application in a Current-Mode Universal Filter." Applied Sciences 15, no. 7 (2025): 3471. https://doi.org/10.3390/app15073471.

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This paper presents a low-voltage, low-power current differencing transconductance amplifier (CDTA) utilizing the bulk-driven MOS transistor technique in the subthreshold region for reduced voltage and power consumption. The proposed CDTA includes a z-copy terminal, which enhances its functionality in current-mode circuit applications. Designed in the Cadence Virtuoso environment using 0.18 µm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC), the amplifier operates with a supply voltage of 0.45 V and consumes 328 nW of power, with a bias current set to 10 nA. The current bandwidth and offset of the CDTA are 35 kHz and 0.3 nA, respectively. To demonstrate its performance, the CDTA is applied in a current-mode universal filter, which can realize low-pass, band-pass, high-pass, band-stop, and all-pass responses within a single topology. This design eliminates issues related to inverting input signals, input signal matching, or the need for multiple input signals. Additionally, the natural frequency of these filtering functions can be electronically controlled. The low-pass filter achieves a dynamic range of 61 dB, with a total harmonic distortion of 0.8%.

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Datta, Suman, Wriddhi Chakraborty, and Marko Radosavljevic. "Toward attojoule switching energy in logic transistors." Science 378, no. 6621 (2022): 733–40. http://dx.doi.org/10.1126/science.ade7656.

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Advances in the theory of semiconductors in the 1930s in addition to the purification of germanium and silicon crystals in the 1940s enabled the point-contact junction transistor in 1947 and initiated the era of semiconductor electronics. Gordon Moore postulated 18 years later that the number of components in an integrated circuit would double every 1 to 2 years with associated reductions in cost per transistor. Transistor density doubling through scaling—the decrease of component sizes—with each new process node continues today, albeit at a slower pace compared with historical rates of scaling. Transistor scaling has resulted in exponential gain in performance and energy efficiency of integrated circuits, which transformed computing from mainframes to personal computers and from mobile computing to cloud computing. Innovations in new materials, transistor structures, and lithographic technologies will enable further scaling. Monolithic 3D integration, design technology co-optimization, alternative switching mechanisms, and cryogenic operation could enable further transistor scaling and improved energy efficiency in the foreseeable future.

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Jung, Minji, Kyeongmin Min, Hyunwoo Son, and Youngwoo Ji. "A 5-Transistor CMOS Voltage Reference with Double Supply-Regulation." Electronics 14, no. 3 (2025): 588. https://doi.org/10.3390/electronics14030588.

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This paper presents an ultra-low-power CMOS voltage reference designed and verified in an 180 nm standard CMOS technology. To achieve DC and AC supply sensitivity under 0.01%/V and −100 dB, it employs a single transistor and two 2-T cores to improve supply immunity with minimal overhead, adding only one drain-to-source voltage for the total supply voltage. The proposed design achieves a line sensitivity of 0.0027%/V in a supply voltage range of 0.5 V to 2 V and consumes 630 pW with a supply voltage of 0.5 V. The simulated temperature coefficient is 12 ppm/°C in a temperature range of −40 °C to 150 °C, and the simulated power supply rejection ratio is −100.5 dB at 100 Hz without requiring any output decoupling capacitor.

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Gyawali, Yadu Prasad, and Mohit Angurala. "Design of Frequency Divider (FD/2 and FD 2/3) Circuits for a Phase Locked Loop." International Journal on Future Revolution in Computer Science & Communication Engineering 8, no. 1 (2022): 27–31. http://dx.doi.org/10.17762/ijfrcsce.v8i1.2103.

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This paper reports on three design of Frequency Divider (FD/2) and Frequency Divider (FD 2/3) circuits. Tanner EDA tool developed on 130nm CMOS technology with a voltage supply of 1.3 V is used to build, model, and compare all circuits. For the FD/2 circuit, E-TSPC Pass Transistor logic uses 1.77 µW, whereas TSPC logic consumes 5.57 µW for the FD 2/3 circuit. It implies that the TSPC logic is the best solution since it meets the speed and power consumption requirements.

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Journal articles on the topic 'Double pass transistor technology'

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