Relevant bibliographies by topics / Drain-source current (IDS)

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Academic literature on the topic 'Drain-source current (IDS)'

Author: Grafiati
Published: 3 June 2025
Last updated: 22 June 2025

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Journal articles on the topic "Drain-source current (IDS)"

1

Kimbrough, Joevonte, Lauren Williams, Qunying Yuan, and Zhigang Xiao. "Dielectrophoresis-Based Positioning of Carbon Nanotubes for Wafer-Scale Fabrication of Carbon Nanotube Devices." Micromachines 12, no. 1 (2020): 12. http://dx.doi.org/10.3390/mi12010012.

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In this paper, we report the wafer-scale fabrication of carbon nanotube field-effect transistors (CNTFETs) with the dielectrophoresis (DEP) method. Semiconducting carbon nanotubes (CNTs) were positioned as the active channel material in the fabrication of carbon nanotube field-effect transistors (CNTFETs) with dielectrophoresis (DEP). The drain-source current (IDS) was measured as a function of the drain-source voltage (VDS) and gate-source voltage (VGS) from each CNTFET on the fabricated wafer. The IDS on/off ratio was derived for each CNTFET. It was found that 87% of the fabricated CNTFETs was functional, and that among the functional CNTFETs, 30% of the CNTFETs had an IDS on/off ratio larger than 20 while 70% of the CNTFETs had an IDS on/off ratio lower than 20. The highest IDS on/off ratio was about 490. The DEP-based positioning of carbon nanotubes is simple and effective, and the DEP-based device fabrication steps are compatible with Si technology processes and could lead to the wafer-scale fabrication of CNT electronic devices.
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2

Tang, Sheng-Yi. "Study on Characteristics of Enhancement-Mode Gallium-Nitride High-Electron-Mobility Transistor for the Design of Gate Drivers." Electronics 9, no. 10 (2020): 1573. http://dx.doi.org/10.3390/electronics9101573.

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An enhancement-mode gallium-nitride high-electron-mobility transistor (E-mode GaN HEMT) operated at high frequency is highly prone to current spikes (di/dt) and voltage spikes (dv/dt) in the parasitic inductor of its circuit, resulting in damage to the power switch. To highlight the phenomena of di/dt and dv/dt, this study connected the drain, source, and gate terminals in series with inductors (LD, LS, and LG, respectively). The objective was to explore the effects of di/dt and dv/dt phenomena and operating frequency (fS) on drain-to-source voltage (Vds), drain-to-source current (Ids), and gate-to-source voltage (Vgs). The experimental method comprised two projects: (1) establishment of a measurement system to assess the change of electrical characteristics of the E-mode GaN HEMT and (2) change of the fS and the inductances (i.e., LD, LS, and LG) in the circuit to measure the changes in Vds, Ids, and Vgs, thus summarizing the experimental results. According to the experimental results on electrical characteristics, a gate driver circuit may be designed to drive and protect the E-mode GaN HEMT while being actually applied to a 120-W synchronous buck converter with an output voltage of 12 V and an output current of 10 A.
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3

Tabib-Azar, Massood, and Rugved Likhite. "Nano-Particle VO2 Insulator-Metal Transition Field-Effect Switch with 42 mV/decade Sub-Threshold Slope." Electronics 8, no. 2 (2019): 151. http://dx.doi.org/10.3390/electronics8020151.

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The possibility of controlling the insulator-to-metal transition (IMT) in nano-particle VO2 (NP-VO2) using the electric field effect in a metal-oxide-VO2 field-effect transistor (MOVFET) at room temperature was investigated for the first time. The IMT induced by current in NP-VO2 is a function of nano-particle size and was studied first using the conducting atomic force microscope (cAFM) current-voltage (I-V) measurements. NP-VO2 switching threshold voltage (VT), leakage current (Ileakage), and the sub-threshold slope of their conductivity (Sc) were all determined. The cAFM data had a large scatter. However, VT increased as a function of particle height (h) approximately as VT(V) = 0.034 h, while Ileakage decreased as a function of h approximately as Ileakage (A) = 3.4 × 10−8e−h/9.1. Thus, an asymptotic leakage current of 34 nA at zero particle size and a tunneling (carrier) decay constant of ~9.1 nm were determined. Sc increased as a function of h approximately as Sc (mV/decade) = 2.1 × 10−3eh/6 and was around 0.6 mV/decade at h~34 nm. MOVFETs composed of Pt drain, source and gate electrodes, HfO2 gate oxide, and NP-VO2 channels were then fabricated and showed gate voltage dependent drain-source switching voltage and current (IDS). The subthreshold slope (St) of drain-source current (IDS) varied from 42 mV/decade at VG = −5 V to 54 mV/decade at VG = +5 V.
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4

Liu, Cuicui, Gang Guo, Huilin Shi, et al. "Equivalence Study of Single-Event Effects in Silicon Carbon Metal-Oxide Semiconductor Field-Effect Transistors by Protons and Heavy Ions." Electronics 14, no. 5 (2025): 1022. https://doi.org/10.3390/electronics14051022.

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The primary objective of this research is to comprehensively investigate the equivalence of single-event effects (SEEs) in silicon carbide metal-oxide semiconductor field-effect transistors (SiC MOSFETs) that are induced by protons and heavy ions. The samples utilized in the experiments are the fourth-generation symmetric groove gate SiC MOSFETs. Proton irradiation experiments were meticulously executed at varying energies, namely 70 MeV, 100 MeV, and 200 MeV, while heavy-ion irradiation was carried out using 138 MeV Cl ions. During these experiments, the drain–source current (IDS) and drain–source voltage (VDS) were continuously and precisely monitored in real time. Experimental results demonstrate that single-event burnout (SEB) susceptibility correlates strongly with proton energy and applied drain–source bias. Notably, SiC MOSFETs exhibit a stronger tolerance to proton SEB compared to heavy-ion SEB. Proton irradiation results in a sudden elevation in IDS, whereas heavy-ion irradiation leads to a gradual increase. In summary, the mechanism underlying proton-induced SEE is intricately related to the ionization of secondary particles. Future research endeavors should place a greater emphasis on comprehensively considering proton effects to establish a more complete and effective evaluation system for SiC MOSFET SEEs.
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5

Najam, Faraz, and Yun Seop Yu. "Compact Trap-Assisted-Tunneling Model for Line Tunneling Field-Effect-Transistor Devices." Applied Sciences 10, no. 13 (2020): 4475. http://dx.doi.org/10.3390/app10134475.

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Trap-assisted-tunneling (TAT) is a well-documented source of severe subthreshold degradation in tunneling field-effect-transistors (TFET). However, the literature lacks in numerical or compact TAT models applied to TFET devices. This work presents a compact formulation of the Schenk TAT model that is used to fit experimental drain-source current (Ids) versus gate-source voltage (Vgs) data of an L-shaped and line tunneling type TFET. The Schenk model incorporates material-dependent fundamental physical constants that play an important role in influencing the TAT generation (GTAT) including the lattice relaxation energy, Huang–Rhys factor, and the electro-optical frequency. This makes fitting any experimental data using the Schenk model physically relevant. The compact formulation of the Schenk TAT model involved solving the potential profile in the TFET and using that potential profile to calculate GTAT using the standard Schenk model. The GTAT was then approximated by the Gaussian distribution function for compact implementation. The model was compared against technology computer-aided design (TCAD) results and was found in reasonable agreement. The model was also used to fit an experimental device’s Ids–Vgs characteristics. The results, while not exactly fitting the experimental data, follow the general experimental Ids–Vgs trend reasonably well; the subthreshold slope was loosely similar to the experimental device. Additionally, the ON-current, especially to make a high drain-source bias model accurate, can be further improved by including effects such as electrostatic degradation and series resistance.
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6

Yang, Hsin-Chia, and Sung-Ching Chi. "Conclusive Model-Fit Current–Voltage Characteristic Curves with Kink Effects." Applied Sciences 13, no. 22 (2023): 12379. http://dx.doi.org/10.3390/app132212379.

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Current–voltage characteristic curves of NFinFET are presented and fitted with modified current–voltage (I-V) formulas, where the modified term in the triode region is demonstrated to be indispensable. In the as-known I-V formula, important parameters need to be determined to make both the measured data and the fitting data as close as possible. These parameters include kN (associated with the sizes of the transistor and mobility), λ (associated with early voltage), and Vth (the threshold voltage). The differences between the measured data and the fitting data vary with the applied source–drain bias, proving that the mobility of the carriers is not consistently constant. On the other hand, a modified formula, called the kink effect factor, is negatively or positively added, simulating solitary heat waves or lattice vibration, which disturb the propagation of carriers and thus influence the source–drain current (IDS). The new statistical standard deviations (δ) are then found to be effectively suppressed as the kink effect is taken into account.
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7

Климов, А. Э., И. О. Ахундов, В. А. Голяшов та ін. "Фоточувствительность полевого транзистора металл-диэлектрик-полупроводник на основе пленки PbSnTe:In с составом вблизи инверсии зон". Письма в журнал технической физики 49, № 3 (2023): 22. http://dx.doi.org/10.21883/pjtf.2023.03.54461.19426.

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A prototype of a metal–insulator–semiconductor field-effect transistor based on PbSnTe:In/(111)BaF2 film with an Al2O3 gate dielectric was designed for the first time. With the gate voltage applied in the range – 7.7 V < Ugate < +7.7 V the relative modulation in the drain-source current Ids/Ids attained near five-fold change at T = 4.2 K. When illuminated with rela-tively low (~100 photon/s) fluxes, negative photoconductivity was detected accompanied with a decrease in Ids by ~104 times and a simultaneous decrease in Ids by ~103 times or even more. The estimated detectivity was about 71016 cmHz0.5W-1 at a wavelength  about 25 micron with the accumulation time about 0.5 s. A qualitative model is discussed which assumes the ex-istence of deep traps and a photo-capacitance effect.
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8

Upasana, Rakhi Narang, Manoj Saxena, and Mridula Gupta. "Drain Current Model for Hetero-Dielectric Based TFET Architectures: Accumulation to Inversion Mode Analysis." Journal of Nano Research 36 (November 2015): 31–43. http://dx.doi.org/10.4028/www.scientific.net/jnanor.36.31.

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The paper presents an in-depth study of device physics and development of a generalized model (Accumulation-Depletion-Inversion Mode) for Hetero-Dielectric based TFET Architecture. A comparative study among single dielectric (high-k and low-k dielectric materials) and dual-dielectric (Hetero-Dielectric) based p-i-n and p-n-i-n TFET architectures has also been made. The model includes the impact of dielectric length variation and mobile charge carriers which has been validated through the Vgs and Vds dependent effective potential at the channel center of the device. Several physics based parameters such as surface potential, energy band profile, total electric field and drain current (both Ids-Vds and Ids-Vds) have also been investigated. Further, the model has been extended to optimize the Hetero-Dielectric p-n-i-n TFET by tuning the gate work function and length of the dielectric material. While optimization various static parameters such as Subthreshold Swing (SS), threshold voltage, Ion/Ioff ratio and dynamic performance parameters (parasitic capacitances) i.e. total gate capacitance (Cgg), gate to source capacitance (Cgs) and gate to drain capacitance (Cgd) have been investigated. The efficacy of the model has been validated through simulation results obtained using ATLAS device simulator.
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9

Adjaye, John, and Michael S. Mazzola. "Physics of Hysteresis in MESFET Drain I-V Characteristics: Simulation Approach." Materials Science Forum 645-648 (April 2010): 945–48. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.945.

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The two-dimensional device simulator, MediciTM, was used to simulate 4H silicon carbide (4H-SiC) n-channel power metal semiconductor field effect transistors (MESFETs) with 0.5 µm gate length with and without p-type buffer layer between the n-channel and the semi-insulating (SI) substrate. The devices, which have previously been fabricated and characterized experimentally, have ion-implanted n+ source and drain ohmic contact regions. The simulations were performed with transient 30 V amplitude symmetrical triangular pulse with 30 s pulse width. Simulations show that hysteresis in drain I-V curves of MESFETs is due to substrate traps and source/drain implant damage traps. The hysteresis is caused by trapping and emission of channel electrons by the traps as VDS rises from 0 V to VDS(max) and as VDS falls from VDS(max) back to 0 V. This leads to difference in trap occupation, and hence difference in channel electron concentration as VDS rises and falls. This finally leads to difference in drain-source current (IDS) at a given VDS for a given VGS as VDS rises and falls, giving rise to the hysteresis in the I-V curves.
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10

Liaw, Yue-Gie, Wen-Shiang Liao, Mu-Chun Wang, et al. "Performance characteristics of p-channel FinFETs with varied Si-fin extension lengths for source and drain contacts." Физика и техника полупроводников 51, no. 12 (2017): 1706. http://dx.doi.org/10.21883/ftp.2017.12.45190.8421.

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The length of Source/Drain (S/D) extension (LSDE) of nano-node p-channel FinFETs (pFinFETs) on SOI wafer influencing the device performance is exposed, especially in drive current and gate/S/D leakage. In observation, the longer LSDE pFinFET provides a larger series resistance and degrades the drive current (IDS), but the isolation capability between the S/D contacts and the gate electrode is increased. The shorter LSDE plus the shorter channel length demonstrates a higher trans-conductance (Gm) contributing to a higher drive current. Moreover, the subthreshold swing (S.S.) at longer channel length and longer LSDE represents a higher value indicating the higher amount of the interface states which possibly deteriorate the channel mobility causing the lower drive current. DOI: 10.21883/FTP.2017.12.45190.8421
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Conference papers on the topic "Drain-source current (IDS)"

1

Chowdhury, Ravin A., Jeff Chiles, Brandon Cage, et al. "CMOS Integrated Circuit Analysis Using Superconducting Nanowire Single-Photon Detectors." In ISTFA 2024. ASM International, 2024. http://dx.doi.org/10.31399/asm.cp.istfa2024p0119.

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Abstract Time-resolved emission microscopy (TREM) enables non-intrusive failure analysis of integrated circuits through photoemission detection at picosecond resolution. While photoemission occurs in both functional and faulty ICs, certain emission patterns distinctively indicate device defects. The primary mechanism driving this phenomenon is hot carrier luminescence in silicon, where carriers with excess kinetic energy release photons through intraband transitions. In CMOS logic, these emissions occur when MOSFETs switch between logical states, generating drain-to-source current flow. However, modern large-scale ICs present unique challenges for photoemission analysis: their lower operating voltages and reduced switching currents result in fewer photon emissions, predominantly in the infrared spectrum. We address these limitations by implementing superconducting-nanowire single-photon detectors (SNSPDs), enabling high-sensitivity photoemission microscopy for advanced IC failure analysis.
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2

Unger, Christian, and Martin Pfost. "Influence of the off-state gate-source voltage on the transient drain current response of SiC MOSFETs." In 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD). IEEE, 2018. http://dx.doi.org/10.1109/ispsd.2018.8393599.

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3

Richardeau, F., A. Borghese, A. Castellazzi, A. Irace, V. Chazal, and G. Guibaud. "Effect of gate-source bias voltage and gate-drain leakage current on the short-circuit performance of FTO-type SiC power MOSFETs." In 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD). IEEE, 2021. http://dx.doi.org/10.23919/ispsd50666.2021.9452253.

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