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1
Kimbrough, Joevonte, Lauren Williams, Qunying Yuan, and Zhigang Xiao. "Dielectrophoresis-Based Positioning of Carbon Nanotubes for Wafer-Scale Fabrication of Carbon Nanotube Devices." Micromachines 12, no. 1 (2020): 12. http://dx.doi.org/10.3390/mi12010012.
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In this paper, we report the wafer-scale fabrication of carbon nanotube field-effect transistors (CNTFETs) with the dielectrophoresis (DEP) method. Semiconducting carbon nanotubes (CNTs) were positioned as the active channel material in the fabrication of carbon nanotube field-effect transistors (CNTFETs) with dielectrophoresis (DEP). The drain-source current (IDS) was measured as a function of the drain-source voltage (VDS) and gate-source voltage (VGS) from each CNTFET on the fabricated wafer. The IDS on/off ratio was derived for each CNTFET. It was found that 87% of the fabricated CNTFETs was functional, and that among the functional CNTFETs, 30% of the CNTFETs had an IDS on/off ratio larger than 20 while 70% of the CNTFETs had an IDS on/off ratio lower than 20. The highest IDS on/off ratio was about 490. The DEP-based positioning of carbon nanotubes is simple and effective, and the DEP-based device fabrication steps are compatible with Si technology processes and could lead to the wafer-scale fabrication of CNT electronic devices.
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Tang, Sheng-Yi. "Study on Characteristics of Enhancement-Mode Gallium-Nitride High-Electron-Mobility Transistor for the Design of Gate Drivers." Electronics 9, no. 10 (2020): 1573. http://dx.doi.org/10.3390/electronics9101573.
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An enhancement-mode gallium-nitride high-electron-mobility transistor (E-mode GaN HEMT) operated at high frequency is highly prone to current spikes (di/dt) and voltage spikes (dv/dt) in the parasitic inductor of its circuit, resulting in damage to the power switch. To highlight the phenomena of di/dt and dv/dt, this study connected the drain, source, and gate terminals in series with inductors (LD, LS, and LG, respectively). The objective was to explore the effects of di/dt and dv/dt phenomena and operating frequency (fS) on drain-to-source voltage (Vds), drain-to-source current (Ids), and gate-to-source voltage (Vgs). The experimental method comprised two projects: (1) establishment of a measurement system to assess the change of electrical characteristics of the E-mode GaN HEMT and (2) change of the fS and the inductances (i.e., LD, LS, and LG) in the circuit to measure the changes in Vds, Ids, and Vgs, thus summarizing the experimental results. According to the experimental results on electrical characteristics, a gate driver circuit may be designed to drive and protect the E-mode GaN HEMT while being actually applied to a 120-W synchronous buck converter with an output voltage of 12 V and an output current of 10 A.
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Tabib-Azar, Massood, and Rugved Likhite. "Nano-Particle VO2 Insulator-Metal Transition Field-Effect Switch with 42 mV/decade Sub-Threshold Slope." Electronics 8, no. 2 (2019): 151. http://dx.doi.org/10.3390/electronics8020151.
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The possibility of controlling the insulator-to-metal transition (IMT) in nano-particle VO2 (NP-VO2) using the electric field effect in a metal-oxide-VO2 field-effect transistor (MOVFET) at room temperature was investigated for the first time. The IMT induced by current in NP-VO2 is a function of nano-particle size and was studied first using the conducting atomic force microscope (cAFM) current-voltage (I-V) measurements. NP-VO2 switching threshold voltage (VT), leakage current (Ileakage), and the sub-threshold slope of their conductivity (Sc) were all determined. The cAFM data had a large scatter. However, VT increased as a function of particle height (h) approximately as VT(V) = 0.034 h, while Ileakage decreased as a function of h approximately as Ileakage (A) = 3.4 × 10−8e−h/9.1. Thus, an asymptotic leakage current of 34 nA at zero particle size and a tunneling (carrier) decay constant of ~9.1 nm were determined. Sc increased as a function of h approximately as Sc (mV/decade) = 2.1 × 10−3eh/6 and was around 0.6 mV/decade at h~34 nm. MOVFETs composed of Pt drain, source and gate electrodes, HfO2 gate oxide, and NP-VO2 channels were then fabricated and showed gate voltage dependent drain-source switching voltage and current (IDS). The subthreshold slope (St) of drain-source current (IDS) varied from 42 mV/decade at VG = −5 V to 54 mV/decade at VG = +5 V.
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Liu, Cuicui, Gang Guo, Huilin Shi, et al. "Equivalence Study of Single-Event Effects in Silicon Carbon Metal-Oxide Semiconductor Field-Effect Transistors by Protons and Heavy Ions." Electronics 14, no. 5 (2025): 1022. https://doi.org/10.3390/electronics14051022.
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The primary objective of this research is to comprehensively investigate the equivalence of single-event effects (SEEs) in silicon carbide metal-oxide semiconductor field-effect transistors (SiC MOSFETs) that are induced by protons and heavy ions. The samples utilized in the experiments are the fourth-generation symmetric groove gate SiC MOSFETs. Proton irradiation experiments were meticulously executed at varying energies, namely 70 MeV, 100 MeV, and 200 MeV, while heavy-ion irradiation was carried out using 138 MeV Cl ions. During these experiments, the drain–source current (IDS) and drain–source voltage (VDS) were continuously and precisely monitored in real time. Experimental results demonstrate that single-event burnout (SEB) susceptibility correlates strongly with proton energy and applied drain–source bias. Notably, SiC MOSFETs exhibit a stronger tolerance to proton SEB compared to heavy-ion SEB. Proton irradiation results in a sudden elevation in IDS, whereas heavy-ion irradiation leads to a gradual increase. In summary, the mechanism underlying proton-induced SEE is intricately related to the ionization of secondary particles. Future research endeavors should place a greater emphasis on comprehensively considering proton effects to establish a more complete and effective evaluation system for SiC MOSFET SEEs.
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Najam, Faraz, and Yun Seop Yu. "Compact Trap-Assisted-Tunneling Model for Line Tunneling Field-Effect-Transistor Devices." Applied Sciences 10, no. 13 (2020): 4475. http://dx.doi.org/10.3390/app10134475.
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Trap-assisted-tunneling (TAT) is a well-documented source of severe subthreshold degradation in tunneling field-effect-transistors (TFET). However, the literature lacks in numerical or compact TAT models applied to TFET devices. This work presents a compact formulation of the Schenk TAT model that is used to fit experimental drain-source current (Ids) versus gate-source voltage (Vgs) data of an L-shaped and line tunneling type TFET. The Schenk model incorporates material-dependent fundamental physical constants that play an important role in influencing the TAT generation (GTAT) including the lattice relaxation energy, Huang–Rhys factor, and the electro-optical frequency. This makes fitting any experimental data using the Schenk model physically relevant. The compact formulation of the Schenk TAT model involved solving the potential profile in the TFET and using that potential profile to calculate GTAT using the standard Schenk model. The GTAT was then approximated by the Gaussian distribution function for compact implementation. The model was compared against technology computer-aided design (TCAD) results and was found in reasonable agreement. The model was also used to fit an experimental device’s Ids–Vgs characteristics. The results, while not exactly fitting the experimental data, follow the general experimental Ids–Vgs trend reasonably well; the subthreshold slope was loosely similar to the experimental device. Additionally, the ON-current, especially to make a high drain-source bias model accurate, can be further improved by including effects such as electrostatic degradation and series resistance.
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Yang, Hsin-Chia, and Sung-Ching Chi. "Conclusive Model-Fit Current–Voltage Characteristic Curves with Kink Effects." Applied Sciences 13, no. 22 (2023): 12379. http://dx.doi.org/10.3390/app132212379.
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Current–voltage characteristic curves of NFinFET are presented and fitted with modified current–voltage (I-V) formulas, where the modified term in the triode region is demonstrated to be indispensable. In the as-known I-V formula, important parameters need to be determined to make both the measured data and the fitting data as close as possible. These parameters include kN (associated with the sizes of the transistor and mobility), λ (associated with early voltage), and Vth (the threshold voltage). The differences between the measured data and the fitting data vary with the applied source–drain bias, proving that the mobility of the carriers is not consistently constant. On the other hand, a modified formula, called the kink effect factor, is negatively or positively added, simulating solitary heat waves or lattice vibration, which disturb the propagation of carriers and thus influence the source–drain current (IDS). The new statistical standard deviations (δ) are then found to be effectively suppressed as the kink effect is taken into account.
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Климов, А. Э., И. О. Ахундов, В. А. Голяшов та ін. "Фоточувствительность полевого транзистора металл-диэлектрик-полупроводник на основе пленки PbSnTe:In с составом вблизи инверсии зон". Письма в журнал технической физики 49, № 3 (2023): 22. http://dx.doi.org/10.21883/pjtf.2023.03.54461.19426.
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A prototype of a metal–insulator–semiconductor field-effect transistor based on PbSnTe:In/(111)BaF2 film with an Al2O3 gate dielectric was designed for the first time. With the gate voltage applied in the range – 7.7 V < Ugate < +7.7 V the relative modulation in the drain-source current Ids/Ids attained near five-fold change at T = 4.2 K. When illuminated with rela-tively low (~100 photon/s) fluxes, negative photoconductivity was detected accompanied with a decrease in Ids by ~104 times and a simultaneous decrease in Ids by ~103 times or even more. The estimated detectivity was about 71016 cmHz0.5W-1 at a wavelength about 25 micron with the accumulation time about 0.5 s. A qualitative model is discussed which assumes the ex-istence of deep traps and a photo-capacitance effect.
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Upasana, Rakhi Narang, Manoj Saxena, and Mridula Gupta. "Drain Current Model for Hetero-Dielectric Based TFET Architectures: Accumulation to Inversion Mode Analysis." Journal of Nano Research 36 (November 2015): 31–43. http://dx.doi.org/10.4028/www.scientific.net/jnanor.36.31.
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The paper presents an in-depth study of device physics and development of a generalized model (Accumulation-Depletion-Inversion Mode) for Hetero-Dielectric based TFET Architecture. A comparative study among single dielectric (high-k and low-k dielectric materials) and dual-dielectric (Hetero-Dielectric) based p-i-n and p-n-i-n TFET architectures has also been made. The model includes the impact of dielectric length variation and mobile charge carriers which has been validated through the Vgs and Vds dependent effective potential at the channel center of the device. Several physics based parameters such as surface potential, energy band profile, total electric field and drain current (both Ids-Vds and Ids-Vds) have also been investigated. Further, the model has been extended to optimize the Hetero-Dielectric p-n-i-n TFET by tuning the gate work function and length of the dielectric material. While optimization various static parameters such as Subthreshold Swing (SS), threshold voltage, Ion/Ioff ratio and dynamic performance parameters (parasitic capacitances) i.e. total gate capacitance (Cgg), gate to source capacitance (Cgs) and gate to drain capacitance (Cgd) have been investigated. The efficacy of the model has been validated through simulation results obtained using ATLAS device simulator.
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Adjaye, John, and Michael S. Mazzola. "Physics of Hysteresis in MESFET Drain I-V Characteristics: Simulation Approach." Materials Science Forum 645-648 (April 2010): 945–48. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.945.
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The two-dimensional device simulator, MediciTM, was used to simulate 4H silicon carbide (4H-SiC) n-channel power metal semiconductor field effect transistors (MESFETs) with 0.5 µm gate length with and without p-type buffer layer between the n-channel and the semi-insulating (SI) substrate. The devices, which have previously been fabricated and characterized experimentally, have ion-implanted n+ source and drain ohmic contact regions. The simulations were performed with transient 30 V amplitude symmetrical triangular pulse with 30 s pulse width. Simulations show that hysteresis in drain I-V curves of MESFETs is due to substrate traps and source/drain implant damage traps. The hysteresis is caused by trapping and emission of channel electrons by the traps as VDS rises from 0 V to VDS(max) and as VDS falls from VDS(max) back to 0 V. This leads to difference in trap occupation, and hence difference in channel electron concentration as VDS rises and falls. This finally leads to difference in drain-source current (IDS) at a given VDS for a given VGS as VDS rises and falls, giving rise to the hysteresis in the I-V curves.
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Liaw, Yue-Gie, Wen-Shiang Liao, Mu-Chun Wang, et al. "Performance characteristics of p-channel FinFETs with varied Si-fin extension lengths for source and drain contacts." Физика и техника полупроводников 51, no. 12 (2017): 1706. http://dx.doi.org/10.21883/ftp.2017.12.45190.8421.
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The length of Source/Drain (S/D) extension (LSDE) of nano-node p-channel FinFETs (pFinFETs) on SOI wafer influencing the device performance is exposed, especially in drive current and gate/S/D leakage. In observation, the longer LSDE pFinFET provides a larger series resistance and degrades the drive current (IDS), but the isolation capability between the S/D contacts and the gate electrode is increased. The shorter LSDE plus the shorter channel length demonstrates a higher trans-conductance (Gm) contributing to a higher drive current. Moreover, the subthreshold swing (S.S.) at longer channel length and longer LSDE represents a higher value indicating the higher amount of the interface states which possibly deteriorate the channel mobility causing the lower drive current. DOI: 10.21883/FTP.2017.12.45190.8421
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Zhang, Bo, Hui Ling Tai, Guang Zhong Xie, Xian Li, and Huan Na Zhang. "The Investigation of a New NO2 OTFT Sensor Based on Heterojunction F16CuPc/CuPc Thin Films." Advanced Materials Research 721 (July 2013): 159–63. http://dx.doi.org/10.4028/www.scientific.net/amr.721.159.
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The bottom contact heterojunction organic thin film transistors (OTFTs) based on n-type hexadecafluorophthalocyaninatocopper (F16CuPc) and p-type copper phthalocyanine (CuPc) bilayer were developed by the vacuum evaporation, which were applied to detect nitrogen dioxide (NO2). The sensors with different thickness (5nm, 10nm, 15nm and 20nm) of CuPc were prepared to investigate the influence of CuPc film thickness on the properties of devices. The results showed that four parameters including the source-drain current (IDS), grid current (IGS), threshold voltage (VT) and carrier mobility (μ) changed in a few seconds when the sensors were exposed to the atmosphere of NO2. Further more, IDS and IGS presented extremely similar variation trend. So the grid current would be taken as a new parameter to reveal the response characteristic of OTFT gas sensor. By comparison, the device with 15nm CuPc thin film exhibited the optimum electronic and gas sensing properties.
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Guo, Han, Wu Tang, Wei Zhou, and Chi Ming Li. "Effect of GaN Cap Layer on the Electrical Properties of AlGaN/GaN HEMT." Applied Mechanics and Materials 217-219 (November 2012): 2393–96. http://dx.doi.org/10.4028/www.scientific.net/amm.217-219.2393.
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The electrical properties of AlGaN/GaN heterojunction high electron mobility transistor (HEMT) are simulated by using sentaurus software. This paper compares two structures, the HEMT with GaN cap layer and the HEMT without GaN cap layer. The sentaurus software simulates the DC and AC characteristics of the two AlGaN/GaN HEMT structures. The HEMT with GaN cap layer can increase the maximum transconductance gm from 177ms/mm to 399ms/mm when the doping concentration of the cap layer is 3×1018cm-3 compared with the other structure under the same conditions. The simulation results indicate that the HEMT with cap layer can increase maximum transconductance gm, saturation current Ids, current-gain cutoff frequency fT, maximum oscillation frequency fmax and reduce the series resistance of the drain to source compared with the HEMT without GaN cap layer. The large Ids of the HEMT with cap layer is attributed to the increase of the concentration of two dimensional electron gas (2DEG). Moreover, the change of the doping concentration of the cap layer will affect the gm and Ids.
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Chen, Yu Cheng, Jian Zhong, and Lin Zhang. "Formaldehyde Gas Sensor Based on Pentacene Organic Thin-Film Transistor." Key Engineering Materials 575-576 (September 2013): 477–80. http://dx.doi.org/10.4028/www.scientific.net/kem.575-576.477.
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Formaldehyde (HCHO) gas sensors based on pentacene active layer and low cost poly (merthyl methacrylate) (PMMA) insulator were fabricated with a structure of bottom contact organic thin-film transistor (OTFT). The OTFT sensor not only presented a remarkable response characteristic in the absence and the presence of HCHO gas with different concentrations, but also exhibited a good repeatability for sensing the HCHO gas. Meanwhile, compared to the device operated in nitrogen circumstance, obvious changes in saturation drain-source current (IDS) and off-state current were observed when the device exposed to HCHO gas. Also the device performance and sensing mechanisms were discussed.
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Lee, Ching-Sung, Jian-Hong Ke, Zhong-Liang Liao, Yu-Syuan Cai, Yong-Han Yang, and Ke Jian-Hong. "Record-High BVDS p-Channel P++-GaN/P-GaN/GaN/AlN/Al0.3Ga0.7n MOS-HFETs with Drain Field-Plate Design." ECS Meeting Abstracts MA2024-02, no. 40 (2024): 4884. https://doi.org/10.1149/ma2024-02404884mtgabs.
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This work reports record-high three-terminal on- state drain-source breakdown voltage (BVDS ) of -735 V, superior on/off current ratio (Ion /Ioff ) of 2 × 106, and improved device performance of the p-channel p++- GaN/p-GaN/GaN/AlGaN metal-oxide-semiconductor hetero-structure field-effect transistors (MOS-HFETs) with drain-field plate (DFP) design. A reference MOS-HFET without DFP was fabricated and studied in comparison. High-k, wide-gap Al2O3 was deposited as the gate oxide and surface passivation by using a non-vacuum ultrasonic spray pyrolysis deposition (USPD) technique. Atomic force microscope (AFM), transmission electron microscope (TEM), X-ray photoelectron spectroscopy (XPS), and capacitance-voltage (C-V) measurement were also performed to characterize the material and interface quality of the MOS-gate design. The present p-channel MOS-HFET design is promising for high-voltage complementary power-switching circuit application. The schematic device structures of the present p++-GaN/ p-GaN/GaN/AlN/Al0.3Ga0.7N MOS-HFETs without/with DFP (samples A/B) are shown in Fig. 1(a). The epitaxial layers for both samples were grown on a Si substrate by using a low-pressure metal-organic chemical vapor deposition (LP-MOCVD) system. The related schematic energy-band diagram was shown in Fig. 1(b), illustrating the formation of 2DHG by the heterostructural design. Standard lift-off and photolithography were applied to the device fabrication for the present sample with (without) DFP design. The AFM photos shown in Figs. 2 (a)-(c) compared the surface roughness after dry-etching, after the TMAH treatment, and after the further deposition of Al2O3 by USPD. The cross-sectional TEM photo of the Al2O3 oxide was shown in Fig. 2 (d). The XPS profile shown in Fig. 3 also verified the composition of the Al2O3 layer. Fig. 4 shows the C-V hysteresis measurement curves to confirm the improved interfacial quality by the Al2O3 passivation. Figs. 5(a)-(b) show the typical IDS -VDS curves and the transfer IDS /gm -VGS characteristics for the studied samples A and B at 300 K. The characterized three-terminal on- state drain-source breakdown voltage (BVDS ) andtwo-terminal off-state gate-drain breakdown voltage (BVGD ) were also compared in Fig. 6 and its inset. Due to the integrated device design as mentioned before, the present sample B (A) with (without) DFP has demonstrated superior maximum drain-source current density (IDS, max ) of -9.5 (-10.6) mA/mm at VDS = 20 V, on/off current ratio (Ion /Ioff ) of 2 × 106 (9.2 × 105), BVGD of 710 (520) V, and BVDS of -735 (-545) V, respectively. Enhanced gate modulation, improved current density, enhanced Ion /Ioff switching, and superior BVDS and BVGD performances have been successfully achieved. Comparisons of the IDS, max vs. Ion/Ioff benchmark of the present samples A and B with respect to other p- channel GaN-based devices were shown in Fig. 7. The present sample B has achieved the record-high BVDS of - 735 V with superior Ion /Ioff ratio of 2 × 106. The present p-channel GaN MOS-HFET designs with/without DFP have been successfully investigated. Through the integrated heterostructural/device designs, material/interface characterizations, and comparative device measurement, the present sample B has demonstrated superior performance with the highest BVDS record, so far. It is beneficial to high-voltage complementary power-switching IC applications. Figure 1
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Asif, A., H. Richter, and J. N. Burghartz. "High-voltage (100 V) Chipfilm<sup>TM</sup> single-crystal silicon LDMOS transistor for integrated driver circuits in flexible displays." Advances in Radio Science 7 (May 19, 2009): 237–42. http://dx.doi.org/10.5194/ars-7-237-2009.
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Abstract. System-in-Foil (SiF) is an emerging field of large-area polymer electronics that employs new materials such as conductive polymers and electrophoretic micro-capsules (E-Ink) along with ultra-thin and thus flexible chips. In flexible displays, the integration of gate and source drivers onto the flexible part increases the yield and enhances the reliability of the system. In this work we propose a high-voltage ChipfilmTM lateral diffused MOS transistor (LDMOS) structure on ultra-thin single-crystalline silicon chips. The fabrication process is compatible with CMOS standard processing. This LDMOS structure proves to be well suited for providing adequately large switching voltages in spite of the thin (<10 μm) substrate. A breakdown voltage of more than 100 volts with drain-to-source saturation current Ids(sat)≈85 μA/μm for N-LDMOS and Ids(sat)≈20 μA/μm for P-LDMOS is predicted through process and device simulations.
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Green, Ronald, Aderinto Ogunniyi, Dimeji Ibitayo, et al. "Evaluation of 4H–SiC DMOSFETs for High–Power Electronics Applications." Materials Science Forum 600-603 (September 2008): 1135–38. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1135.
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In this paper, large area (0.18cm2) SiC DMOSFETs with 1.2 kV and 20 A rating are evaluated for power electronic switching applications. A drain-to-source voltage drop VDS of 2 V at a forward drain current of 20 A (JD = 110 A/cm2) was obtained and a specific on-resistance of 18 mΩ-cm2 was extracted at room temperature. The device on-resistance was measured up to 150°C and initially decreases with increasing temperature, but remains relatively flat over the entire temperature range, demonstrating stable device behavior. High voltage blocking of 1.2 kV between 25°C and 150°C is also demonstrated with a gate-to-source voltage VGS = 0 V. The drain leakage current under reverse bias and high temperature stress is shown to increase from 10 μA at 25°C to 27 μA at 150°C while maintaining the full blocking rating of the device. Experimental results from double-pulse clamped inductive load tests are presented demonstrating fast high voltage and high current switching capability. High voltage resistive-switching measurements on parallel connected SiC DMOSFETs were performed with VDS having rise and fall times of 49 and 74 ns respectively. Thermal camera images taken of parallel connected DMOSFET die during repetitive switching operation with VDS = 420 V, IDS = 25 A and a 40% duty cycle shows a 2°C difference in die temperature, which suggests even current sharing and temperature stable device operation.
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Malik, Amit, Robert Laishram, D. S. Rawal, and Manoj Saxena. "Performance of the AlGaN/GaN HEMT with Sunken Source Connected Field Plate under High Voltage Reverse Bias Step Stress." Current Natural Sciences and Engineering 1, no. 6 (2024): 464–70. https://doi.org/10.63015/10s-2446.1.6.
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The manuscript investigates the DC performance of conventional HEMT and Sunken Source Connected Field Plate (SSC-FP) HEMT reliability under reverse bias step stress. To assess the electrical performance of the device at the gate terminal is subjected to a high reverse bias step stress up to – 40 V with an increase of – 5 V step. A higher degree of ON–state resistance (RON) degradation is observed in the conventional HEMT than in the SSC-FP HEMT device. Post-stress drain to source current (Ids) degradation is ~11% and ~6% in non-FP and with SSC-FP devices respectively. In conventional devices when gate voltage (VGS) is up to -20V, the device leakage current is recoverable but after that, the gate current increases exponentially and becomes noisy. In SSC-FP devices, this behavior is shown after gate voltage -30V.
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Huang, Chong-Rong, Hsien-Chin Chiu, Chia-Hao Liu, et al. "Characteristic Analysis of AlGaN/GaN HEMT with Composited Buffer Layer on High-Heat Dissipation Poly-AlN Substrates." Membranes 11, no. 11 (2021): 848. http://dx.doi.org/10.3390/membranes11110848.
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In this study, an AlGaN/GaN high-electron-mobility transistor (HEMT) was grown through metal organic chemical vapor deposition on a Qromis Substrate Technology (QST). The GaN on the QST device exhibited a superior heat dissipation performance to the GaN on a Si device because of the higher thermal conductivity of the QST substrate. Thermal imaging analysis indicated that the temperature variation of the GaN on the QST device was 4.5 °C and that of the GaN on the Si device was 9.2 °C at a drain-to-source current (IDS) of 300 mA/mm following 50 s of operation. Compared with the GaN HEMT on the Si device, the GaN on the QST device exhibited a lower IDS degradation at high temperatures (17.5% at 400 K). The QST substrate is suitable for employment in different temperature environments because of its high thermal stability.
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Mallem, Siva Pratap Reddy, Peddathimula Puneetha, Yeojin Choi, et al. "Barrier Height, Ideality Factor and Role of Inhomogeneities at the AlGaN/GaN Interface in GaN Nanowire Wrap-Gate Transistor." Nanomaterials 13, no. 24 (2023): 3159. http://dx.doi.org/10.3390/nano13243159.
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It is essential to understand the barrier height, ideality factor, and role of inhomogeneities at the metal/semiconductor interfaces in nanowires for the development of next generation nanoscale devices. Here, we investigate the drain current (Ids)–gate voltage (Vgs) characteristics of GaN nanowire wrap-gate transistors (WGTs) for various gate potentials in the wide temperature range of 130–310 K. An anomalous reduction in the experimental barrier height and rise in the ideality factor with reducing the temperature have been perceived. It is noteworthy that the variations in barrier height and ideality factor are attributed to the spatial barrier inhomogeneities at the AlGaN/GaN interface in the GaN nanowire WGTs by assuming a double Gaussian distribution of barrier heights at 310–190 K (distribution 1) and 190–130 K (distribution 2). The standard deviation for distribution 2 is lower than that of distribution 1, which suggests that distribution 2 reflects more homogeneity at the AlGaN/GaN interface in the transistor’s source/drain regions than distribution 1.
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Pharkphoumy, Sakhone, Vallivedu Janardhanam, Tae-Hoon Jang, Jaejun Park, Kyu-Hwan Shim, and Chel-Jong Choi. "Optimized Device Geometry of Normally-On Field-Plate AlGaN/GaN High Electron Mobility Transistors for High Breakdown Performance Using TCAD Simulation." Electronics 10, no. 21 (2021): 2642. http://dx.doi.org/10.3390/electronics10212642.
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This study presents the optimization of the lateral device geometry and thickness of the channel and barrier layers of AlGaN/GaN high electron mobility transistors (HEMTs) for the enhancement of breakdown voltage (VBR) characteristics using a TCAD simulation. The effect of device geometry on the device performance was explored by varying the device design parameters, such as the field plate length (LFP), gate-to-drain length (LGD), gate-to-source length (LGS), gate length (LG), thickness of the Si3N4 passivation layer (Tox), thickness of the GaN channel (Tch), and AlGaN barrier (Tbarrier). The VBR was estimated from the off-state drain current versus the drain voltage (IDS–VDS) curve, and it exhibited a strong dependence on the length and thickness of the parameters. The optimum values of VBR for all the device’s geometrical parameters were evaluated, based on which, an optimized device geometry of the field-plated AlGaN/GaN HEMT structure was proposed. The optimized AlGaN/GaN HEMT structure exhibited VBR = 970 V at IGS = 0.14 A/mm, which was considerably higher than the results obtained in previous studies. The results obtained in this study could provide vital information for the selection of the device geometry for the implementation of HEMT structures.
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Hsu, Che-Wei, Yueh-Chin Lin, Ming-Wen Lee, and Edward-Yi Chang. "Investigation of the Effect of Different SiNx Thicknesses on the Characteristics of AlGaN/GaN High-Electron-Mobility Transistors in Ka-Band." Electronics 12, no. 20 (2023): 4336. http://dx.doi.org/10.3390/electronics12204336.
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The effect of different SiNx thicknesses on the performance of AlGaN/GaN high-electron-mobility transistors (HEMTs) was investigated in this paper. The current, transconductance (Gm), cut-off frequency (fT), maximum oscillation frequency (fmax), power performance, and output third-order intercept point (OIP3) of devices with three different SiNx thicknesses (150 nm, 200 nm, and 250 nm) were measured and analyzed. The DC measurements revealed an increase in both the drain-source current (IDS) and Gm values of the device with increasing SiNx thickness. The S-parameter measurement results show that devices with a higher SiNx thickness exhibit improved fT and fmax. Regarding power performance, thicker SiNx devices also improve the output power density (Pout) and power-added efficiency (PAE) in the Ka-band. In addition, the two-tone measurement results at 28 GHz show that the OIP3 increased from 35.60 dBm to 40.87 dBm as the SiNx thickness increased from 150 nm to 250 nm. The device’s characteristics improved by appropriately increasing the SiNx thickness.
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Feng, Liefeng, Kaijin Liu, and Miaoyu Wang. "Exact Relationship between Black Phosphorus Thickness and Behaviors of Field-Effect Transistors." Applied Sciences 13, no. 3 (2023): 1736. http://dx.doi.org/10.3390/app13031736.
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As a two-dimensional (2D) semiconductor material with excellent optoelectronic properties, black phosphorus (BP) has attracted widespread attention. It was found that the energy band structure of BP crystal changes with its thickness if BP is thin. To explore the accurate effects of the BP thicknesses on devices, BP-FETs with different BP thickness (50 nm, 40 nm, 30 nm, 20 nm, and 6 nm) as the channel material were fabricated by mechanical exfoliation technique. The output characteristics and transfer characteristics of the BP-FETs were analyzed in detail. The source–drain current (Ids) of devices is directly related to the BP thickness. The larger the BP thickness, the larger the Ids obtained under the same gate voltage modulation, but the electric field modulation effect decreases. Especially, the correlation between Ids and BP thickness can be described by a semi-empirical formula, which predicts that only when the BP thickness is less than 21.7 nm, the band structure of BP will be significantly affected by the thickness. The mobility of the carrier increases with the increasing of the BP thickness; for BP thickness of 6 nm, 20 nm, 30 nm, 40 nm, and 50 nm, the mobility is about 52.5 cm2/Vs, 187.5 cm2/Vs, 214.4 cm2/Vs, 252.5 cm2/Vs, and 336.4 cm2/Vs. Finally, the 50 nm BP in FET was etched to 30 nm using plasma etching technology to further verify the above experimental results. It also confirmed that plasma etching methods tend to introduce structural damage and impurity elements, which in turn has an impact on the output characteristics of the device.
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Perina, Welder, Joao Martino, and Paula Agopian. "(Digital Presentation) Analysis of MIS-HEMT Kink Effect in Saturation Region." ECS Meeting Abstracts MA2023-01, no. 33 (2023): 1873. http://dx.doi.org/10.1149/ma2023-01331873mtgabs.
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The High Electron Mobility Transistor (HEMT) has been widely used in the field of power electronics and high frequency operation since 1983 (1), while presenting a simple circuit design for analog applications (2, 3), and for extreme harsh environments as well (3, 4). However, HEMTs presents a problem with gate leakage and current collapse which can be solved by introducing an insulator between the gate and semiconductor while maintaining the high performance, hence the Metal Insulator Semiconductor High Electron Mobility Transistor (MIS-HEMT) appears as a solution. The AlGaN/GaN heterostructures forms, at the interface, a sheet with high electron density (2DEG – 2 Dimension Electron Gas), which also presents a high electron mobility. The MIS structure presents a well know conduction between source and drain. As a result, the MIS-HEMT device presents multiple conductions. The focus of this work is to study how the multiple conductions of the MIS-HEMT impact on the output characteristics. The studied devices are, a MIS-HEMT with the gate insulator composed of a 2 nm Si3N4, and a GaN MOSFET of 25 nm of Al2O3 as the gate insulator, both devices were fabricated at imec Leuven – Belgium, and have the same dimensions: gate width of 5 µm and gate length of 600 nm. Their respective schematics are presented at figure 1. The drain current (IDS) as a function of drain voltage (VDS) for a MIS-HEMT (left) and GaN MOSFET (right) with multiple overdrive voltage (VGT) is presented in figure 2. The VDS ranges for these devices are different because they have different saturation points, although it is possible to notice that the MIS-HEMT shows greater current drive when compared to MOSFET considering the same VDS, which is likely due to the formation of the 2DEG as the main conducting mechanism in the MIS-HEMT. Previous works (5 – 8) showed that the MIS-HEMT have multiple conduction mechanisms dependent on VGT, and figure 3 shows the effect of those multiple conductions on the output current of the device where it is very likely that one of those conductions have different VDS sat. It is possible to notice higher values of IDS with increasing VGT, as expected. However, for high enough VGT, there is an anomalous IDS increase (kink) in the saturation region, that occurs due to the different conduction mechanism (MOS and HEMT conductions). This effect will be called as MIS-HEMT kink effect (MH kink effect). This MH Kink effect occurs when the HEMT conduction mechanism overcomes the MOS conduction. The output conductance (gD) as a function of VDS for the MOSFET is presented in figure 4. Figure 5 shows gD as a function of VDS for multiple VGT for the MIS-HEMT, where it is possible to see a peak in the gD (in saturation region) shifting to the right for increasing VGT, caused by the MH kink effect. In order to better visualize, the VDS value for which the MH kink takes place, it is plotted as a function of VGT in figure 6. It is possible to see that as VGT increases, the MK kink effect shifts for higher VDS values, thanks to the higher electron density in 2DEG making the HEMT conduction less dependent on VDS. Figure 1
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Carvalho, Henrique Lanfredi, Ricardo Cardoso Rangel, Katia Sasaki, Leonardo Yojo, Paula Agopian, and Joao Martino. "Improved RFET Performance Using Dual-Aluminum-Contact (DAC)." ECS Meeting Abstracts MA2023-01, no. 33 (2023): 1855. http://dx.doi.org/10.1149/ma2023-01331855mtgabs.
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The reconfigurable field effect transistors (RFET) enable the integration of MOS-type transistors (N-type and P-type) in a single device. The programming gate voltage (VPG) controls the transistor type [1]. A greater area efficiency in logic circuits can be obtained, due to the possible different logic operation, such as NAND to NOR in a single circuit [2 - 3]. Others application include the use of RFET in circuits for security reason in order to avoid the reverse engineering [4]. Figure 1 (A) and (B) show a special type of RFET called BESOI MOSFET that will be one of the devices used in this work. Many conventional RFETs contain NiSi source/drain (S/D) contacts, or other contacts with mid-gap S/D material, providing a symmetrical current between holes and electrons. However such contacts decrease injection of current [5 - 7]. Devices based on dual-doping (DD), provided a significant improvement in the current level, in addition to the ease fabrication due to the absence of the silicidation process, such technology cannot act in doping-free CMOS processes [6] [8]. Figure 2 shows the drain current as a function of the control gate voltage (IDS -VCG) for the BESOI MOSFET. This work presents a new proposal for a dual-contact S/D (DC) RFET, without the presence of DD regions and doping process, enabling dopants-free CMOS processes, using only S/D aluminum contacts, performed through Sentaurus TCAD simulations [9]. Recently in the Integrable Systems Laboratory of the University of São Paulo (LSI-USP), two RFET with aluminum S/D contacts were reported. Both presented a high current for only one type of carrier (holes or electrons) [10 - 13]. The BESOI MOSFET conducts current through its back interface, where the channel between S/D contacts is formed by the bias of the programming gate (VPG), thus its operating mode is divided into P-type (VPG < 0 ) and N-type (VPG > 0). The transistor drain current is controlled by control gate voltage (VCG) [5] [10 - 11]. The Figure 3 shows the drain current balanced as a function of the control gate voltage (ID -VCG), for aluminum BESOI MOSFET’s with and without annealing process (W/A, Wo/A) after the metal deposition [10 - 11]. Using both BE SOI MOSFET with S/D aluminum contact, without process doping, a new RFET Dual Aluminum Contact (DAC) is shown Figure 4. The challenge the design is to flow of current (holes) through the outer contact (W/A contact), due to the influence of the inner schottky low-barrier aluminum contact (Wo/A contact) near to the back interface. Figure 5 shows the carrier density as a function of the depth of the silicon under the inner contact, for different silicon thicknesses (tSi) and fixed programming gate voltage (VPG). The high concentration of electrons near to the inner contact, provided an ohmic contact for electrons [11], however near the back interface, an increasing concentration of holes, due to VPG. Increasing the tSi reduces the influence of charges near the back interface, for tSi=30nm the current flow between the outer contact is possible. However, increasing the tSi decreases the efficiency of the control gate, added to the high electric field in back interface increases IOFF (similar effect described for FD SOI [14]). The Figure 6 shows the drain current as a function of the control gate voltage of BESOI nMOSFET with tSi = 30nm. Such effect can be mitigated, optimizing the coupling the gates. Figure 7 shows the final proposal of the BESOI MOSFET DAC. Figure 8 shows the IDS-VCG for different thicknesses in the S/D contacts (tsi cont). As shown in Figure 5, a greater thickness in the contacts makes possible a smaller influence of the inner contact near the back interface, allowing greater concentrations of gaps, so consequently there is an increase in the p-mode current. However, increasing the thickness of the contacts promotes a reduction in the electron current, due to the increase in the series resistance in inner contact in n-mode. Figure 9 presents the ID-VCG for different VPG bias for the DAC BESOI MOSFET (A) and NiSi BESOI MOSFET (B). Using the DAC BESOI MOSFET, an increase in current was obtained in relation to the NiSi contact (900% in n-type and 300% in p-type), without the addition of doping regions (dual-doping) and using a single contact metal (Aluminum). Figure 1
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Tamersit, Khalil, Abdellah Kouzou, José Rodriguez, and Mohamed Abdelrahem. "Electrostatically Doped Junctionless Graphene Nanoribbon Tunnel Field-Effect Transistor for High-Performance Gas Sensing Applications: Leveraging Doping Gates for Multi-Gas Detection." Nanomaterials 14, no. 2 (2024): 220. http://dx.doi.org/10.3390/nano14020220.
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In this paper, a new junctionless graphene nanoribbon tunnel field-effect transistor (JLGNR TFET) is proposed as a multi-gas nanosensor. The nanosensor has been computationally assessed using a quantum simulation based on the self-consistent solutions of the mode space non-equilibrium Green’s function (NEGF) formalism coupled with the Poisson’s equation considering ballistic transport conditions. The proposed multi-gas nanosensor is endowed with two top gates ensuring both reservoirs’ doping and multi-gas sensing. The investigations have included the IDS-VGS transfer characteristics, the gas-induced electrostatic modulations, subthreshold swing, and sensitivity. The order of change in drain current has been considered as a sensitivity metric. The underlying physics of the proposed JLGNR TFET-based multi-gas nanosensor has also been studied through the analysis of the band diagrams behavior and the energy-position-resolved current spectrum. It has been found that the gas-induced work function modulation of the source (drain) gate affects the n-type (p-type) conduction branch by modulating the band-to-band tunneling (BTBT) while the p-type (n-type) conduction branch still unaffected forming a kind of high selectivity from operating regime point of view. The high sensitivity has been recorded in subthermionic subthreshold swing (SS < 60 mV/dec) regime considering small gas-induced gate work function modulation. In addition, advanced simulations have been performed for the detection of two different types of gases separately and simultaneously, where high-performance has been recorded in terms of sensitivity, selectivity, and electrical behavior. The proposed detection approach, which is viable, innovative, simple, and efficient, can be applied using other types of junctionless tunneling field-effect transistors with emerging channel nanomaterials such as the transition metal dichalcogenides materials. The proposed JLGNRTFET-based multi-gas nanosensor is not limited to two specific gases but can also detect other gases by employing appropriate gate materials in terms of selectivity.
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Takeda, Yuki, Yuki Azuma, Ziye Zheng, Junichi Motohisa, and Katsuhiro Tomioka. "Demonstration of VGAA-TFETs using InAs/Si Heterojunction on SOI substrate." ECS Meeting Abstracts MA2024-02, no. 32 (2024): 2334. https://doi.org/10.1149/ma2024-02322334mtgabs.
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Introduction Miniaturization of field-effect transistors (FETs) have serious issues in enhanced leakage current, short-channel effect, and power consumption. In this regard, the vertical gate all-around (VGAA) structure using the III-V compound semiconductor nanowires (NWs) is expected as alternative transistor to solve the problems in leakage current and short channel effect. There is still challenge in decreasing power consumption of the FET because the reduction in subthreshold slope (SS) has physical limitation in thermionic carrier transport (SS = 60 mV/dec). Tunnel FETs (TFETs) can lower the SS less than the physical limitation in MOSFETs and are expected to be used as next-generation low-voltage switching devices. We have demonstrated vertical gate-all-around (VGAA) TFET using III-V/Si tunnel junction which was formed by the selective-area growth of III-V NWs on Si and achieved a steep SS characteristics and complementary operation [1]. These demonstrations should be expanded on silicon-on-insulator (SOI)(111) platforms toward circuit applications using the III-V/Si VGAA-TFETs. Here, selective-area growth of the InAs NWs on thin SOI(111) substrates and demonstrated InAs/Si VGAA-TFETs on SOI platforms. Experimental procedure First, a 35-nm-thick SiO2 film was formed on p-type SOI(111) by thermal oxidation. The SOI thickness was 600 nm. Periodical circular openings were formed using electron beam lithography and dry/wet etchings. Next, InAs NWs were grown by selective-area growth. Here, we used a pulse growth technique to orient NWs in the vertical <111>B direction on a nonpolar SOI substrate, making the substrate surface polar (111)B, and aligning vertical NWs [2]. Next, we fabricated VGAA-TFETs by using three-dimensional device process in previous reports [1]. First, Hf0.8Al0.2O were formed as gate oxides by atomic layer deposition (ALD). Next, 200 nm-thick tungsten (W) was deposited around the NW sidewalls as gate metal. After that source metal (Ti/Au) was evaporated 20 nm/50 nm on the substrate by EB vapor deposition. Next, benzocyclobutene (BCB) was used as isolation layer between gate and drain metals. Then drain metal (Ti/Pd/Au) was evaporated 20 nm/20 nm/50nm on the top of the NWs. Finally, the VGAA-TFETs were annealed at 350 - 400°C in order in N2 for ohmic contacts in the source and drain regions. VGAA-TFETs were measured after annealing for each temperature. Results The growth results showed vertical InAs NWs were successfully integrated on the p-SOI(111) substrates. The grown InAs NWs have hexagonal pillar structures surrounded with {-110} vertical facets and (111) B planes. Each NWs were composed of axial Zn-pulse doped intrinsic/Si-doped n-type/Sn-pulse doped n+-type NW segments. The average height is inversely proportional to the square of the diameter. Therefore, as similar to the conventional selective growth of InAs NWs on Si(111), the surface diffusion process of In atoms was dominant for the NW growth on SOI(111) surface. Transfer characteristics of the fabricated VGAA-TFET after annealed at 350°C indicated the tunnel current in the InAs/Si tunnel junction was electrically modulated by gate bias. The minimum SS was 37 mV/dec at VDS = 0.50 V, which was less than the theoretical limitation of conventional MOSFETs. The on-state current was 21 nA/μm at drain and source (VDS) of 1.00 V. The off current was 6.5 fA/μm when VDS was 1.00 V. Also, the threshold voltage (VTH) was 0.55 V. Transconductance was 31 nS/μm at VDS = 0.50 V. The measured current and transconductance were normalized by the number of NWs and the gate outer perimeter. We also investigated anneal temperature dependence of the device performance. The increasing in anneal temperature slightly lowered the minimum SS from 37 mV/dec to 23 mV/dec. And the on-state current was increased with increasing the anneal temperature. However, nonlinearity in the output IDS – VDS curve was enhanced with increasing the anneal temperature. This was assumed to be formed Schottky contact on the source metal. At the higher anneal temperature above 380°C, Ti/Au source metal possibly formed silicide (TiSi2) layer at the Ti/p-SOI interface. Thus, the contact resistance was decreased by the silicidation, and the on-state current was increased. However, Schottky contact of Au/Si was partially formed through the silicidation layer due to the very thin Ti interlayer. One of the possible approaches was to increase the Ti thickness or to use Al or Cu as single layer film. Further improvement of the device performance will be discussed. [1] K.Tomioka et al., IEEE IEDM. Tech. Dig. (2020) 429-432 [2] K.Tomioka et al., Nano Lett. 8(2008) 3475-3480
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Khanwalker, Mukund, Mika Hatada, Ellie Wilson, et al. "Development of an In Vivo, Real-Time and Continuous Insulin Sensor Utilizing an Extended Gate Field Effect Transistor-Based Transducer." ECS Meeting Abstracts MA2024-02, no. 64 (2024): 4315. https://doi.org/10.1149/ma2024-02644315mtgabs.
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Introduction In this paper, we aim to utilize an extended gate field-effect transistor (EGFET)-based transducer to measure insulin. The design of EGFETs is characterized by a unique structural arrangement, where a physical barrier exists between the semiconductor component and the analyte or physical medium. Due to this structure, EGFET possesses the advantage of protecting the electrode from intricacies within the measurement solution or medium. The need for a redox probe is also effectively eliminated by incorporating EGFETs, marking a significant breakthrough in electrochemical measurement. The lack of a redox probe allows EGFET-based sensors to conduct measurements with minimal invasiveness and enhanced biocompatibility in accordance with an in vivo monitoring system. As the target analyte is not required to be electrochemically active, EGFET is highly customizable for a wide range of targets, including neurotransmitters, biomarkers, and metabolites. Therefore, we constructed immunosensors immobilized with anti-insulin single-chain antibody (scFv) and measured insulin levels, with the objective of creating an in vivo sensor designed to improve glycemic management. We aimed to implement the inherent semiconductor properties of EGFETs by performing real-time monitoring of changes in electrical properties to quantify various insulin concentrations. Methods Development of an in vivo sensor requires the use of a platform that can be implemented within an in vivo environment. For this purpose, we utilized a gold microwire electrode immobilized with anti-insulin scFv. The gold microwire electrodes were prepared by electrochemically cleaning and further roughening them to increase the active surface area for the purpose of improving immobilization of the antibody. To achieve site-specific immobilization of anti-insulin scFv, we employed a nickel-chelated nitrilotriacetate self-assembled monolayer (Ni-NTA SAM). As the scFv harbors a histidine tag and Ni-NTA has an affinity for histidine residues, we were able to achieve oriented immobilization on the electrode surface. Within this study, we compared the effects of covalent immobilization, which leads to random orientation with the antibody, and non-covalent oriented immobilization by comparing the signal obtained from EGFET measurement. EGFET measurements were conducted using a transistor consisting of source, drain, and gate terminals. In this configuration, a constant potential was maintained between the source and drain terminals, while a sweeping potential was applied between an Ag/AgCl reference electrode and the source terminal. Measurement of insulin was performed within a buffer and artificial interstitial fluid (aISF) to model an in vivo environment. Results and Discussion The interaction between insulin and the immobilized anti-insulin scFv on the electrode surface induces a shift in surface potential, driven by the redistribution of charges across the extended gate. The change in surface potential leads to a subsequent modification of the gate potential, known as Vg. The gate potential, when less than the threshold voltage (Vth), operates in the cutoff region where little to no current is present. However, when Vg is greater than Vth, the system operates in the ohmic region where current can flow. The following relationship allowed us to monitor the drain-source current or Ids within the ohmic region to evaluate insulin concentrations. The signal change due to insulin binding to anti-insulin scFv was observed at a reference voltage of 0.6 volts. Conclusion We measured insulin concentrations using an electrode modified with anti-insulin scFv and demonstrated that EGFET can be used as a working principle for an in vivo monitoring system. Additionally, the measurement principle does not require a redox probe within the measurement solution. Future work will include implanting the anti-insulin scFv immobilized gold microwire electrode within a rat model and measuring insulin.
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Taniyama, Keita, Yuki Takeda, Yuki Azuma, Ziye Zheng, Junichi Motohisa, and Katsuhiro Tomioka. "Selective-Area Growth of InGaAs Nanowires on SOI and the Vertical Transistor Application." ECS Meeting Abstracts MA2024-02, no. 32 (2024): 2333. https://doi.org/10.1149/ma2024-02322333mtgabs.
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INTRODUCTION Conventional field-effect transistors (FETs) are expected to have new gate structures and channel materials to avoid serious issues caused by the miniaturization of FETs, such as enhanced leakage currents and short-channel effects. With this regard, III-V compound semiconductor nanowires (NWs) have attracted much attention as one of the alternative channel materials because of their fast carrier mobility and compatibility with the gate-all-around (GAA) structure. We have demonstrated vertical GAA (VGAA) field-effect transistors (FETs) using InGaAs NWs on Si [1]. For circuit applications, this demonstration must be expanded on silicon-on-insulator (SOI) platforms. Here, we demonstrated the selective growth of vertical InGaAs NWs on SOI (111) and InGaAs VGAA-FETs on SOI (111). EXPERIMENTS The InGaAs nanowires (NWs) were grown on n-type silicon-on-insulator (SOI) substrates by the selective-area epitaxy. The SOI layer had a thickness of 600 nm. First, a 15-nm-thick SiO2 film was formed on SOI (111) by thermal oxidation. Next, we formed circular mask openings using electron beam lithography, reactive ion etching (RIE), and wet etching. Then, after the formation of (111) B-polar surface [2], we grew InGaAs NWs by metal-organic vapor phase epitaxy (MOVPE). Trimethylgallium (TMGa), trimethylindium (TMIn), and arsine (AsH3) were used as precursor materials. In addition, silane (SiH4), diethylzinc (DEZn), and tetraethyltin (TESn) were used as n-type and p-type dopants. Next, we fabricated VGAA-FETs. At first, we deposited a 10-nm-thick Hf0.8Al0.2O gate oxide film using atomic layer deposition (ALD). Next, we deposited a 200-nm-thick tungsten (W) film for the gate electrode by sputtering. Then, we covered the NWs with benzocyclobutene (BCB) by spin coating and etched the BCB, W, and Hf0.8Al0.2O, and top of the NWs, simultaneously. We repeated the BCB coating and the etching process to isolate the gate and drain electrodes. Then, we formed a drain electrode (Ti/Pd/Au) on top of the NWs, and a source electrode (Ni/Au) on the n-SOI surface by evaporation. Finally, to obtain an ohmic contact between the electrode and the NW, we annealed the devices at 420°C in N2. RESULTS The InGaAs NWs were vertically aligned on n-type SOI (111) substrates by the selective-area epitaxy, indicating (111) B-oriented surface was formed on SOI (111). The average diameter of the NW was 70 nm, and the average height was 2000 nm. The NWs had axial segments: Zn pulse-compensated intrinsic segment, Si-doped n-type segment, and Sn pulse-doped n-type segment. The segment heights were 800 nm, 240 nm, and 960 nm, respectively. The VGAA-FETs using the InGaAs NWs on an SOI substrate exhibited moderate switching characteristics. The VGAA-FETs had a threshold voltage (VTH) of 1.0 V and a subthreshold slope (SS) of 178 mV/dec. The on-off current ratio was 104 and the on-state drain current (Ids) was 7.6×10-4 μA/μm at the drain-source voltage (VDS) of 0.5 V. The transconductance (gm) was 2.0×10-3 μS/μm and the gate leakage current was approximately 9.5×10-3 pA/μm at VDS of 0.5V. The SS was slightly higher than the minimum SS at room temperature (60 mV/dec). This was caused by a high off-leakage current. The high off-leakage current originated from the quality of the oxide/NW interface and the gate-induced barrier lowering. In the output characteristics, the linear region exhibited a nonlinear curve. This was because Schottky contact was formed between the Ni/Au and the Si interface due to the thin Ni layer. The output characteristics indicated that the off-state leakage current was also modulated by negative VGS. This was because the SOI layer was electrically floated due to the above incomplete Ohmic contact and may have been modulated by the gate voltage. In the conference, the details of the selective area growth method of vertical InGaAs NWs and the improvements in the VGAA-FETs properties will be discussed. [1]. K. Tomioka et al., Nature 488 (2012) 189. [2]. K. Tomioka et al., IEEE J. Selec. Top. Quant. Elec. 17 (2019) 1112.
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Duarte, Pedro Henrique, Ricardo Cardoso Rangel, Daniel Augusto Ramos, et al. "Back Gate Bias Influence on BESOI ISFET Sensitivity." ECS Meeting Abstracts MA2023-01, no. 33 (2023): 1870. http://dx.doi.org/10.1149/ma2023-01331870mtgabs.
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The application of Field Effect Transistors (FETs) to sensors and biosensors allows a mass production, low cost, small size, fast response and, also, the possibility of integrating the device and conditioning signal circuit in the same integrated circuit (IC). The Ion Sensitive Field Effect Transistor (ISFET), invented in 1970 by Piet Bergveld (1), is a device similar to the conventional Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), except that the metal gate is replaced by an inert electrode/pseudo electrode and a sample solution, in order to expose the gate oxide layer to ions present in the solution. The solution charges change the electrical potential in the gate oxide surface and, consequently, the device threshold voltage changes as a function of the ion concentration in the sample solution, being used as a pH sensor. Thus, the ISFET is a very promising device to Point-of-Care (POC) monitoring, such as COVID-19 control (2) and for continuous in vivo monitoring ion activity in biological processes (3)-(6). The BESOI (Back Enhanced Silicon-On-Insulator) MOSFET is a device patented in 2015 by João Antonio Martino and Ricardo Cardoso Rangel (7). This device is easy to fabricate and low cost. In the last years, the research using this device as a sensor/biosensor has been done (8)-(14). This paper presents, for the first time, the BESOI MOSFET working as an Ion Sensitive Field Effect Transistor (ISFET): the BESOI ISFET. Therefore, the focus of this work is to study the device electrical behavior influenced for pH standard solutions. The BESOI ISFET was fabricated at Integrated System Laboratory (LSI) from University of Sao Paulo (USP), Brazil. It is a planar device made on a SOI (Silicon-On-Insulator) wafer with three conventional photolithography steps, in an analogous way to previous work (15) and one more photolithography step to create microchannel and microreservoirs with SU-8 (16) layer to contain the sample solution. The wafer has no doping process (there is only the natural wafer doping of 1015 cm-3). The silicon channel layer and the gate oxide (SiO2) thicknesses are 10 nm and 25 nm, respectively. The buried oxide layer thickness is 200 nm. The drain and source contacts are fabricated with nickel and the contact pads using aluminum. The Figure 1 presents the final device layout and the Figure 2 shows the device schematic drawn. Differently from a conventional ISFET, where the drain current flows at the front interface, in the BESOI ISFET the drain current flows at the back interface. As the BESOI ISFET is a non-intentionally doped device, the free conduction charge layer is formed by biasing the Back Gate electrode (VGB). When a positive enough VGB is applied, electrons are attracted and accumulated at the back interface, and therefore, current flows from source to drain when VDS (Drain bias) is applied. A Platinum (Pt) pseudo-electrode is used to apply front-gate voltage (VGF) to the sample solution. The experimental drain current (IDS) as a function of the front-gate voltage (VGF), for 25 V applied at the back-gate (VGB), is presented in Figure 3.A, which is possible to observe that the neutral pH (pH7) curve stayed between the acid pH (pH4) curve, in the left, and alkaline pH (pH10) curve, in the right. This result shows that the threshold voltage (VTH) is lower for acid pH and higher for alkaline pH, what is compatible with the conventional ISFET results present in the literature (17). To corroborate the experimental measurement result, the device simulation was made with TCAD-Sentaurus (18), based in the paper (19). Figure 3.B shows the same trend for the simulated device with pH solution for any VGB value. In Figure 4, the threshold voltage was analyzed as a function of the pH for different VGB values. The VTH increases (becomes more positive) for alkaline pH values, regardless of the VGB applied. However, the VTH variation in the pH range, between pH4 and pH10, is different for different VGB values. With higher VGB applied, higher is the VTH variation. In Figure 5 Is possible to see clearly that the sensitivity (ΔVTH /ΔpH) increases with the VGB increase probably due to the small influence of the series resistance. In another hand, the acquired sensitivity values for VGB higher than 15 V in this work (about 25-33 mV/pH, approximately), is compatible with results present in the literature for conventional ISFETs with silicon dioxide (SiO2) for gate insulator (20). Figure 1
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Diniz, Jose Alexandre, Rodrigo REIGOTA César, Angelica Denardi Barros, et al. "(Invited) ISFET-Based Sensors." ECS Meeting Abstracts MA2023-01, no. 33 (2023): 1868. http://dx.doi.org/10.1149/ma2023-01331868mtgabs.
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The big difference between an ISFET (Ion Sensitive Field Effect Transistor) and a conventional MOSFET (Metal Oxide Semiconductor FET) is contained in the absence of the upper electrode on the gate oxide of the device, as shown in Figures 1 (a) and 1(b), respectively. In the case of an ISFET (Figure 1(a)), the gate reference electrode with the solution (of chemical or biological materials), which is in contact with the gate oxide (dielectric), work as the upper electrode, inducing the channel in the semiconductor and enabling the conduction of electric current between source and drain terminals. On these two terminals, there are the polymer layers as barrier against chemical or biological solutions. Therefore, the choice of the gate oxide is of great importance, since it must present chemical stability when in contact with the solution that will be measured. The solution pH is the main parameter which is measured. The gate dielectric chosen for application as a pH sensor must carry out measurements in acidic and basic media and be capable of forming hydrogen bonds. This ability is associated with atoms that have greater electronegativity such as fluorine, oxygen and nitrogen. Furthermore, the water contamination metals, DNA, RNA, enzymatic, antigen-antibody and cell related detections can be obtained by ISFETs.Thus, thin films of SiNx, TiOx, TaOx, AlOx and AlN were chosen as gate dielectrics because are compatible to chemical or biological substances. Various results from literature will be present. For example, pH ISFET devices with silicon nitride (SiNx) as gate dielectric were fabricated [2]. Silicon nitride (SiNx) films have been obtained by Low Pressure Chemical Vapor Deposition (LPCVD) at temperature of 720oC for 30 min, using different ratios of [SiH2Cl2]/[NH3] reagent gases. These films been used as ISFET gate dielectric. Figure 2 presents a characteristic of the current between source and drain (IDS) versus voltage between source and gate (VGS) of ISFETs (for voltage VDS of 2V) in related to the four values of pH solution. In this case, sensibility of S=51mV/pH [2]. was estimated, which is close to the expected 59mV/pH determined by the Nernst limit. Other application: Controlling the water quality has become an important issue nowadays, especially due to its contamination along the years which may cause significant damage to human health and in this context, phosphate in water reuse or lead deserves a great attention. The Electrolyte-Insulator-Semiconductor (EIS) structure, which is similar to the gate structure of ISFETs, with TiO2 thin films as gate dielectric, were fabricated and Capacitance x Voltage (CxV) curves to estimate the sensitivity values through the flat-band voltage variation for each curve. In order to enhance the Pb+ detection an additional cerium phosphate layer (TiO2 surface functionalization) was deposited over the TiO2 thin film as selective membrane for Pb+ measurements and the device presented 40 mV/100 ppm sensitivity. For the case of phosphate detection in waste water, EIS devices with TiO2 films as gate dielectric, without functionalization layer, were used and the good sensitivity to phosphate ions of 66 mV/ppm was obtained. Most of results with ISFET devices are based on Si semiconductor conduction channel between the source and drain regions. Others materials have been used as conduction channels of transistors, such as 2D layer, mainly graphene. One example is the biosensor based on Graphene Field Effect Transistor (GraFET), using the TiO2 dielectric gate, capable of being applied effectively for early diagnosis of COVID-19. The graphene channel has ten parallel ribbons, and the virus of SARS-Cov-2 interacts with the unprotected TiO2 gate dielectric. Unlike rapid tests, which depend on the body's immune response (production of IgM and/or IgG antibodies), this project seeks to detect components of the infectious agent itself. It makes graphene-based biosensors very advantageous compared to current tests available since there will be no dependence on the immune response to infection by COVID-19 but only on the presence of the virus in the tested samples. Thus, these devices can reduce the time involved in the analyses. In conclusion, as observed in this review, the ISFET devices are mandatory sensors to develop the future instrumentation, because allow the detection of various chemical and biological species, using different materials as gate dielectrics or electrodes, and conduction channels. Figure 1
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Williams, Kia, and Pablo Fanjul. "Cell Culture Monitoring using Coplanar Electrochemical Transistors." ECS Meeting Abstracts MA2022-01, no. 42 (2022): 1831. http://dx.doi.org/10.1149/ma2022-01421831mtgabs.
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In vitro cell death process monitoring is a method widely used in medical and pharmacological studies to know the effect of drugs and toxins on tissue models. This work presents a study of cell viability using commercial platforms designed for the generation of electrochemical transistors as sensor devices for different cultures of HEK294 embryonic kidney cells. In this work, we cover the idea of using an electrochemical transducer-based device to measure the number of cells deposited or growing on the source-drain channel. Using this method, it has been observed that the deposited cells behave like the semi-conductor material. Therefore, drain-source intensity versus gate-source voltage varies depending on the number of cells that are covering the drain-source system, with the measured intensity increasing with the growing number of cells. The electrochemical signals of different cultures have been compared to the number of cells measured by microscopy and a correlation has been performed. Different cell cultures have been evaluated before and after, and considerable decreases in current intensity have been observed, indicating that damage has taken place. Therefore, these transistors have proven to be an alternative for the study of cell viability, maintaining the integrity of the sample and being able to increase the number of studies performed on it. In addition, the monitoring of the evolution of cellular activity can be performed simpler and faster, providing comparable results with the advantage of maintaining a usable sample. This work was supported by the Project "NANOBIO-TEER" (IDE/2018/000485 and IDE/2018/000415), co-financed through IDEPA and ERDF fund.
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Shlimak, I., A. Butenko, D. I. Golosov, K. J. Friedland, and S. V. Kravchenko. "Current Induced Spin Injection in Si-MOSFET." Solid State Phenomena 190 (June 2012): 129–32. http://dx.doi.org/10.4028/www.scientific.net/ssp.190.129.
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Longitudinal resistivity in strong parallel magnetic fields up to B = 14 Tesla was measured in Si-MOSFET with a narrow slot (90nm) in the upper metallic gate that allows to apply different gate voltage across the slot and, therefore, to control the electron density n1 and n2 in two parts of the sample independently. The experimental scheme allows us to pass through the source-drain channel relatively large DC current (IDC), while the dynamic resistance was measured using a standard lock-in technique with small AC current. It was shown that the sample resistance is asymmetric with respect to the direction of DC current. The asymmetry increases with increase of magnetic field, DC current, and difference between n1 and n2. Results are interpreted in terms of a current-induced spin accumulation or depletion near the slot, as described by a spin drift-diffusion equation. The effect on the sample resistance is due to the positive magnetoresistance of Si-MOSFETs in parallel magnetic fields.
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Lee, Sanguk, Jinsu Jeong, Bohyeon Kang, et al. "A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs." Nanomaterials 13, no. 5 (2023): 868. http://dx.doi.org/10.3390/nano13050868.
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This study proposed a novel source/drain (S/D) extension scheme to increase the stress in nanosheet (NS) field-effect transistors (NSFETs) and investigated the scheme by using technology-computer-aided-design simulations. In three-dimensional integrated circuits, transistors in the bottom tier were exposed to subsequent processes; therefore, selective annealing, such as laser-spike annealing (LSA), should be applied. However, the application of the LSA process to NSFETs significantly decreased the on-state current (Ion) owing to diffusionless S/D dopants. Furthermore, the barrier height below the inner spacer was not lowered even under on-state bias conditions because ultra-shallow junctions between the NS and S/D were formed far from the gate metal. However, the proposed S/D extension scheme overcame these Ion reduction issues by adding an NS-channel-etching process before S/D formation. A larger S/D volume induced a larger stress in the NS channels; thus, the stress was boosted by over 25%. Additionally, an increase in carrier concentrations in the NS channels improved Ion. Therefore, Ion increased by approximately 21.7% (37.4%) in NFETs (PFETs) compared with NSFETs without the proposed scheme. Additionally, the RC delay was improved by 2.03% (9.27%) in NFETs (PFETs) compared with NSFETs using rapid thermal annealing. Therefore, the S/D extension scheme overcame the Ion reduction issues encountered in LSA and significantly enhanced the AC/DC performance.
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Zhang, Xiaorui, Huiping Zhu, Song’ang Peng, et al. "Radiation-hardened property of single-walled carbon nanotube film-based field-effect transistors under low-energy proton irradiation." Journal of Semiconductors 42, no. 11 (2021): 112002. http://dx.doi.org/10.1088/1674-4926/42/11/112002.
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Abstract Strong C–C bonds, nanoscale cross-section and low atomic number make single-walled carbon nanotubes (SWCNTs) a potential candidate material for integrated circuits (ICs) applied in outer space. However, very little work combines the simulation calculations with the electrical measurements of SWCNT field-effect transistors (FETs), which limits further understanding on the mechanisms of radiation effects. Here, SWCNT film-based FETs were fabricated to explore the total ionizing dose (TID) and displacement damage effect on the electrical performance under low-energy proton irradiation with different fluences up to 1 × 1015 p/cm2. Large negative shift of the threshold voltage and obvious decrease of the on-state current verified the TID effect caused in the oxide layer. The stability of the subthreshold swing and the off-state current reveals that the displacement damage caused in the CNT layer is not serious, which proves that the CNT film is radiation-hardened. Specially, according to the simulation, we found the displacement damage caused by protons is different in the source/drain contact area and channel area, leading to varying degrees of change for the contact resistance and sheet resistance. Having analyzed the simulation results and electrical measurements, we explained the low-energy proton irradiation mechanism of the CNT FETs, which is essential for the construction of radiation-hardened CNT film-based ICs for aircrafts.
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Gong, Xiao, Kaizhen Han, Chen Sun, et al. "Beol-Compatible Ingazno-Based Devices for 3D Integrated Circuits." ECS Meeting Abstracts MA2022-02, no. 32 (2022): 1186. http://dx.doi.org/10.1149/ma2022-02321186mtgabs.
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Due to its attractive materials and electrical properties, indium-gallium-zinc-oxide (IGZO) has been extensively researched in many emerging technologies, especially for three-dimensional (3D) monolithic integration and back-end-of-line (BEOL) compatible applications [1]. On the pathway toward the realization of high-performance 3D monolithic integrated chips (ICs), a wide range of building blocks with different functionalities are required. 3D monolithic ICs also demand optimization in device performance and circuit architecture design. In this paper, we discuss our recent research development in IGZO-based techniques at both device and circuit levels. This includes nanowire structure for IGZO-based transistors, as well as the BEOL-compatible ferroelectric ternary content-addressable memory (TCAM) and embedded dynamic random-access-memory (eDRAM) for compute-in-memory (CiM) using IGZO-based transistors. A novel digital etch technique for amorphous IGZO (α-IGZO) material as well as the formation of α-IGZO nanowires were realized, enabling high performance α-IGZO nanowire field-effect transistors (NWFETs) with ultra-scaled nanowire width (W NW) [2]. The scanning electron microscopy (SEM) images of α-IGZO nanowire before and after the digital etch show that the nanowire structure as well as W NW reduction after digital etch can be clearly observed. The smallest α-IGZO nanowire after digital etch has a W NW of ~20 nm. By leveraging the ultra-scaled nanowire structure, the NWFET with the smallest W NW achieves decent subthreshold swing of 80 mV/decade as well as high peak extrinsic transconductance (G m,ext) of 612 μS/μm at a drain to source voltage (V DS) = 2 V (456 μS/μm at V DS = 1 V). As compared with previous works in literature, our IGZO NWFET achieves one of the highest peak G m among all IGZO-based FETs. α-IGZO ferroelectric FETs (Fe-FETs) with a metal-ferroelectric-metal-oxide-semiconductor (MFMIS) structure were further realized based on the α-IGZO transistor process modules. The smallest L CH is as small as 40 nm. The cross-sectional transmission electron microscopy (TEM) image of the device shows sharp interface. The α-IGZO Fe-FETs achieve a large memory window of 2.9 V, high endurance of 108 cycles, high conductance ratio, and small cycle-to-cycle variation. By leveraging the low temperature processed α-IGZO Fe-FETs with good electrical characteristics, a BEOL-compatible ferroelectric TCAM circuit with 2 Fe-FETs connected in parallel was realized [3], showing an extremely large sensing margin. In addition, such α-IGZO Fe-FET TCAM reduces the transistor number from 16 to 2 as compared to traditional SRAM-based TCAM. Smaller cell size and higher energy efficiency can also be obtained. IGZO transistors can play an important role in in-memory computing as well. SEM image of the eDRAM CiM cell shows utilization of IGZO transistors. The smallest device has L CH of 45 nm [4]. The IGZO transistor-based eDRAM CiM with differential cell structure achieves low leakage current, low variation, low charge loss sensitivity, and the control-friendly charge-domain computing without DC power. By evaluating the key figure-of-merits, including precision, power efficiency, computing density, retention time, and robustness, it can be concluded that our IGZO transistor-based eDRAM CiM is promising for low-power and scalable compute-in-eDRAM design. Acknowledgments: This work is supported by Singapore Ministry of Education (Tier 2: MOE2018-T2-2-154, Tier 1: R-263-000-D65-114). References: [1] K. Normura et al., Nature, 432 (7016), 488-492, 2004. [2] K. Han et al., VLSI, 2021, p. T10-1. [3] C. Sun et al., VLSI, 2021, p. T7-4. [4] J. Liu et al., IEDM, 2021, p. 462.
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Parvez, Bazila, Jyoti Sahu, Subhajit Basak, et al. "Asymmetric Gate and SiC Substrate Grooved InGaN Back‐Barrier AlGaN/GaN HEMTs for High‐Power RF Applications." physica status solidi (a), January 22, 2024. http://dx.doi.org/10.1002/pssa.202300708.
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We report high‐power InGaN back‐barrier AlGaN/GaN high electron mobility transistors with the gate placed closer to the source with an Au‐filled groove in the SiC substrate near the drain end. An InGaN back‐barrier is known to reduce short‐channel effects at high drain‐to‐source (VDS) voltage. However, the improvement is realized at the cost of reduced two‐dimensional electron gas density (ns) and saturation drain‐to‐source (IDS,SAT) current. Here, we demonstrate that both ns and IDS,SAT are recovered when the gate is appropriately delineated near the source. The junction temperature increases at higher VDS, which tends to deteriorate the power performance and suppress the benefits from higher IDS,SAT. This problem is contained by further thinning down the SiC substrate near the drain by creating a backside groove using deep reactive‐ion‐etching and filling it with Ti/Au. An enhanced thinned‐down substrate distributes the lateral electric field uniformly near the drain end, compounding its benefits with an asymmetric gate and lower junction temperature. The proposed device shows an output power of Pout = 6.7 W mm−1 at VDS = 28 V at 15 GHz for a 200 nm gate length (LG).
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Chen, Chun-Ying, and Jerzy Kanicki. "Influence Of The Density of States and Series Resistance on the Field-Effect Activation Energy in a-Si:H TFT." MRS Proceedings 424 (1996). http://dx.doi.org/10.1557/proc-424-77.
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AbstractWe have proposed a new two-dimensional simulation model, which takes into account the density of states of hydrogenated amorphous silicon (a-Si:H) and temperature-dependence of the source/drain series resistances (Rs), to explain the dependence of the activation energy (Eact) of drain-source current (IDs) on gate-source bias (VGs) in a-Si:H thin-film transistors (TFTs). We found that the influence of series resistance cannot be ignored, else an overestimated Eact will result. The results of our simulation are in agreement with experimentally observed saturation of the Eact at higher VGs.
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Alam, Md Zafar, Imran Ahmed Khan, S. Intekhab Amin, Aadil Anam та Mirza Tariq Beg. "Design and Analysis of High‐Performance Schottky Barrier β‐Ga2O3 MOSFET With Enhanced Drain Current, Breakdown Voltage, and PFOM". International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 38, № 1 (2024). https://doi.org/10.1002/jnm.70009.
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ABSTRACTIn this article, a Schottky barrier β‐Ga2O3 MOSFET is proposed. It shows improvements in drain saturation current, Ion/Ioff ratio, transconductance, and off‐state breakdown voltage. The proposed design, which implements the Schottky barrier source and drain contacts, has led to reduced on‐state resistance (Ron), reduced forward voltage drops, faster switching speed, higher frequency, and improved efficiency. After device optimization, we determined that a source and drain having a work function of 3.90 eV result in the highest drain saturation current of (Ids) 264 mA. Additionally, in the transfer characteristics, we demonstrate that increasing the channel doping concentration led to a shift toward depletion mode operation, while decreasing the doping concentration moved the device toward enhancement mode at the cost of drain current. Analysis of lattice temperature and self‐heating effects on different substrates has also been performed. Furthermore, introducing a passivation layer of SiO2 as a gate oxide and an unintentionally doped (UID) layer of 400 nm doping concentration of 1.5 × 1015 cm−3, results in further significant improvements in the drain saturation current (Ids) of 624 mA and transconductance of 38.09 mS, approximately doubling their values compared with the device without a passivation layer of SiO2 and an Ion/Ioff ratio of 1015, and the device's performance at various substrate temperatures has been evaluated. In addition, the inclusion of a passivation layer of SiO2 improves the breakdown voltage to 2385 V, which is significantly high compared with the conventional device. Moreover, the lower specific‐on‐resistance Ron,sp of 7.6 mΩ/cm2 and higher breakdown voltage then the high‐power figure of merit (PFOM) (BV2/Ron,sp) of 748 MW/cm2 have been achieved.
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Cao, Shu-rui, Rui-ze Feng, Bo Wang, Tong Liu, Peng Ding, and Zhi Jin. "Impact of Gate Offset in Gate Recess on DC and RF Performance of InAlAs/InGaAs InP-based HEMTs." Chinese Physics B, December 24, 2021. http://dx.doi.org/10.1088/1674-1056/ac464f.
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Abstract In this work, a set of 100-nm gate-length InP-based HEMTs were designed and fabricated with different gate offsets in gate recess. A novel technology was proposed for independent definition of gate recess and T-shaped gate by electron beam lithography. DC and RF measurement was conducted. With the gate offset varying from drain side to source side, the maximum drain current (Ids,max) and transconductance (gm,max) increased. In the meantime, f T decreased while f max increased, and the highest f max of 1096 GHz was obtained. It can be explained by the increase of gate-source capacitance and the decrease of gate-drain capacitance and source resistance. Output conductance was also suppressed by gate offset toward source side. This provides simple and flexible device parameter selection for HEMTs of different usage.
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Griep, S. "Geometry Dependence of the Transport Parameters in Field Effect Transistors Made from Amorphous Silicon." MRS Proceedings 149 (1989). http://dx.doi.org/10.1557/proc-149-283.
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ABSTRACTField effect transistors (TFTs) with different channel lengths L and widths W have been prepared to study the influence of the geometry on the characteristics of the transistors. The mobility μ and the threshold voltage Vth are determined from the √Ids (Uds) plot. Effective values of L and W can be determined by analyzing their dependence on geometry. It can be shown that parts of the amorphous silicon which are outside the area between the source and drain contacts contribute to the current. The reason for this is that the drain-source field spreads out into these regions. Taking this effect into account we obtain the values for the mobility μ. The part of the overlap contributing to the transistor current is smaller than 2 μm.
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A., Hamdoune, Abdelmoumene M., and Hamroun A. "Static and Dynamic Characteristics of an Appropriated and Recessed n-GaN/AlGaN/GaN HEMT." November 6, 2013. https://doi.org/10.5281/zenodo.1089575.
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The objective of this paper is to simulate static I-V and dynamic characteristics of an appropriated and recessed n-GaN/AlxGa1-xN/GaN high electron mobility (HEMT). Using SILVACO TCAD device simulation, and optimized technological parameters; we calculate the drain-source current (lDS) as a function of the drain-source voltage (VDS) for different values of the gate-source voltage (VGS), and the drain-source current (lDS) depending on the gate-source voltage (VGS) for a drain-source voltage (VDS) of 20 V, for various temperatures. Then, we calculate the cut-off frequency and the maximum oscillation frequency for different temperatures. We obtain a high drain-current equal to 60 mA, a low knee voltage (Vknee) of 2 V, a high pinch-off voltage (VGS0) of 53.5 V, a transconductance greater than 600 mS/mm, a cut-off frequency (f<sub>T</sub>) of about 330 GHz, and a maximum oscillation frequency (fmax) of about 1 THz.
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Khan, Md Arif, Rangrajan Muralidharan, and Hareesh Chandrasekar. "Physical design guidelines to minimize area-specific ON-resistance for rated ON-current and breakdown voltage of GaN power HEMTs." Semiconductor Science and Technology, February 3, 2023. http://dx.doi.org/10.1088/1361-6641/acb8d5.
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Abstract In this article, we report on the development of an analytical model to estimate area-specific ON-state resistance (RON) of GaN-based power high electron mobility transistor (HEMT) using rated device specifications – ON-state drain current (ION) and maximum operating drain-to-source voltage (VDSO) – as input parameters. The rated ION and VDSO are considered as fractions k and S, of the maximum possible drain current (IDS,max) and breakdown voltage (VBR), respectively, deliverable by the power device. The developed model is utilized to obtain the optimal physical design space parameters including unit gate width (W), number of unit gate fingers (N), source and drain electrode widths (L) and thickness (t), for a comb-like power HEMT design. Due consideration has been given to the trade-off between RON and area-specific RON of the transistor, and device processing limitations for all these parameters and the model has been benchmarked to experimental results. Our calculations impose a lower-bound for the best possible RON as well as the area-specific on-resistance product (RON × AA) that can be obtained for a given starting channel sheet resistance in the comb architecture for a desired ION – VDSO rating.
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Cai, Xiangzhen, Y. Q. Chen, and Changjian Zhou. "Total-ionizing dose irradiation induced degradation behavior and mechanism of the Cascode GaN HEMTs." Semiconductor Science and Technology, March 10, 2023. http://dx.doi.org/10.1088/1361-6641/acc34e.
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Abstract In this article, the effects of total ionizing dose (TID) irradiation and the annealing treatment on the degradation of the commercial Cascode GaN high-electron-mobility transistors (HEMTs) were investigated, and low frequency noise method (LFN) was carried out to analyze the defects. The DC characteristics show that the device after TID irradiation with different doses exhibits a negative drift of threshold voltage (Vth) and a remarkable increase of drain-source current (Ids) with respect to the fresh one. Meanwhile, with increasing doses of the TID irradiation, the off-state drain leakage current increases, while the drain-source resistance decreases. The gate-lag characteristic gets better for the Cascode GaN HEMTs after TID irradiation. The transfer characteristics, output characteristics, blocking characteristics and capacitance characteristics of the devices can partly be restored by annealing treatment, but there is no pronounced influence on the gate-lag characteristics and drain-source resistance. The trap density extracted by the LFN method decreases in the Cascode GaN HEMTs after TID irradiation. The degradation behavior and mechanism of the Cascode GaN HEMTs under TID irradiation are analyzed. The experimental results may provide a useful reference for the design and space application of the Cascode GaN HEMTs.
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Lee, Ching-Sung, Kuan-Ting Lee, Wei-Chou Hsu, Han-Yin Liu, Yang Wen-Luh, and Chien-Hung Ko. "Investigations on Al2O3-Dielectric Wide-Gap Al0.3Ga0.7N Channel MOS-HFETs with Composite Al2O3/In Situ SiN Passivation." ECS Journal of Solid State Science and Technology, July 7, 2022. http://dx.doi.org/10.1149/2162-8777/ac7f59.
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Abstract 3/in-situ SiN passivation and Al2O3 gate dielectric were investigated. 20 nm thick high-k Al2O3 was deposited using a non-vacuum ultrasonic spray pyrolysis deposition method. Comparative studies between an in-situ SiN-passivated Schottky-gate HFET (sample A) and a composite Al2O3/SiN-passivated MOS-HFET were made. Electrical and deep-UV sensing characteristics for devices with different gate-drain separations (LGD) of 6 and 14 μm were also studied. Improved device performance has been obtained for the present sample B (A) with LGD = 6/14 μm separately, including maximum drain-source current density (IDS, max) of 634.4/463.1 (421.8/301.1) mA/mm, maximum extrinsic transconductance (gm, max) of 25.2/17.9 (19.1/15.2) mS/mm, on/off-current ratio (Ion/Ioff) of 7.4 × 107/5.4 × 107 (4.5 × 105/5.4 × 104), two-terminal off-state gate-drain breakdown voltage (BVGD) of -420/-480 (-320/-390) V, and three-terminal on-state drain-source breakdown voltage of 310/380 (220/300) V at 300 K. Superior spectral responsivity of 885.6 A/W under 250-nm deep-UV radiation has also been achieved for the present MOS-HFET.
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Mamun, Md Ataul, Bennett Smith, Benjamin Horstmann, et al. "Measurement and control of stiction force in in-plane electrostatically actuated Si nanoelectromechanical cantilever relays with Pt contacts." Journal of Micromechanics and Microengineering, June 7, 2023. http://dx.doi.org/10.1088/1361-6439/acdc32.
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Abstract We measure the stiction force using in-plane electrostatically actuated Si nanoelectromechanical cantilever relays with Pt contacts. The average, current-dependent values of stiction force ranging from 60 nN to 265 nN were extracted using the IDS vs VGS hysteresis curves, the cantilever displacement information from finite element method (Comsol Multiphysics)simulations, and force distribution determined using an analytical model. It is shown that stiction force is inversely and directly proportional to the contact resistance (Rc) and drain-source current (IDS), respectively. Using the dependence of stiction force on contact current, we demonstrate the tuning of voltage hysteresis for a same relay from 8V to 36V (equivalent to a stiction force of 70 nN to 260 nN respectively). We attribute the stiction force primarily to the metallic bonding force which shows a strong dependence on the contact current.&#xD;
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Saha, Chinmoy Nath, Abhishek Vaidya, Noor Jahan Nipu, et al. "Thin channel Ga2O3 MOSFET with 55 GHz fMAX and >100 V breakdown." Applied Physics Letters 125, no. 6 (2024). http://dx.doi.org/10.1063/5.0208580.
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This Letter reports a highly scaled 90 nm gate length β-Ga2O3 (Ga2O3) T-gate MOSFET with a power gain cutoff frequency (fMAX) of 55 GHz. The 60 nm thin epitaxial Ga2O3 channel layer was grown by molecular beam epitaxy, while the highly doped (n++) source/drain regions were regrown using metal organic chemical vapor deposition. Maximum on current (IDS,MAX) of 160 mA/mm and trans-conductance (gm) around 36 mS/mm were measured at VDS = 10 V for LSD = 1.5 μm device. Transconductance and on current are limited by high channel sheet resistance (Rsheet). Gate/drain breakdown voltage of 125 V was measured for LGD = 1.2 μm. We extracted 27 GHz current gain cutoff frequency (fT) and 55 GHz fMAX for 20 V drain bias for unpassivated devices. While no current collapse was seen initially for both drain and gate lag measurements for 500 ns pulse, moderate current collapse was observed after DC, RF measurements caused by electrical stressing. We calculated a high fT. VBR product of 3.375 THz V, which is comparable to the state-of-the-art GaN HEMTs. This figure of merit suggests that Ga2O3 could be a potential candidate for X-band application.
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Sharma, Himani, and Zhigang Xiao. "Fabrication of Carbon Nanotube Field-Effect Transistors with Metal and Semiconductor Electrodes." MRS Proceedings 1057 (2007). http://dx.doi.org/10.1557/proc-1057-ii15-20.
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ABSTRACTCarbon nanotube field-effect transistors (CNTFETs) were fabricated with metal material (gold) and semiconductor material (bismuth telluride) as the source and drain materials. Highly-purified HiPCO-grown single-walled carbon nanotubes (CNTs) from Carbon Nanotechnologies, Inc. (CNI) were used for the fabrication of CNTFETs. The single-walled carbon nanotubes were ultrasonically dispersed in toluene and dimethylformamide (DMF) with trifluoroacetic acid (TFA), as co-solvent. Dielectrophoresis (DEP) method was used to deposit, align, and assemble carbon nanotubes (CNTs) to bridge the gap between the source and drain of CNTFETs to form the channel. The structure of CNTFET is similar to a conventional field-effect transistor with substrate acting as a back-side gate. Electron-beam evaporation was used to deposit gold and bismuth telluride thin films. Microfabrication techniques such as photolithography, e-beam lithography, and lift-off process were used to define and fabricate the source, drain, and gate of CNTFETs. The gap between the source and drain varied from 800 nm to 3 µm. The drain-source current (IDS) of the fabricated CNTFETs versus the drain-source voltage (VDS) and the gate voltage (VG) was characterized. It was found that in the case of gold (Au) electrodes, the IV curves of CNTFETs clearly show behavior of the CNT (metallic or semiconducting) aligned across the source and drain of CNTFETs, while in the case of bismuth telluride (Bi2Te3) electrodes, the I-V curves are less dependent on the type of CNTs (metallic or semiconducting). The developed carbon nanotube field-effect transistors (CNTFETs) can be a good candidate for the application of nanoelectronics and integrated circuits with a high mobility and fast switching.
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Lee, Seon Woo, Slava Rotkin, Andrei Sirenko, Daniel Lopez, Avi Kornblit, and Haim Grebel. "Gate Controlled Negative Differential Resistance and Photoconductivity Enhancement in Carbon Nanotube Addressable Intra-connects." MRS Proceedings 1142 (2008). http://dx.doi.org/10.1557/proc-1142-jj15-14.
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ABSTRACTWe have observed gate-controlled N-shaped negative differential resistance (NDR) and photoconductivity enhancement in carbon nanotube (CNT) based addressable intra-connects. The intra-connects – bridges spanning across planar electrodes – were measured at room temperature. Individual single-walled CNT (SWCNT) channels were grown using chemical vapor deposition (CVD) precisely between very sharp metal tips on the pre-fabricated electrodes without post-processing. The electrodes were made of cobalt. Methane and H2 gas mixture were introduced into quartz tube for an hour at 900 C, with flow rate of 1900 sccm for methane and 20 sccm for H2. We have investigated two different cases: in one case, the source-drain current-voltage, Ids-Vds, characteristics were linear. The other case exhibited nonlinear Ids-Vds characteristics. Raman scattering of the intra-connects indicated that each were made of SWCNT with radial breathing mode (RBM) at 191.9 cm-1 and 176.2 cm-1, respectively. Current-voltage Ids-Vds characteristics were measured for various Vgs from -10 V to +10 V. Negative differential resistance (NDR) was found in the Ids-Vgs curves for gate bias in the region of -3>Vgs>-6 V. The NDR peak was shifted to the negative side as the source-drain voltage was increased from Vds=0 to 0.75 V. Otherwise, the intra-connects exhibited characteristics of an ordinary p-type channel. The experiments were repeated under white light illumination. The light increases the carrier density in the channel but not in the metal electrodes and allowed us to study the effective doping of the channel without affecting the work function of the SWCNT/metal contact. The overall channel conductance increased under the light irradiation. Under illumination, the devices became more stable, as well. In summary, we have investigated contact properties between a SWCNT intra-connect and metal electrodes in a well controlled layout settings.
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Thakur, Anchal, Prashant Mani, Prabin Kumar Bera, Nishant Srivastava, Girish Wadhwa, and Antonino Proto. "Lateral Si/Si1‐xGex/Si Channel Heterostructure Charge Plasma Nanowire JLFET to Eliminate the Effects of Variation of Geometrical Dimensions." International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 38, no. 2 (2025). https://doi.org/10.1002/jnm.70042.
Full textAbstract:
ABSTRACTIn this article, a charge plasma (CP) based doping‐less (DL) nanowire junctionless field effect transistor (NW JLFET) has been investigated for better immunity against geometrical dimension variation from a low power application perspective. SiGe source/drain and Si/SiGe/Si heterostructure channel have been used to improve the electrostatics in the channel to reduce the leakage current. With this doping‐less structure, the concept of charge plasmas has been incorporated by selecting electrodes with appropriate work functions. In addition to a low thermal budget, the doping‐less devices are easier to fabricate, have a reduced random fluctuation effect, and offer a low cost per unit. The doping‐less structure also offers improved mobility and higher current flow. The proposed device is compared with the conventional SiGe nanowire junctionless FET. When both devices are compared, lateral Si/SiGe/Si CP DL NW JLFET shows fewer changes in geometrical dimension variation in terms of germanium content x, nanowire thickness (tsi) and doping profile (Nd) on the drain current (IDS), ION/IOFF ratio, threshold voltage (Vth), drain‐induced barrier lowering (DIBL), and subthreshold slope (SS). A drain current model for lateral Si/SiGe/Si CP DL NW JLFET has also been developed in this paper, which includes the impact of the charge plasma technique. The impact of geometrical dimension variation on the analog characteristics of both devices has been studied in terms of like transconductance (gm) and transconductance gain factor (TGF) (gm/IDS). Thus, in the lateral Si/SiGe/Si CP DL NW JLFET, the charge plasma technique along with channel engineering solves the problem of geometrical dimension variation without affecting the inherited properties of junctionless devices.
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Yoshida, Manabu, Sei Uemura, Satoshi Hoshino, Takehito Kodzasa, Satoshi Haraichi, and Toshihide Kamata. "High Performance Organic Field Effect Transistor Withanovel Top-And-Bottom Contact (TBC) Structure." MRS Proceedings 736 (2002). http://dx.doi.org/10.1557/proc-736-d7.7.
Full textAbstract:
ABSTRACTWe studied the features of the newly developed Top and Bottom Contact Field Effect Transistor (TBCFET) with organic semiconductor layers. TBCFETs with ca.0.5μm channel length (L) were fabricated and their transistor properties were measured. The output drain-source currents (IDS) of TBCFET were 1 to 2 orders of magnitude higher than those of ordinary planar type FETs with 100μm channel length. On the other hand, because of the TBC structure, off current tends to become larger in the TBCFET. Therefore, in order to solve this off-current problem, we intentionally formed the Schottky junction at the top electrode/semiconductor interface. As a result, the off current became about 2 orders of magnitude smaller than before the formation of the Schottky junction.