Relevant bibliographies by topics / DSP processor

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'DSP processor'

Author: Grafiati
Published: 4 June 2021
Last updated: 15 February 2022

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Journal articles on the topic "DSP processor"

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Saastamoinen, Piia, Ilkka Saastamoinen, and Jari Nurmi. "Code compression in DSP processor systems." International Journal of Embedded Systems 3, no. 4 (2008): 256. http://dx.doi.org/10.1504/ijes.2008.022396.

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Lapsley, P., and G. Blalock. "How to estimate DSP processor performance." IEEE Spectrum 33, no. 7 (July 1996): 74–78. http://dx.doi.org/10.1109/6.526871.

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de Dinechin, Benoit Dupont, Christophe Monat, Patrick Blouet, and Christian Bertin. "DSP-MCU processor optimization for portable applications." Microelectronic Engineering 54, no. 1-2 (December 2000): 123–32. http://dx.doi.org/10.1016/s0167-9317(00)80064-7.

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Mochida, Yukou, and Toshitaka Tsuda. "Special edition Digital signal processor. DSP applications." Journal of the Institute of Television Engineers of Japan 41, no. 3 (1987): 234–41. http://dx.doi.org/10.3169/itej1978.41.234.

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Yu, Xiao Bo, Yun Feng Zhang, and Yao Gang Fu. "Research on Applied Technology in Digital Signal Processor (DSP)." Advanced Materials Research 978 (June 2014): 193–96. http://dx.doi.org/10.4028/www.scientific.net/amr.978.193.

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Based on the advance of computer and modern electronic technology, technology of digital signal processor (DSP) and DSP chips have mutual promotion. And the functions of DSP chips have been improved greatly and the fields in which they are applied have also been increasingly expanded. Nowadays, they can be applied in all aspects of modern people’s life and work such as computer enclosure, communication and industrial control.
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Lian, Jin Hua. "A New Microprocessor Protection Scheme Based on Digital Signal Processor." Applied Mechanics and Materials 397-400 (September 2013): 1854–57. http://dx.doi.org/10.4028/www.scientific.net/amm.397-400.1854.

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Based on the demand of power department, a protection & monitoring device for the power distribution line is studied. The device using DSP as the core technology is a new industrial control unit, which adopts the of dual CPU of DSP+DSP and consists of chip selection unit, A/D conversion, data storage, watchdog circuit, press key, switch quantity detection, control output, communication, display and clock etc. The software system includes two parts: tracking software and protection software. The device ensures the high reliability and feasibility, at same time incarnates the advantage of microprocessor protection by intelligent designs.
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Glinski, S., and D. Roe. "Spoken language recognition on a DSP array processor." IEEE Transactions on Parallel and Distributed Systems 5, no. 7 (July 1994): 697–703. http://dx.doi.org/10.1109/71.296316.

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Fan, Jia Liang, and Qiang Yang. "A New Radar Signal Processing Architecture Based on Multi-Core Processor." Applied Mechanics and Materials 556-562 (May 2014): 1618–21. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1618.

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Most radar systems based on the structure that contains many DSP chips. The system structure is always complex, and it is difficult to update. Nowadays, multi-core processor develops very fast. Compared with DSP chips, multi-core processor has better performance in signal processing field. In this paper, we present a signal processing architecture which based on multi-core processor. Pulse compression algorithms and PCI-E bus are discussed as two important technologies. Adaptive beamforming test results show that multi-core processor is able to achieve radar signal processing.
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Bormann, Frank. "Teaching DSP in Digital Control." International Journal of Electrical Engineering & Education 49, no. 3 (July 2012): 291–301. http://dx.doi.org/10.7227/ijeee.49.3.8.

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The paper describes an approach to introduce digital signal processors (DSPs) in teaching digital control for undergraduates in electrical engineering. The article focuses first on the increasing demand for computational power from new mathematical approaches to digital control techniques, such as digital power supply, digital motor control, photovoltaic inverters, inverters for solar arrays and LED illuminating. The challenge for educators is to provide both a basic understanding of hardware and software modules on processor technology and a reasonable mathematical background to the underlying theory. Over the last decade the author has developed a set of teaching modules based on the C2000 family of digital signal controllers. As an example of students' work, the paper also describes a project based on an autonomous driving car.
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Park, Sung-Wook. "A Design of Superscalar Digital Signal Processor." Journal of Korean Institute of Intelligent Systems 18, no. 3 (June 25, 2008): 323–28. http://dx.doi.org/10.5391/jkiis.2008.18.3.323.

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Dissertations / Theses on the topic "DSP processor"

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Lennartsson, Per, and Lars Nordlander. "Benchmarking a DSP processor." Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1491.

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This Master thesis describes the benchmarking of a DSP processor. Benchmarking means measuring the performance in some way. In this report, we have focused on the number of instruction cycles needed to execute certain algorithms. The algorithms we have used in the benchmark are all very common in signal processing today.

The results we have reached in this thesis have been compared to benchmarks for other processors, performed by Berkeley Design Technology, Inc.

The algorithms were programmed in assembly code and then executed on the instruction set simulator. After that, we proposed changes to the instruction set, with the aim to reduce the execution time for the algorithms.

The results from the benchmark show that our processor is at the same level as the ones tested by BDTI. Probably would a more experienced programmer be able to reduce the cycle count even more, especially for some of the more complex benchmarks.

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Struhelka, Michal. "DSP audio procesor pro laboratorní výuku." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221230.

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This project deals with the subject of laboratory preparation for low-frequency and audio electronics. It is used DSP audio processor with integrated ADCs and DACs converters ADAU1701 from Analog Devices. Also, Atmel microcontroller with a connected graphic LCD display and buttons is used for adjusting DSP. The work presents the complete instructions of the laboratory project with a model protocol.
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Gnatyuk, Vladimir, and Christian Runesson. "A Multimedia DSP Processor Design." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2269.

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This Master Thesis presents the design of the core of a fixed point general purpose multimedia DSP processor (MDSP) and its instruction set. This processor employs parallel processing techniques and specialized addressing models to speed up the processing of multimedia applications.

The MDSP has a dual MAC structure with one enhanced MAC that provides a SIMD, Single Instruction Multiple Data, unit consisting of four parallel data paths that are optimized for accelerating multimedia applications. The SIMD unit performs four multimedia- oriented 16- bit operations every clock cycle. This accelerates computationally intensive procedures such as video and audio decoding. The MDSP uses a memory bank of four memories to provide multiple accesses of source data each clock cycle.

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Tell, Eric. "A Domain Specific DSP Processor." Thesis, Linköping University, Department of Electrical Engineering, 2001. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-980.

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This thesis describes the design of a domain specific DSP processor. The thesis is divided into two parts. The first part gives some theoretical background, describes the different steps of the design process (both for DSP processors in general and for this project) and motivates the design decisions made for this processor.

The second part is a nearly complete design specification.

The intended use of the processor is as a platform for hardware acceleration units. Support for this has however not yet been implemented.

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Peng, Sean Hsien-en. "UTDSP, a VLIW programmable DSP processor." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0017/MQ49751.pdf.

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Murugesan, Somasekar. "Benchmarking of Sleipnir DSP Processor, ePUMA Platform." Thesis, Linköpings universitet, Datorteknik, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-74080.

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Choosing a right processor for an embedded application, or designing a new pro-cessor requires us to know how it stacks up against the competition, or sellinga processor requires a credible communication about its performance to the cus-tomers, which means benchmarking of a processor is very important. They arerecognized world wide by processor vendors and customers alike as the fact-basedway to evaluate and communicate embedded processor performance. In this the-sis, the benchmarking of ePUMA multiprocessor developed by the Division ofComputer Engineering, ISY, Linköping University, Sweden will be described indetails. A number of typical digital signal processing algorithms are chosen asbenchmarks. These benchmarks have been implemented in assembly code withtheir performance measured in terms of clock cycles and root mean square errorwhen compared with result computed using double precision. The ePUMA multi-processor platform which comprises of the Sleipnir DSP processor and Senior DSPprocessor was used to implement the DSP algorithms. Matlab inbuilt models wereused as reference to compare with the assembly implementation to derive the rootmean square error values of different algorithms. The execution time for differentDSP algorithms ranged from 51 to 6148 clock cycles and the root mean squareerror values varies between 0.0003 to 0.11.
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Wang, P. "Softcore stream processor for FPGA-based DSP." Thesis, Queen's University Belfast, 2014. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.677848.

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Modern DSP applications present increasingly high computational requirements and keep evolving in nature. Field Programmable Gate Arrays (FPGAs) host a vast array of logic; hardwired DSP slices and memory resources combined with reconfigurability, emerging as a promising platform for DSP implementations. However, the current manner of programming FPGA still relies on design of dedicated circuits which is time consuming and complex. This has prompted the emergence of 'soft' processor architectures, hosted on the FPGAs reconfigurable fabric. However, existing softcore processors are still constrained in terms of performance, resource efficiency and applicability. In this thesis, these issues are addressed by a proposed Softcore Stream Processor (SSP). The SSP is used to achieve the first recorded software defined IEEE 802.11 ac FFT architecture with real-time processing ability for 8 channels and all required bandwidths. More importantly, it demonstrates not only it can offer a flexible, real-time processing, it also achieves reductions in resource cost of, on average, 65%, compared to dedicated circuit designs. Sliding window applications as an important subdomain of DSP applications are also targeted in this thesis. The implementations achieve over an order of magnitude higher resource efficiency when compared to current best metrics achieved by soft vector processors. In addition to the novel softcore architecture, a model-level SSP platform synthesis flow is presented to allow generation of high-quality real-time DSP on SSP in a systematic and automated way.
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Antelius, Henrik. "Retargeting a C Compiler for a DSP Processor." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2567.

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The purpose of this thesis is to retarget a C compiler for a DSP processor.

Developing a new compiler from scratch is a major task. Instead, modifying an existing compiler so that it generates code for another target is a common way to develop compilers for new processors.

This is called retargeting. This thesis describes how this was done with the LCC C compiler for the Motorola DSP56002 processor.

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Soni, Maneesh. "VLSI Implementation of a Wormhole Runtime Reconfigurable Processor." Thesis, Virginia Tech, 2001. http://hdl.handle.net/10919/35387.

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Until now, the performance improvement of computing machines was a mostly a result of shrinking transistor geometries and increasing clock speeds. With the advent of signal processing applications that have stringent performance requirements from processing hardware, the field of configurable computing has received a lot of attention. Efforts are being made to improve computation bandwidth by architectural innovations. Among these, the wormhole runtime reconfigurable architecture introduces the concept of stream processing. It enables dynamic reconfiguration of hardware with little overheads and is very much suited for data-path based computations with deep computational pipelines. Stallion, second in the generation of Wormhole runtime reconfigurable processors, demonstrates the efficacy of wormhole runtime reconfiguration. The work presented here deals with the VLSI implementation of Stallion and discusses the full-custom physical design flow adopted for Stallion. Also, the tools and techniques to customize this flow are detailed. The Stallion design methodology offers a possible solution that can be pursued for executing similar efforts in future.
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Andersson, Mikael, and Per Karlström. "Parallel JPEG Processing with a Hardware Accelerated DSP Processor." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2615.

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This thesis describes the design of fast JPEG processing accelerators for a DSP processor.

Certain computation tasks are moved from the DSP processor to hardware accelerators. The accelerators are slave co processing machines and are controlled via a new instruction set. The clock cycle and power consumption is reduced by utilizing the custom built hardware. The hardware can perform the tasks in fewer clock cycles and several tasks can run in parallel. This will reduce the total number of clock cycles needed.

First a decoder and an encoder were implemented in DSP assembler. The cycle consumption of the parts was measured and from this the hardware/software partitioning was done. Behavioral models of the accelerators were then written in C++ and the assembly code was modified to work with the new hardware. Finally, the accelerators were implemented using Verilog.

Extension of the accelerator instructions was given following a custom design flow.

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Books on the topic "DSP processor"

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Goudaropoulos, Ilias. DSP address processor. Manchester: University of Manchester, Department of Computer Science, 1997.

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Peng, Sean Hsien-en. UTDSP: A VLIW programmable DSP processor. Ottawa: National Library of Canada, 2000.

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Embedded DSP processor design: Application specific instruction set processors. Amsterdam: Morgan Kaufmann, 2008.

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Wilmot, Sinbad. An efficient processor core for DSP filtering applications. Dublin: University College Dublin, 1995.

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Lin, Wen-Yen. An optimizing compiler for the TMS320C25 DSP processor. Ottawa: National Library of Canada, 1994.

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Marković, Dejan. DSP Architecture Design Essentials. Boston, MA: Springer US, 2012.

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Tokhi, M. O. CISC, RISC and DSP processors in real-time signal processing and control. Sheffield: University of Sheffield, Dept. of Automatic Control and Systems Engineering, 1995.

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Mujica, Isabel Rojas. Comparison of three SPN packages: Great SPN 1.6, DSP Nexpress 1.2, SPN 3.0. Edinburgh: Computer Systems Group, University of Edinburgh, 1994.

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Environment, Great Britain Department of the. Secretary of State's guidance - hot dip galvanising processes. London: H.M.S.O., 1991.

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Hot-dip galvanizing: Guide to process selection and galvanizing practice. London: Intermediate Technology Publications, 1994.

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Book chapters on the topic "DSP processor"

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Glossner, C. John, Michael Schulte, and Stamatis Vassiliadis. "A Java-Enabled DSP." In Embedded Processor Design Challenges, 307–25. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45874-3_18.

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Frantz, Gene. "The DSP and Its Impact on Technology." In Processor Design, 101–19. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5530-0_6.

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Panis, Christian. "VLIW DSP Processor for High-End Mobile Communication Applications." In Processor Design, 121–48. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5530-0_7.

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Mehendale, Manesh, and Sunil D. Sherlekar. "Implementation of Multiplication-Free Linear Transforms on a Programmable Processor." In VLSI Synthesis of DSP Kernels, 141–69. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3355-6_6.

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Patricia, Guitton-Ouhamou, Belleudy Cécile, and Auguin Michel. "Power Consumption Model for the DSP OAK Processor." In IFIP Advances in Information and Communication Technology, 217–28. Boston, MA: Springer US, 2002. http://dx.doi.org/10.1007/978-0-387-35597-9_19.

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Paakkulainen, Jani, Seppo Virtanen, and Jouni Isoaho. "Tuning a Protocol Processor Architecture Towards DSP Operations." In Lecture Notes in Computer Science, 132–41. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11512622_15.

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Guo, Zicheng, and Rami G. Melhem. "Perfect Shuffle Communications In Optically Interconnected Processor Arrays." In Parallel Algorithms and Architectures for DSP Applications, 33–47. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3996-4_2.

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Gebotys, C. H., and R. Muresan. "Modeling Power Dynamics for an Embedded DSP Processor Core." In IFIP Advances in Information and Communication Technology, 205–16. Boston, MA: Springer US, 2002. http://dx.doi.org/10.1007/978-0-387-35597-9_18.

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Kim, Hyun-Gyu, and Hyeong-Cheol Oh. "A Low-Power DSP-Enhanced 32-Bit EISC Processor." In High Performance Embedded Architectures and Compilers, 302–16. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11587514_20.

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D’Alberto, Paolo, Markus Püschel, and Franz Franchetti. "Performance/Energy Optimization of DSP Transforms on the XScale Processor." In High Performance Embedded Architectures and Compilers, 201–14. Berlin, Heidelberg: Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-69338-3_14.

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Conference papers on the topic "DSP processor"

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Milovanovic, I. Z., M. K. Stojcev, E. I. Milovanovic, and T. R. Nikolic. "Linear processor array in DSP." In 2012 28th International Conference on Microelectronics (MIEL 2012). IEEE, 2012. http://dx.doi.org/10.1109/miel.2012.6222883.

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Gao, Jian, Jie Chen, Li Zhou, Yang Liu, Xu Ma, Xuan Huang, Zhenpeng Wang, and Lu Li. "Design of a Media Processor based on DSP Processor." In 2006 International Conference on Communication Technology. IEEE, 2006. http://dx.doi.org/10.1109/icct.2006.341942.

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Shi, Ce, Wei-Dong Wang, Li Zhou, Lei Gao, Peng Liu, and Qingdong Yao. "32b RISC/DSP media processor: MediaDSP3201." In Electronic Imaging 2005, edited by Subramania Sudharsanan, V. Michael Bove, Jr., and Sethuraman Panchanathan. SPIE, 2005. http://dx.doi.org/10.1117/12.586072.

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Mody, Mihir, Hemant Hariyani, Anand Balagopalakrishnan, Jason Jones, Ajay Jayaraj, and Y. A. Prithvishankar. "GPU Assist using DSP Pre-processor." In 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT). IEEE, 2020. http://dx.doi.org/10.1109/conecct50063.2020.9198650.

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Vashi, Harshal B., G. T. Haldankar, and Y. S. Rao. "Real time circuit simulation using DSP processor." In 2014 International Conference for Convergence of Technology (I2CT). IEEE, 2014. http://dx.doi.org/10.1109/i2ct.2014.7092263.

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Karlsson, Andreas, Joar Sohl, and Dake Liu. "ePUMA: A processor architecture for future DSP." In 2015 IEEE International Conference on Digital Signal Processing (DSP). IEEE, 2015. http://dx.doi.org/10.1109/icdsp.2015.7251870.

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Jage, Chaitanya S., Mukesh D. Patil, and Vishwesh A. Vyawahare. "Implementation of fractional derivative using DSP processor." In 2015 International Conference on Information Processing (ICIP). IEEE, 2015. http://dx.doi.org/10.1109/infop.2015.7489494.

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Hobson, Rick F., Peter S. Wong, and S. A. Evenson. "Embedded-processor architecture for parallel DSP algorithms." In SPIE's 1996 International Symposium on Optical Science, Engineering, and Instrumentation, edited by Franklin T. Luk. SPIE, 1996. http://dx.doi.org/10.1117/12.255463.

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Xiong, Y., Y. Huang, M. Evans, and T. Cronk. "A SDR for realtime DAB COFDM demodulation with ARM processor." In IEE Colloquium on DSP enabled Radio. IET, 2003. http://dx.doi.org/10.1049/ic.2003.0313.

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Ismail, Muhammad Ali. "Multi-core processor based parallel implementation for finding distribution vectors in Markov processes." In 2013 18th International Conference on Digital Signal Processing (DSP). IEEE, 2013. http://dx.doi.org/10.1109/siecpc.2013.6550997.

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Reports on the topic "DSP processor"

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Moran, T. M. Design of an Expandable Digital Signal Processor (DSP) Based on the TMS320C25. Fort Belvoir, VA: Defense Technical Information Center, August 1989. http://dx.doi.org/10.21236/ada211343.

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Reddell, Noah F. Development of a Digital Signal Processor (DSP) Based Chaotic Communication System With Emphasis on Military Applications. Fort Belvoir, VA: Defense Technical Information Center, May 2002. http://dx.doi.org/10.21236/ada403362.

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Affo, Abdel. Aperture and Receiver Technology. Delivery Order 0002: Bandwidth Invariant Spatial Processing. Volume 2. Digital Signal Processor (DSP) Based Implementation of Direction of Arrival (DOA) for Wideband Sources. Fort Belvoir, VA: Defense Technical Information Center, May 2007. http://dx.doi.org/10.21236/ada470116.

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Parhi, Keshab K. Design Tools and Architectures for Dedicated Digital Signal Processing (DSP) Processors. Fort Belvoir, VA: Defense Technical Information Center, July 1996. http://dx.doi.org/10.21236/ada397589.

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J.T. Birkholzer and S. Mukhopadhyay. DRIFT-SCALE COUPLED PROCESSES (DST AND TH SEEPAGE) MODELS. Office of Scientific and Technical Information (OSTI), January 2005. http://dx.doi.org/10.2172/883411.

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E. Sonnenthale. Drift-Scale Coupled Processes (DST and THC Seepage) Models. Office of Scientific and Technical Information (OSTI), April 2001. http://dx.doi.org/10.2172/837042.

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E. Gonnenthal and N. Spyoher. Drift-Scale Coupled Processes (DST and THC Seepage) Models. Office of Scientific and Technical Information (OSTI), February 2001. http://dx.doi.org/10.2172/837097.

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P. Dixon. Drift-Scale Coupled Processes (DST and THC Seepage) Models. Office of Scientific and Technical Information (OSTI), April 2004. http://dx.doi.org/10.2172/837496.

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J. Birkholzer and S. Mukhopadhyay. Drift-Scale Coupled Processes (DST and TH Seepage) Models. Office of Scientific and Technical Information (OSTI), September 2004. http://dx.doi.org/10.2172/837686.

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RASMUSSEN, J. H. Double Shell Tank (DST) Process Waste Sampling Subsystem Specification. Office of Scientific and Technical Information (OSTI), May 2000. http://dx.doi.org/10.2172/803637.

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