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Dissertations / Theses on the topic 'DSP processor design'

Author: Grafiati

Published: 4 June 2021

Last updated: 18 February 2022

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1

Gnatyuk, Vladimir, and Christian Runesson. "A Multimedia DSP Processor Design." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2269.

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<p>This Master Thesis presents the design of the core of a fixed point general purpose multimedia DSP processor (MDSP) and its instruction set. This processor employs parallel processing techniques and specialized addressing models to speed up the processing of multimedia applications. </p><p>The MDSP has a dual MAC structure with one enhanced MAC that provides a SIMD, Single Instruction Multiple Data, unit consisting of four parallel data paths that are optimized for accelerating multimedia applications. The SIMD unit performs four multimedia- oriented 16- bit operations every clock cycle. Th

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2

Tell, Eric. "A Domain Specific DSP Processor." Thesis, Linköping University, Department of Electrical Engineering, 2001. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-980.

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<p>This thesis describes the design of a domain specific DSP processor. The thesis is divided into two parts. The first part gives some theoretical background, describes the different steps of the design process (both for DSP processors in general and for this project) and motivates the design decisions made for this processor. </p><p>The second part is a nearly complete design specification. </p><p>The intended use of the processor is as a platform for hardware acceleration units. Support for this has however not yet been implemented.</p>

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Ravinath, Vinodh. "Design and Implementation of Single Issue DSP Processor Core." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10160.

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<p>Micro processors built specifically for digital signal processing are DSP processors. DSP is one of the core technologies in rapidly growing applications like communications and audio processing. The estimated growth of DSP processors in the last 6 years is over 40%. The variety of DSP capable processors for various applications also increased with the rising popularity of DSP processors. The design flow and architecture of such processors are not commonly available to students for learning.</p><p>This report is a structured approach to design and implementation of an embedded DSP processor

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4

Wang, Jian. "Low Overhead Memory Subsystem Design for a Multicore Parallel DSP Processor." Doctoral thesis, Linköpings universitet, Datorteknik, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-105866.

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The physical scaling following Moore’s law is saturated while the requirement on computing keeps growing. The gain from improving silicon technology is only the shrinking of the silicon area, and the speed-power scaling has almost stopped in the last two years. It calls for new parallel computing architectures and new parallel programming methods. Traditional ASIC (Application Specific Integrated Circuits) hardware has been used for acceleration of Digital Signal Processing (DSP) subsystems on SoC (System-on-Chip). Embedded systems become more complicated, and more functions, more applications

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5

Hägglund, Erik. "Design of a DVB-T Receiver : For SFN on a DSP-Processor." Thesis, Linköpings universitet, Datorteknik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-86070.

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The goal of this thesis was to implement a DVB-T receiver on Coresonic’s DSP-processor and attempt to evaluate how to design a receiver that is robust against very strong echoes with a long delay. Long delayed echoes is very common in Single Frequency Networks (SFN) which is why focus was put on finding algorithms that work well in SFN.The thesis involved analyzing different algorithms involved in making a DVB-T receiver where the focus was to find a good channel estimation algorithm. The thesis also included programming the DSP-processor and making some smaller modifications to their hardware

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6

Nilsson, Anders. "Design of programmable multi-standard baseband processors." Doctoral thesis, Linköping : Department of Electrical Engineering, Linköping University, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8908.

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7

Packiaraj, Vivek. "Study, Design and Implementation of an Application Specific Instruction Set Processor for a Specific DSP Task." Thesis, Linköping University, Electronics System, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-52314.

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<p>There is a lot of literature already available describing well-structured approach for embeddeddesign and implementation of Application Specific Integrated Processor (ASIP) micro processorcore.</p><p>This concept features hardware structured approach for implementation of processor core fromminimal instruction set, encoding standards, hardware mapping, and micro architecture design,coding conventions, RTL,verification and burning into a FPGA. The goal is to design an ASIPprocessor core (Micro architecture design and RTL) which can perform DSP task, e.g., FIR. Thereport is a well structured

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8

Broich, René. "A Soft-core processor architecture optimised for radar signal processing applications." Diss., University of Pretoria, 2013. http://hdl.handle.net/2263/40821.

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Current radar signal processor architectures lack either performance or flexibility in terms of ease of modification and large design time overheads. Combinations of processors and FPGAs are typically hard-wired together into a precisely timed and pipelined solution to achieve a desired level of functionality and performance. Such a fixed processing solution is clearly not feasible for new algorithm evaluation or quick changes during field tests. A more flexible solution based on a high-performance soft-core processing architecture is proposed. To develop such a processing architecture,

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9

Jiang, Guoyou. "Design and Implementation of a DMA Controller for Digital Signal Processor." Thesis, Linköping University, Computer Engineering, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-58868.

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<p>The thesis work is conducted in the division of computer engineering at thedepartment of electrical engineering in Linköping University. During the thesiswork, a configurable Direct Memory Access (DMA) controller was designed andimplemented. The DMA controller runs at 200MHz under 65nm digital CMOS technology. The estimated gate count is 26595.</p><p>The DMA controller has two address generators and can provide two clocksources. It can thus handle data read and write simultaneously. There are 16channels built in the DMA controller, the data width can be 16-bit, 32-bit and64-bit. The DMA con

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10

Mokrzycki, Brian Thomas. "WvFEv3: An FPGA-based general purpose digital signal processor for space applications." Thesis, University of Iowa, 2011. https://ir.uiowa.edu/etd/3355.

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The Waves instruments aboard the Juno and Radiation Belt Storm Probe (RBSP) spacecraft represents the next generation of space radio and plasma wave instrumentation developed by the University of Iowa's Radio and Plasma Wave group. The previous generation of such instruments on the Cassini spacecraft utilized several analog signal-conditioning techniques to compress and condense scientific data. Compression techniques are necessary because the plasma wave instruments can often generate significantly more science data than can be transmitted using the narrow telemetry channel of the hosting spa

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11

Tell, Eric. "Design of Programmable Baseband Processors." Doctoral thesis, Linköping : Univ, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-4377.

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12

Zhou, Yuan. "Novel very fast FFT processors : on DSP algorithm design and FPGA-based implementation." Thesis, University of Bradford, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.508609.

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13

Nilsson, Per. "Hardware / Software co-design for JPEG2000." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5796.

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<p>For demanding applications, for example image or video processing, there may be computations that aren’t very suitable for digital signal processors. While a DSP processor is appropriate for some tasks, the instruction set could be extended in order to achieve higher performance for the tasks that such a processor normally isn’t actually design for. The platform used in this project is flexible in the sense that new hardware can be designed to speed up certain computations.</p><p>This thesis analyzes the computational complex parts of JPEG2000. In order to achieve sufficient performance for

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14

Nobre, Filho Wilson. "Contribuição do design thinking para o processo de inovação de produtos." reponame:Repositório Institucional do FGV, 2013. http://hdl.handle.net/10438/10990.

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Submitted by Wilson Nobre Filho (wilson.nobre@fgv.br) on 2013-07-16T21:54:48Z No. of bitstreams: 1 Dissertacao de Mestrado – Wilson Nobre 2013.pdf: 2816404 bytes, checksum: bd330cdfccbdec4ced5db374509a28bc (MD5)<br>Approved for entry into archive by Suzinei Teles Garcia Garcia (suzinei.garcia@fgv.br) on 2013-07-17T12:24:17Z (GMT) No. of bitstreams: 1 Dissertacao de Mestrado – Wilson Nobre 2013.pdf: 2816404 bytes, checksum: bd330cdfccbdec4ced5db374509a28bc (MD5)<br>Made available in DSpace on 2013-07-17T13:33:14Z (GMT). No. of bitstreams: 1 Dissertacao de Mestrado – Wilson Nobre 2013.pdf: 2

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Hadikusumo, Bonaventura H. W. "Virtually real construction sfite processes : hazard identification and accident precaution planning using design-for-safety-process (DFSP) tool /." Thesis, Hong Kong : University of Hong Kong, 2001. http://sunzi.lib.hku.hk/hkuto/record.jsp?B24872829.

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16

Lippi, Sara. "Prima del progetto. Definizione del DPP dell'intervento di rifunzionalizzazione dell'ex Deposito ATR a Forli." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2018.

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La presente tesi costituisce una simulazione del ruolo professionale del Responsabile Unico del Procedimento, figura che, ai sensi dell'art. 31 del D.Lgs. 50/2016, prende parte alle fasi di programmazione, progettazione, affidamento ed esecuzione di progetti per conto della Pubblica Amministrazione. Questa figura svolge i compiti propri del manager che conosce e gestisce le questioni di carattere decisionale, scientifico, urbanistico, tecnico e progettuale. Nell'ottica di un concorso di progettazione, lo scopo della tesi consiste nella redazione del Documento Preliminare alla Progettazione

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Simi, Eleonora. "Prima del progetto. Definizione del DPP dell'intervento di rifunzionalizzazione dell'ex Merlettificio Türck a Pinerolo (TO)." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2018.

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La presente tesi costituisce una simulazione del ruolo professionale del Responsabile Unico del Procedimento (RUP), figura che, ai sensi dell'art. 31 del D.Lgs. 50/2016, prende parte alle fasi di programmazione, progettazione, affidamento ed esecuzione di progetti per conto della Pubblica Amministrazione. Questa figura svolge i compiti propri del manager che conosce e gestisce le questioni di carattere decisionale, scientifico, urbanistico, tecnico e progettuale. Nell'ottica di un concorso di progettazione, lo scopo della tesi consiste nella redazione del Documento Preliminare alla Progett

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18

簡文昱. "A Design of High Performance DSP Processor." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/08446299716090418171.

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碩士<br>中華大學<br>電機工程研究所<br>86<br>This paper presents a 32-bit reduced instruction set computer (RISC) with digital signal processing (DSP) architecture. The processor can perform a general purpose microprocessor and particular application in DSP. Because of DSP technique has been used widely in many applications, such as video, image, com-munication... and so on, using this chip can easily execute programs in DSP applications. 　　The Design is described in verilog, a hardware description language, the function-level verification is done in RTL-level, and the design is then synthesized via "synops

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19

HUANG, SHENG-JIE, and 黃聖傑. "Logarithmic number system processor design for DSP applications." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/21569535239743077225.

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20

Yang, Chi-Hung, and 楊啟鴻. "The Design of Address Sequence Generator in DSP processor." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/68780787454777112815.

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碩士<br>元智大學<br>資訊工程學系<br>89<br>According to the continuous progress in DSP algorithm and hardware design tools, we can rapidly design a new architecture for our ideal. The most important character of DSP processor is the realization of a real time system. There are many good ways have done in this field. The most common way to meet this requirement is to shorten the instruction execution time. In our paper, we provide another way; efficiently control the data stream between the host processor and the memory, to solve this problem. So we propose an advanced architecture of AGU (Addre

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21

Kuo-Wei, Peng, and 彭國維. "The Design of the DSP-X Programmable Speech Processor." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/74346592298096583949.

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碩士<br>國立臺灣大學<br>資訊工程研究所<br>81<br>This thesis discusses the design of a programmable speech proces- sor called DSP-X. The work includes instruction set and hardware architecture design. The DSP-X is developed to support speech compression and decompression applications. The design of the DSP-X is described in the Verilog hardware description language (HDL). All Verilog descriptions are detailed to the register transfer level(RTL), and descriptions are simulated by Verilog simulator in order

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22

Lin, Wen-Hsiang, and 林文翔. "Design of Data Access Agent for VLIW DSP Processor." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/37513777645991220166.

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碩士<br>國立交通大學<br>資訊工程系<br>91<br>In resent years, VLIW architecture is widely introduced by DSP processors for high performance computing. However, energy consumption has also become an important consideration on account of the currency of portable and wireless applications. Owing to the improvement of semiconductor technology, more and more CMOS memories will be disposed to SoC designs. Thus, the energy consumed by memory will dominate energy consumption of the future SoC designs. The objective of this thesis is to reduce the energy consumption of memory by lessening the volume of pr

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23

孔憲華. "VLSI design of 24-bit seven-stage pipeline DSP processor." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/22216390349344365413.

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Hong, Ming-Yen, and 洪銘彥. "Vector Register Architecture Design and Simulation on Embedded DSP Processor." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/67564599866418809962.

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碩士<br>國立清華大學<br>電機工程學系<br>96<br>在多媒體處理的領域中，由於資料的特性，單一指令操作於多重資料( Single Instruction Multiple Data, SIMD )的運算處理技術是有效及廣泛被使用的。通常，對於一台32-bit的機器來說，假如一個運算資料單位是8-bit的話，一條SIMD的指令可以同時操作於4個資料單位，因此也能將運算的平行度提升到4。這些運算資料單元在SIMD運算處理技術中，時常被稱之為子字符( subword )。然而，SIMD運算的效能常常受限於這些subwords在暫存器( register )之間的排列狀況。因此，為了解決subwords的排列問題，我們提出了一種新的暫存器架構，稱之為向量暫存器架構( Vector Register Architecture )。藉由向量暫存器架構，我們可以更自由地在暫存器間，排列、重組這些subwords，而不需要在暫存器跟記憶體之間，製造大量的資料流量。為了模擬與驗證向量暫存器的效能，我們基於新一代的影像壓縮技術─H.264/AVC，設計了三組標準測試程式( benchmark )，這些程式分別是矩陣轉置( matrix transposition)，去方塊效應濾波器( deblocking filter)，離散餘弦轉換 ( discrete cosine transform

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dolph and 林榮壕. "A Design and Test of Pipeline DSP Processor with Special Application in H.263 Codec Processor." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/14096330985781279645.

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碩士<br>中華大學<br>電機工程學系碩士班<br>89<br>In this design of DSP, the instruction set and addressing modes are defined in RISC approach, and except the regular DSP instructions, we add a couple of multimedia instructions in our DSP design, such as DCT、Motion Estimation and Butterfly instructions. The instruction length is 20-bit and data is 8-bit long. The instruction cycle is then proposed and the five-stage pipeline architecture is developed. The problems of data dependency、resource conflict、conditional branch and interrupt in the design of pipeline architecture are addressed. An interrupt controller

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26

Lee, Duehee. "Design and implementation of three-phase inverters using a TMS320F2812 digital signal processor." Thesis, 2009. http://hdl.handle.net/2152/ETD-UT-2009-12-498.

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The goal of this thesis project was to design and build a three-phase inverter controlled by the TMS320F2812 DSP by Texas Instruments. The TMS320F2812 is controlled in order to make inverters generate output waveforms which mimic the main reference signal coming from a computer. The project included building three different inverters on two platforms including auxiliary circuits and designing five pulse width modulation (PWM) switching algorithms for the inverters. The motivation was that a newly designed inverter was required as an intermediary device between a computer and a laboratory-scale

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27

Chiang, Chia-Chun, and 江佳峻. "A Floating Point Addition Unit for DSP Processor Using Asynchronous Circuit Design." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/68376586968432449743.

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28

Chang, Ming-Chin, and 張明欽. "Design of a Simulation and Testing System for ADI-2184 DSP Processor." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/89668090473277506137.

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碩士<br>國立臺灣科技大學<br>資訊工程研究所<br>89<br>This thesis is related to the design and implementation of a simulation and testing system for ADSP-2184 DSP processor. First of all, a behavioral model for simulating ADSP-2184 is designed. Then, by integrating this model with other related behavioral models, a simulation and testing system has been well developed. This simulation and testing system consists of three parts. The first part is about the design of a behavioral simulation model for ADSP-2184 processor. The second part is to integrate a simulation and testing system for ADSP-2184 proce

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29

Hsu, Han-Jen, and 許瀚仁. "Design and Implementation of Dual-mode DCT IP Core and Reconfigurable DSP Processor." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/69479246943881421764.

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碩士<br>國立中興大學<br>電機工程學系<br>91<br>In this thesis, we propose a cost-effective 2-D Discrete Cosine Transform IP Core with reconfigurable datapath. The chip can process 8 × 8 block of video sequence. Even-odd decomposition is suitable for VLSI implementation. The architecture includes of two types of reconfigurable processor to process even and odd data. We use two mode operations of reconfigurable datapaths to achieve high speed and low power consumption. The precision of wordlength can meet the requirement of CCITT standard. A prototype c

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30

Hsiao, Pi-Chen, and 蕭丕承. "Efficient Datapath Design for Clustered & Pipelined VLIW DSP Processors." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/24419684455805579987.

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碩士<br>國立交通大學<br>電子工程系所<br>94<br>Most DSP applications feature a high degree of data-level and instruction-level parallelism, which enables efficient datapath design with clustering and deep pipelining. However, the ad-hoc data forwarding and inter-cluster communications in most processors significantly compensate the advantages. This thesis presents analytical formulae which are based on cell-based implementation with flip-flops and multiplexers to analyze the complexity of forwarding unit and inter-cluster communication mechanisms. We also propose a complexity-aware data forwarding architectu

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31

Huang, Chien-Chin, and 黃建今. "Microkernel Design and Dual-core Supports for PAC VLIW DSP Processors." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/10718300342293107975.

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碩士<br>國立清華大學<br>資訊工程學系<br>95<br>High-performance and low-power VLIW DSP processors are increasingly deployed in embedded mobile devices to process video and multimedia applications. Also, dual-core embedded processors which combine a MPU and a DSP are widely used in embedded systems to provide powerful computation. As there are diversified applications concurrently used for such systems, resource and communication management for dual-core embedded system become a focus of recent research efforts. To manage resource, we need operating systems for both processors. And there are many popular ope

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