Journal articles: 'DSP processor design'

1

Park, Sung-Wook. "A Design of Superscalar Digital Signal Processor." Journal of Korean Institute of Intelligent Systems 18, no. 3 (2008): 323–28. http://dx.doi.org/10.5391/jkiis.2008.18.3.323.

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Savadi, Anuradha, Raju Yanamshetti, and Jyoti Godihal. "Design and Synthesis of High Performance Vedic DSP Processor." International Journal of Computer Applications 168, no. 6 (2017): 27–32. http://dx.doi.org/10.5120/ijca2017914469.

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Kong, Su Ran. "FPGA + DSP-Based Real-Time Image Acquisition System Research and Design." Advanced Materials Research 433-440 (January 2012): 5482–88. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.5482.

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Image processing system to calculate the volume, real-time high and the requirements of small size, using the DSP-based processor, FPGA approach, supplemented by the processor design of a high-performance real-time image processing system, and the system In the process of image acquisition and transmission of noise, using the PCB's anti-jamming design. Practice shows that two chips using FPGA + DSP, the algorithm is divided into two parts by the FPGA and DSP processing; effectively improve the efficiency of the algorithm. System real-time high, adaptability, real-time image acquisition system can meet the design requirements.

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Wan, Xiong, Dong Gang Yao, Zhi Min Zhang, Hua Ming Zhang, and Wen Bo Xiao. "Design of Data Acquisition System Based on DSP and Optical Fiber Bundle." Advanced Materials Research 629 (December 2012): 725–29. http://dx.doi.org/10.4028/www.scientific.net/amr.629.725.

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This paper introduces the design of a DSP-based acquisition system with high parallelism of the beam. The system uses fiber arrays connected to spatial filters as the detection devices. A TMS320LF2407A DSP is adopted as the primary embedded processor, which connects Analog to Digital (A/D) converters via I/O ports. Simultaneously, the processor realizes the parallel processing of data storage, transmission and calculation. The design of the main processor control module, the signal processing module and its corresponding software, are discussed in detail.

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Sharma, P. K. "Design of a Communication System Using DSP Processor DSK C6713." Bioscience Biotechnology Research Communications 13, no. 15 (2020): 185–88. http://dx.doi.org/10.21786/bbrc/13.15/30.

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Deng, Shu Zhang. "Research on DSP Embedded Digital Signal Processing System for Ship Navigation Radar." Applied Mechanics and Materials 556-562 (May 2014): 4718–21. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.4718.

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Development of digital signal processing and embedded technologies today, to the development of radar technology has brought new opportunities. Relative to the simulation of radar, digital radar has good performance, features, ease of operation, and other benefits. Design based on embedded processor and digital signal processor (DSP) dual processor shipboard navigation radar system, and focuses on digital shipborne navigational radar system architecture, hardware design and software algorithms for digital signal processing module, gives the overall scheme for DSP systems.

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Wu, Xun, Yue Song Mei, Jian Qiao Yu, Tian Peng Yu, and Jing Xu Li. "A Design of UART Serial Communication between the TMS320C6748 DSP and PC." Applied Mechanics and Materials 380-384 (August 2013): 3657–60. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3657.

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The digital signal processor (DSP: Digital Signal Proceeding) are widely used in industrial, military, communications and the other fields, so the research and design work about DSP is one of the hot spots of scholars and research. Communication and data transfer between the DSP and peripherals is one of the DSP function in the process of using which is the basic but important. This paper introduces a TMS320C6748 DSP with PC serial communication method based on the UART module. The hardware connection and software programming were highlights description. Finally, this paper gives some key code about TMS320C6748 DSP and PC serial communication programming.

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Hu, Wen Bin. "The Design of Embedded Video Monitoring System Based on DSP Processor." Advanced Materials Research 989-994 (July 2014): 3003–6. http://dx.doi.org/10.4028/www.scientific.net/amr.989-994.3003.

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This paper designs a embedded video monitoring system based on ARM processor Ep9315 and TMS320DM642, and using embedded Linux operating system. In the system, video capturing module uses the video decoder TW2814. In order to capture better data, the control of TW2814 is needed. Through the imitation of I2C bus, the driver provide the application with the function of the setting of capturing parameters such as hue, color saturation, contrast and brightness, and the check of video losing.

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Priya, K. Hari, and Chinthakindi Roja Sree. "Design of 32 Bit Low Power RISC Processor for DSP Applications." International Journal of Engineering Trends and Technology 34, no. 1 (2016): 5–14. http://dx.doi.org/10.14445/22315381/ijett-v34p202.

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Wu, Qiang, Peng Zhao, Tong Yin, and Qing Shan Liu. "Design and Implementation of a Multi-DSP Processing System." Advanced Materials Research 718-720 (July 2013): 1361–64. http://dx.doi.org/10.4028/www.scientific.net/amr.718-720.1361.

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A multi-DSP real time image processing system is designed, with TI's TMS320C6455 as core processor as well as Xilinx Virtex5 FPGA for pre-processing and important data channel. The system has completed testing verification and results show that the design is feasible and reliable.

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Wei, Chi Pin, Zhao Lin Li, Hao Liu, and Zhi Xiang Chen. "Design of a Random Test Platform for DSP Serials Used in Embedded Systems." Advanced Materials Research 267 (June 2011): 98–103. http://dx.doi.org/10.4028/www.scientific.net/amr.267.98.

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Embedded systems with digital signal processor (DSP) become more and more popular for the increasing requirement of supercomputing these days. Efficient development of DSP serials used in embedded systems shortens the embedded system R&D cycle. Functional verification is one of the most complex and expensive tasks during DSP serials design process. A random test platform which is urged for DSP serials verification is proposed in this paper. The platform can automatically generate the random test program. The platform also realized the recording and checking of simulation results, which make the verification more effective. In order to improve the efficiency of DSP verification, a testing experience library has been generated through the testing procedure. This platform can be transplanted for different DSP models easily by updating few modules. According to the verification results, this platform has satisfactory coverage of DSP models.

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Cai, Lin. "The Design of Power Harmonic Analyzer Based on UC/OS-II." Advanced Materials Research 1055 (November 2014): 118–21. http://dx.doi.org/10.4028/www.scientific.net/amr.1055.118.

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In this paper, we discuss the applications of UC/OS-II and DSP(digital signal processor) in area of harmonic analyzing. In this research, the FFT algorithm is employed, and the realization of FFT on DSP is discussed. The whole system is based on UC/OS-II operation system, which coordinate all the tasks about the system. The system based on DSP+ARM and UC/OS-II improve the reliability and real time quality. The hardware design and software design are proposed in this paper, with flow chart and part of routine codes shown.

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Lin, Hai Yan, Hai Liu, and Yin Zhao Wang. "Design of Hardware Based on Control Circuit of APF." Applied Mechanics and Materials 148-149 (December 2011): 353–56. http://dx.doi.org/10.4028/www.scientific.net/amm.148-149.353.

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In this paper, we focus on the hardware design of control circuit based on shunt active power filter (APF). It described the AD transformation module, DSP data processing module, CPLD logic control module, man-machine interaction module and asynchronous communication module. As the core controller, TMS320C5416 digital signal processor (DSP) controls this peripheral assistant circuit to complete data acquisition, harmonic detection and output of control signal. Finally, we design the layout and routing of the control circuit.

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Hu, Ju Fang, Chun Ru Xiong, Hao Hu, and Run Yang Zhong. "Design of a DSP System Based on FPGA." Advanced Materials Research 317-319 (August 2011): 1559–62. http://dx.doi.org/10.4028/www.scientific.net/amr.317-319.1559.

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This paper proposes an innovative methodology to design a DSP (Digital Signal Processing) system using FPGA (Field-programmable Gate Array). There are several main components in this system, including A/D sampling unit, FFT processing unit and control unit. A/D sampling and FFT processing units utilize the Nios processor in FPGA as controller. Control unit uses EP1C20 FPGA chip from ALTERA as FFT processing unit so as to manage the FIFO operations. This unit can handle 128 FFT operations. This system design approach is tested on Matlab. The results indicate that the calculation speed is much faster than common DSP manner.

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Liu, Yong Tao, Hui Jun Wang, Jia Liu, and Wei Wei Xu. "Static Reactive Power Compensation of Generator Design Based on TMS320LF2407." Applied Mechanics and Materials 734 (February 2015): 692–96. http://dx.doi.org/10.4028/www.scientific.net/amm.734.692.

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In this paper, we study a kind of method which using DSP processor to control the reactive power compensation of generator. In the main circuit, power electronic switching devices on all control type (IGBT) is used as the main device of inverter, and controlled by SVPWM technology on and off to produce pulse. The generator to a digital signal processor as the core processor, the processor can quickly complete the data processing and real-time data sampled signal calculation tasks, the power system to achieve a fast response of the dynamic compensation, given the various modules of the system program flowchart.

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Shi, Xiao Juan. "The Design and Implementation of Motion Control Card Based on DSP." Advanced Materials Research 102-104 (March 2010): 427–31. http://dx.doi.org/10.4028/www.scientific.net/amr.102-104.427.

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A hardware implement scheme is proposed based on digital signal processor, and the complex programmable logic device and industry standard architecture bus is proposed. The dual-port random access memory communication circuit, I/O port address decoding circuit, two axis control output circuit and position detecting circuit are developed, the main program and interrupt-serving program of digital signal processor are designed by the idea of modularization. The static accuray of the motion control card is tested via special experimental device. The present analysis show that the designed circuit is effective and the static control precision of motion control card is satisfied.

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Wei, Zhen Qi, Pei Lin Liu, Ji Kong, and Ren Dong Ying. "Design of Arithmetic Operation Core in Embedded Processor for High Definition Audio Applications." Applied Mechanics and Materials 538 (April 2014): 289–92. http://dx.doi.org/10.4028/www.scientific.net/amm.538.289.

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To meet requirements of wider data width, higher throughput, and more flexibility, a specific arithmetic operation core (AOC) is designed for high definition audio application specific processors. The proposed core is capable of processing long bit-width operations, as well as short bit-width operations in parallel. A six-stage pipeline is applied in the architecture of AOC to support amounts of DSP operations, and a novel stage-skipping technique is used to improve the execution efficiency of instructions passing through the deep pipeline. Several DSP kernels and audio data decoding applications are used in performance evaluation of AOC. Experiment results show that the proposed operation core can achieve over 50% higher execution efficiency in audio applications than conventional high performance DSPs, providing an appealing solution for design of operation core for high definition audio applications.

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Zhang Wumei. "Design and Application of Intelligence Sensor System that based on DSP Processor." International Journal of Advancements in Computing Technology 5, no. 6 (2013): 276–82. http://dx.doi.org/10.4156/ijact.vol5.issue6.32.

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Wu, Chou-Pin, and Jen-Ming Wu. "Design of Vector Register Architecture in DSP Processor for Efficient Multimedia Processing." JSTS:Journal of Semiconductor Technology and Science 7, no. 4 (2007): 229–34. http://dx.doi.org/10.5573/jsts.2007.7.4.229.

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Sala, M., F. Salidu, F. Stefani, C. Kutschenreiter, and A. Baschirotto. "Design considerations and implementation of a DSP-based car-radio IF Processor." IEEE Journal of Solid-State Circuits 39, no. 7 (2004): 1110–18. http://dx.doi.org/10.1109/jssc.2004.829402.

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21

Biswas Dutta, Chaitali. "Design of a Reconfigurable DSP Processor with Bit Efficient Residue Number System." International Journal of VLSI Design & Communication Systems 3, no. 5 (2012): 175–89. http://dx.doi.org/10.5121/vlsic.2012.3515.

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Zhu, Xiang Dong, Tao Han, Wei Lu, Lei Xing, and Di Xue. "Design of Portable Gas Detector Based on DSP." Advanced Materials Research 430-432 (January 2012): 1667–70. http://dx.doi.org/10.4028/www.scientific.net/amr.430-432.1667.

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A new design method of gas detection system was given based on the new DSP processor TMS320F28335. The experiment system takes six metal-oxide semiconducter gas sensors as well as temperature and humidity sensors in comprising the sensor array module, followed the excellent detection principle how to choose, and choose CH4 and H2 as the test samples and use dual-BP neural-network with the temperature and humidity compensation function as the method to recognize and measure single gas and mixed gases respectively. The result shows that the measuring instrument has higher measuring accuracy and overcomes the shortcoming of other methods, and has important practical application value.

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Jiang, Hong Xu, Wei Zhao, Xiao Hong Zhang, and Jin Yuan Lu. "Design and Implementation of CABAC Parallelization on Multicore DSP." Applied Mechanics and Materials 340 (July 2013): 685–90. http://dx.doi.org/10.4028/www.scientific.net/amm.340.685.

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This work mainly focus on the design and implementation of context-based adaptive binary arithmetic coding (CABAC) parallelization on multicourse digital signal processor (DSP) platform. Syntax elements partitioning based on load balancing is proposed to achieve data parallelization of CABAC. On the multicourse DSP, a task-dispatch structure is proposed. Inter-core communication is achieved by combination of shared memory and interrupt. And inter-core synchronization is achieved by combination of shared variable and hardware semaphore. The above structure makes the overall system clearer and program control easier. A speedup of 2.77 is obtained.

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Dong, Pei Chao, Hong Ke Xu, and Shan Lin. "Design and Implementation of Point Light Source Tracking System." Applied Mechanics and Materials 380-384 (August 2013): 609–12. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.609.

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Base on the fuzzy reasoning technology and digital signal processor technology, this paper designs a DSP-based point light source fuzzy tracking system, which can be used to improve the efficiency of solar panels. By analysis characteristics of the system and summing up the experience, it gave a set of fuzzy control rules, and determined some important control parameters. It uses the DSP as the core of the system control unit to ensure the real-time and stability. Simulation and experiments results show the system has a good performance.

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Sharma, Poonam, Ashwani Kumar Dubey, and Ayush Goyal. "Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier." Recent Patents on Engineering 13, no. 2 (2019): 174–80. http://dx.doi.org/10.2174/1872212112666180810150357.

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Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.

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Wang, Chao, Feng Su, and Yun Peng Han. "Design and Implementation of a Phase-Coded Quasi-CW Radar Signal Processor." Applied Mechanics and Materials 20-23 (January 2010): 785–90. http://dx.doi.org/10.4028/www.scientific.net/amm.20-23.785.

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A pseudo-random phase-coded quasi-CW radar signal processor is designed，and implemented based on a parallel signal processing platform. Distance sidelobe and “echo eclipse” are two problems inherent to the phase-coded quasi-CW radar. In this paper, “Code agility” method is used to suppress the distance sidelobe, which has good performance even when the radar echo is badly eclipsed. Software of the radar signal processor is characterized by pipelined processing, and the DSP program is based on real-time operation system. Results of the field experiment verify the correctness of our design.

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Huang, Jing, She Yu Zhou, and Bing Lei Guan. "Design of Online Pipeline Ultrasonic Data Acquisition and Storage System Based on PCI Bus." Applied Mechanics and Materials 651-653 (September 2014): 2296–300. http://dx.doi.org/10.4028/www.scientific.net/amm.651-653.2296.

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Based on the theory of ultrasonic testing, an online data-acquisition and storage system is designed. The design scheme of hardware and software of the system is introduced in this paper, in which the embedded processor DSP and FPGA is used as its control core and the interface of PCI bus and DSP is designed. Thus a high speed and large-capacity ultrasonic signal can be processed, furthermore the pipelines defects can be analyze and evaluate.

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Yu, Fei, Hong Mi Guo, and Yan He Chu. "Design of Photovoltaic Generation Grid-Connected Inverter Based on DSP." Advanced Materials Research 383-390 (November 2011): 3443–48. http://dx.doi.org/10.4028/www.scientific.net/amr.383-390.3443.

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According to characteristics of solar photovoltaic generation system, this paper presents a design of a single-phase photovoltaic grid-connected inverter about 1KW based on the digital signal processor TMS320F2812. This paper designs the algorithm of MPPT (Maximum Power Point tracking) and the algorithm of phase tracking according to its characteristics. The experiment is successful, and the output voltage wave of grid-connected inverter has the same frequency and phase with the grid voltage. The power factor of grid-connected inverter has reached to 0.99.

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LIU, WANLI, DAVID H. ALBONESI, JOHN GOSTOMSKI, et al. "AN EVALUATION OF A CONFIGURABLE VLIW MICROARCHITECTURE FOR EMBEDDED DSP APPLICATIONS." Journal of Circuits, Systems and Computers 13, no. 06 (2004): 1321–45. http://dx.doi.org/10.1142/s0218126604001994.

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The last decade has witnessed a significant increase in processor offerings geared towards embedded DSP applications. Such processors are commonly VLIW architectures with special ISA and/or microarchitecture features for speeding up signal processing functions and customization options to improve cost/performance. The Jazz Programmable System Architecture from Improv Systems is one such processor offering. Jazz employs a VLIW architecture which is well-suited to the characteristics of embedded DSP applications such as voice over packet, media processing, and home connectivity. The microarchitecture incorporates overlaid datapaths, distributed register file and memory systems, code compression, and parallel computation and memory access. Jazz permits design-time configuration in an attempt to bridge the gap between the flexibility of a programmable processor and the cost-benefit of full customization. In this paper, we explore the cost/performance tradeoffs of the Jazz microarchitecture on various embedded multimedia applications using a detailed cycle-level simulator as well as area and power models. Through a comparison of the performance, power, and area of different hardware configurations running these applications, we demonstrate how the configurability of the architecture affords a cost-performance benefit over a fixed microarchitecture. Key features of the microarchitecture are quantitatively evaluated in terms of their influence on performance. The relationship between compiler optimizations and processor performance is also explored.

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Wang, Ping, Gui Zhi Xu, Lei Wang, and Cheng Long Liu. "The Design of an Intelligent EEG Monitoring and Control System." Applied Mechanics and Materials 598 (July 2014): 583–86. http://dx.doi.org/10.4028/www.scientific.net/amm.598.583.

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The core device of our system is a handheld EEG monitoring analyzer, which is based on a new DSP (Digital Signal Processor) control system. The DSP is based on a Think-Gear module and collects the EEG signals reliably. The system only uses a dry electrode, which ensures that the user can have a happy experience in daily life. Our main purpose is that we can provide a hardware prototype with the application of BCI (Brain-Computer Interface).The system can monitor the sleep process accurately and distinguish the eyes open or closed state, sleep state and the degree of relaxation.

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Lewis, Mike, and Linda Brackenbury. "CADRE: A Low-power, Low-EMI DSP Architecture for Digital Mobile Phones." VLSI Design 12, no. 3 (2001): 333–48. http://dx.doi.org/10.1155/2001/47640.

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Current mobile phone applications demand high performance from the DSP, and future generations are likely to require even greater throughput. However, it is important to balance these processing demands against the requirement of low power consumption for extended battery lifetime. A novel low-power digital signal processor (DSP) architecture CADRE (Configurable Asynchronous DSP for Reduced Energy) addresses these requirements through a multi-level power reduction strategy. A parallel architecture and configurable compressed instruction set meets the throughput requirements without excessive program memory bandwidth, while a large register file reduces the cost of data accesses. Sign-magnitude representation is used for data, to reduce switching activity within the datapath. Asynchronous design gives fine-grained activity control without the complexities of clock gating, and gives low electromagnetic interference. Finally, the operational model of the target application allows for a reduced interrupt structure, simplifying processor design by avoiding the need for exact exceptions.

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Ahmad, M. O., and D. V. Poornalah. "Design of an efficient VLSI inner-product processor for real-time DSP applications." IEEE Transactions on Circuits and Systems 36, no. 2 (1989): 324–29. http://dx.doi.org/10.1109/31.20218.

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Hou, Si Zu, and Yong Zhang. "Hardware Design and Implementation of Power Line Carrier Communication for Medium Voltage Based on DSP." Advanced Materials Research 926-930 (May 2014): 490–93. http://dx.doi.org/10.4028/www.scientific.net/amr.926-930.490.

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A hardware system based on digital signal processor (DSP) is designed for power line carrier communication (PLC) over medium voltage power line networks. This system is designed to realize better stability and reliability of data communication in electric system. This paper introduces PLC technology, and then discusses the composition of this system and gives design scheme. Finally, the DSP implementation is developed with analog front-end (AFE) and coupling circuit. This paper shows a new PLC and automatic management solution.

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Liu, Yang, Yong Tie, Shun Na, and Dong Li. "Correlation Analyzer Project for Teaching Digital Signal Processing with MATLAB and DSP Processor." Applied Mechanics and Materials 263-266 (December 2012): 139–42. http://dx.doi.org/10.4028/www.scientific.net/amm.263-266.139.

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Digital signal processing (DSP) has become one of key enabling technologies for communications, condition monitoring, multimedia computing, wireless networks and other areas requiring signal and information processing. With the rapid growth of applications of digital signal processing in the world, it has become necessary to introduce these concepts to graduates and undergraduates. Teaching of digital signal processing is carried out not only at the electrical and electronic engineering departments as the most traditional interested in this subject, but also others technical universities are carried out lectures and tutorials. In this paper, a digital signal processing development process is described. It starts from the conceptual algorithm design and computer simulation using MATLAB. After verification of the algorithm, a fixed-point C program is developed for a specific fixed-point DSP processor. This application covers most topics included in a DSP courses performing independent multiple simple experiments. The used methodology enables students and engineers to understand and develop complex fixed-point applications on hardware implementations.

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Bu, Wei Jing. "A Novel Numerical Control Architecture Based on Multiprocessor and Real-Time Ethernet." Applied Mechanics and Materials 155-156 (February 2012): 120–24. http://dx.doi.org/10.4028/www.scientific.net/amm.155-156.120.

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The design of the CNC system to realize the function of the dedicated processor/modular is very select. Low cost of the ARM processor with Windows CE operating system is perfect for soft real-time tasks, such as the system state display, program explains, etc. The high performance DSP processors µ C/OS-II operating system is real-time tasks efforts, which is responsible for interpolation, speed control. In addition, to meet demand for the reconstruction of the design and flexible manufacturing, a reconfigurable based on FPGA technology for module, meet the functional requirement, build the PLC based on real-time Ethernet field bus network for simple connections between executors in the numerical control system controller.

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Zhang, Zeng Nian, Zun Yi Wang, Mian Mian Chen, and Jiong Shi. "Intelligent Transportation Video Detecting System Based on DSP." Applied Mechanics and Materials 701-702 (December 2014): 498–504. http://dx.doi.org/10.4028/www.scientific.net/amm.701-702.498.

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This paper proposes a method of realizing a moving vehicle video detecting system based on DSP processor, and describes the system's hardware architecture and software design in detail. Based on the characteristic of dual-core of DM6437 processor, the methods of communication protocol between ARM and DSP, as well as the double-buffer switching method are presented. Background modeling is made on the traffic video data from DM6437 via difference accumulation. Background subtraction is used to detect vehicle movement areas. With the adoption of algorithms such as Otsu, morphological filtering and region growing, the whole system is finally realized on the DM6446 hardware platform. Experimental results show that the system achieves good performance on moving vehicle detection.

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Chen, Chui Xin, and Yang Hong Mao. "Design and Implementation of Audio Process System Based on DSP." Advanced Materials Research 945-949 (June 2014): 1752–55. http://dx.doi.org/10.4028/www.scientific.net/amr.945-949.1752.

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The real-time processing for the input analog audio signal, audio processing program is proposed based on DSP. The system use FFT algorithm as the core, first, the input analog audio signal is sampled and A/D conversion using TLV320AIC23, and then use high speed digital signal processor to make real-time processing for the signal. Theoretical and experimental results show that the system can meet the design requirements, it has the advantage of high real-time and simple structure. The system has a good application and reference value for the development and design of data collecting and remote monitoring.

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TSAI, TSUNG-HAN, and LIAN-TSUNG TSAI. "AN EFFICIENT DESIGN FOR MOTION-JPEG2000 SYSTEM IN REAL-TIME VIDEO ENCODING." Journal of Circuits, Systems and Computers 17, no. 04 (2008): 597–610. http://dx.doi.org/10.1142/s0218126608004563.

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Motion-JPEG2000 is derived from Part 1 of the JPEG2000 standard and provides high quality image compression in video coding system. This paper presents a real-time Motion-JPEG2000 encoding which is built on a fixed-point digital signal processor (DSP) as a single-chip implementation. The design addresses on the system-level design considerations. Among several modules in JPEG2000, Embedded Block Coding with Optimized Truncation (EBCOT) algorithm contains the highest computation complexity and also becomes the bottleneck of JPEG2000. Two speed-improved methods are proposed to significantly reduce the processing time of EBCOT. The fast algorithm is used by processing the three coding passes in sequential and is very suitable to the execution on programming-based processor. For Motion-JPEG2000 implementation, a real-time encoding system is built on the single-chip DSP processor without any extra hardware support. The optimization techniques are also applied to enhance the performance. Due to the contribution on algorithm and implementation issue, the complexity of Motion-JPEG2000 is largely reduced. Simulation results show that the proposed system can process 30 frames per second in CIF size (352 × 288 pixels) with 4:2:0 video sequences. For SDTV size resolution (760 × 480 pixels), the system can achieve near 20 frames per second.

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Liu, Li, and Qing Hong Wu. "Image Acquisition Method Based on TMS320DM642." Applied Mechanics and Materials 397-400 (September 2013): 2196–99. http://dx.doi.org/10.4028/www.scientific.net/amm.397-400.2196.

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A method of the image acquisition based on digital signal processor (DSP) is introduced. DSP, complex programmable logic device (CPLD) and contact image sensor (CIS) are combined in the hardware design, and the time-sequence analysis of the image acquisition process is also presented. Practical application indicates that this method has high accuracy and is rapid enough to satisfy the requirement of real-time acquisition.

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Li, Chun Tian, Yi Luo, Chang Hua Du, and Gui Sheng Gan. "The Design of TIG-AWP Based on Inverter and DSP." Applied Mechanics and Materials 236-237 (November 2012): 484–87. http://dx.doi.org/10.4028/www.scientific.net/amm.236-237.484.

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The main circuit of tungsten inert gas (TIG) arc welding power (AWP), which is mode of the inverter for intermediate frequency and full-bridge IGBT, is designed based on DSP (Digital Signal Processor). The control designing, also based on DSP, include the sampling signal circuit, the control circuit for external characteristics, the PWM (Pulse-Width -Modulation) control circuit of TIG-AWP, the IGBT drive circuit and etc. This designing can strengthen the reliability of feedback regulation property on TIG-AWP; can enhance the stability of the parameters from the power system. The experimental result shows that the designed TIG-AWP has good feedback regulation and stability properties during the TIG welding process.

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Yuan, Zhong Hu, Shuo Jun Yu, and Xiao Wei Han. "Design of Weld Seam Tracking Control System Based on DSP." Applied Mechanics and Materials 55-57 (May 2011): 1759–63. http://dx.doi.org/10.4028/www.scientific.net/amm.55-57.1759.

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In the process of weld seam tracking, traditional mathematical model of classical and modern control theory is hard to meet the requirement of high performance controller. This article based on the embedded digital signal processor DSP-TMS320F2812 for the field of industrial automation control.The fuzzy control technology is applied to real-time welding seam-tracking system, according to the F2812 which has the characteristics of real-time multitasking scheduling of resources and then designed the real-time control value adjustment Fuzzy-PI control system. The designed DSP real-time fuzzy control system gives full play to powerful control and signal processing ability of F2812, it can fully adapt for the controlling requirement of super-speed and high-precision.

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Dramicanin, Dejan, Dejan Rakic, Slobodan Denic, and Veljko Vlahovic. "FPGA-based prototyping of IEEE 802.11a base band processor." Serbian Journal of Electrical Engineering 1, no. 3 (2004): 125–36. http://dx.doi.org/10.2298/sjee0403125d.

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In technical literature and especially in domestic, predominant way to examine performance of 802.11a-based systems are experiments in simulations. In this paper, we present FPGA based 802.11a prototype, which gave us a possibility to gain closer insight into the problems of OFDM system implementation. A specific design of base band modem physical layer is discussed, along with the presentation of the FPGA prototyping platform on which it was developed. Prototype is implemented on the latest generation of FPGA chips, using state-of-the-art tools for DSP development. Custom made development environment, and design flow optimized for rapid prototyping of software defined radios, are also presented in the paper.

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Li, Xing Ze, Ling Zhu, and Yi Hua. "Embedded Robot Vision System Based on DSP." Applied Mechanics and Materials 734 (February 2015): 168–71. http://dx.doi.org/10.4028/www.scientific.net/amm.734.168.

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Aim at the real-time problem of industrial robot vision system, design a embedded robot vision system based on DSP microprocessor. This system can use CCD camera and the ultrasonic sensor to collect the target environment information. It also can use the processor DSP to process the images and recognize target. And then through the communication module, send results in the form of wireless to the upper computer, providing target object information for robot control layer. This system completes the software and hardware system design, image collection & processing and robot control, as well as meet the real-time requirements of machine vision system.

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Li, Sheng Long, Zhao Lin Li, and Qing Wei Zheng. "Design of a Reconfigurable Coprocessor for Double Precision Floating Point Matrix Algorithms." Applied Mechanics and Materials 58-60 (June 2011): 1037–42. http://dx.doi.org/10.4028/www.scientific.net/amm.58-60.1037.

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Double precision floating point matrix operations are wildly used in a variety of engineering and scientific computing applications. However, it’s inefficient to achieve these operations using software approaches on general purpose processors. In order to reduce the processing time and satisfy the real-time demand, a reconfigurable coprocessor for double precision floating point matrix algorithms is proposed in this paper. The coprocessor is embedded in a Multi-Processor System on Chip (MPSoC), cooperates with an ARM core and a DSP core for high-performance control and calculation. One algorithm in GPS applications is taken for example to illustrate the efficiency of the coprocessor proposed in this paper. The experiment result shows that the coprocessor can achieve speedup a factor of 50 for the quaternion algorithm of attitude solution in inertial navigation application compare with software execution time of a TI C6713 DSP. The coprocessor is implemented in SMIC 0.13μm CMOS technology, the synthesis time delay is 9.75ns, and the power consumption is 63.69 mW when it works at 100MHz.

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Sethi, Kabiraj, and Rutuparna Panda. "Design and Implementation of a New Program Address Generator Unit in a DSP Processor." International Journal of Computer Applications 41, no. 12 (2012): 29–33. http://dx.doi.org/10.5120/5595-7841.

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Chen, Su Hua, Zhi Meng Shu, and Xu Fang. "The Research and Design of Image Processing System Based on FPGA and DSP." Advanced Materials Research 886 (January 2014): 556–59. http://dx.doi.org/10.4028/www.scientific.net/amr.886.556.

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In order to improve high performance and low power of image processing embedded system, A high-efficient image processing embedded system which is based on the field programmable gate array and high-speed digital signal processor in this paper. In the whole system, A novel data transmission structure with a dual-port RAM which is divided into two halves, is applied to buff the high-speed real-time image data by Ping-pong technique. Because all work in the system is divided between the FPGA and DSP in the form of the pipelined, it is 25% higher than the processing system based on the single DSP in performance.

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Fu, Qing Qing, and Zheng Bin Liang. "The Design of Textile Image Processing System." Applied Mechanics and Materials 148-149 (December 2011): 250–53. http://dx.doi.org/10.4028/www.scientific.net/amm.148-149.250.

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According to the drawback of high cost and complicated circuit and inadequate use of resources in DSP and FPGA structure of textile image processing, an image processing system based on Nios II in FPGA is designed. FPGA is the core of the system.Nios II processor is created in FPGA.Video image is acquired by CCD and processed in FPGA. The result shows that the system has some characteristics of small size, low cost, high integration, high stability and flexibility.

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Hu, Li Wei. "A Design and Implementation for the Auto-Booting of Baseband Board with ARM, DSP and FPGA." Applied Mechanics and Materials 721 (December 2014): 349–52. http://dx.doi.org/10.4028/www.scientific.net/amm.721.349.

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In this paper, I propose a solution for the auto-booting of baseband board, including the auto-booting of an ARM processor and the configuration of a FPGA chip. The baseband board’s FPGA chip is Xilinx’s XC6VSX475T which belongs to Virtex-6 series, the ARM processor is TI’s DM8168. ARM processor boots from nandflash, using uboot as its boot loader. I use Slave SelectMAP mode with 8-bit data bus interface as FPGA configuration mode. This paper introduces the transplantation of uboot and the FPGA configuration process with details, also analyses the result. This solution has already been used in TD-LTE TTCN extended test sets instrument, and it works well, which proves itself a practical solution.

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Chen, Nan. "Design of Micro Inertial Navigation Computer and Data Real-Time Displaying System Based on FPGA." Advanced Materials Research 919-921 (April 2014): 2123–26. http://dx.doi.org/10.4028/www.scientific.net/amr.919-921.2123.

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To meet the demands of high precision and real-time navigation calculating of some tiny volume projectiles in engineering, a kind of FPGA + DSP architecture hardware calculating system is designed. It transmits motion and attitude information through the wireless transmission and displays the messages on upper computer. In the system, FPGA is the kernel controller, which is used to control all timing logic, start the DSP calculating and transmit the wireless data of navigation information and data acquisition of micro inertial measurement unit (MIMU). DSP as a processor for navigation algorithm, calculates the navigation parameters and transmits the result to FPGA. This design system has the characteristics of low power consumption, small volume and high flexibility. It can collect MIMU data, transmit wireless data and display navigation information on upper computer. The experiment proved that the method is feasible

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Maladkar, Kishan. "Design and Implementation of a 32-bit Floating Point Unit." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (2021): 731–36. http://dx.doi.org/10.22214/ijraset.2021.35052.

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A Floating Point Unit is a math co-processor that is in the most demand of Digital Signal Processing (DSP), Processors and more. It is used to perform functions or operations on floating point numbers like addition, subtraction, multiplication, division, square root and more. It is specifically designed to carry out mathematical operations and it can be emulated in CPU. Floating point unit is a common operation used in advanced Digital Signal Processing and various processor applications. The aim was to develop an optimized floating point unit so that the delay was reduced and efficiency was increased. The floating point unit has been written according to IEEE 754 standard and the entire design has been coded in Verilog HDL. The results are improved by 12% with the usage of Vedic multiplier that is a delay of 4.450ns as compared to 5.123ns with an array multiplier. Designs can be further optimized using low power designing techniques at architectural level. Different behaviour can be observed for different size and technologies.

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Journal articles on the topic 'DSP processor design'

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