Dissertations / Theses on the topic 'DSP processor'

This Master thesis describes the benchmarking of a DSP processor. Benchmarking means measuring the performance in some way. In this report, we have focused on the number of instruction cycles needed to execute certain algorithms. The algorithms we have used in the benchmark are all very common in signal processing today.

The results we have reached in this thesis have been compared to benchmarks for other processors, performed by Berkeley Design Technology, Inc.

The algorithms were programmed in assembly code and then executed on the instruction set simulator. After that, we proposed changes to the instruction set, with the aim to reduce the execution time for the algorithms.

The results from the benchmark show that our processor is at the same level as the ones tested by BDTI. Probably would a more experienced programmer be able to reduce the cycle count even more, especially for some of the more complex benchmarks.

This Master Thesis presents the design of the core of a fixed point general purpose multimedia DSP processor (MDSP) and its instruction set. This processor employs parallel processing techniques and specialized addressing models to speed up the processing of multimedia applications.

The MDSP has a dual MAC structure with one enhanced MAC that provides a SIMD, Single Instruction Multiple Data, unit consisting of four parallel data paths that are optimized for accelerating multimedia applications. The SIMD unit performs four multimedia- oriented 16- bit operations every clock cycle. This accelerates computationally intensive procedures such as video and audio decoding. The MDSP uses a memory bank of four memories to provide multiple accesses of source data each clock cycle.

This thesis describes the design of a domain specific DSP processor. The thesis is divided into two parts. The first part gives some theoretical background, describes the different steps of the design process (both for DSP processors in general and for this project) and motivates the design decisions made for this processor.

The second part is a nearly complete design specification.

The intended use of the processor is as a platform for hardware acceleration units. Support for this has however not yet been implemented.

The purpose of this thesis is to retarget a C compiler for a DSP processor.

Developing a new compiler from scratch is a major task. Instead, modifying an existing compiler so that it generates code for another target is a common way to develop compilers for new processors.

This is called retargeting. This thesis describes how this was done with the LCC C compiler for the Motorola DSP56002 processor.

This thesis describes the design of fast JPEG processing accelerators for a DSP processor.

Certain computation tasks are moved from the DSP processor to hardware accelerators. The accelerators are slave co processing machines and are controlled via a new instruction set. The clock cycle and power consumption is reduced by utilizing the custom built hardware. The hardware can perform the tasks in fewer clock cycles and several tasks can run in parallel. This will reduce the total number of clock cycles needed.

First a decoder and an encoder were implemented in DSP assembler. The cycle consumption of the parts was measured and from this the hardware/software partitioning was done. Behavioral models of the accelerators were then written in C++ and the assembly code was modified to work with the new hardware. Finally, the accelerators were implemented using Verilog.

Extension of the accelerator instructions was given following a custom design flow.

Micro processors built specifically for digital signal processing are DSP processors. DSP is one of the core technologies in rapidly growing applications like communications and audio processing. The estimated growth of DSP processors in the last 6 years is over 40%. The variety of DSP capable processors for various applications also increased with the rising popularity of DSP processors. The design flow and architecture of such processors are not commonly available to students for learning.

This report is a structured approach to design and implementation of an embedded DSP processor core for voice, audio and video codec. The report focuses on the design requirement specification, senior instruction set and assembly manual release, micro architecture design and implementation of the core. Details about the core verification are also included in this report. The instruction set of this processor supports running basic kernels of BDTI benchmarking.

Digital Signal Processing (DSP) processors are used in personal computers, smart phones, multimedia devices, etc. Traditional DSP processors with custom logic must meet the demand for increased processing speed. The main aim of the project is to design a 32-bit integer arithmetic processor and to implement it. This design has three major processing features. First, the speed must be optimized by using a hazard free control unit. Second, it must have a two stage pipeline. Third, a single cycle multiply accumulator is utilized. The main advantage of the two stage pipeline is that it can manipulate the instructions, and it can produce correct cycle timing even though there may be hazards. A reduced instruction set is used in this design. A filtering operation is included in order to differentiate the DSP processor from a traditional processor. The processor is designed using Harvard architecture in which both data memory and program memory are accessed simultaneously. This design increases the processing speed by 30%.

In mobile digital devices, low power consumption is an important matter to reduce the need for a heavy and big battery. One way of reducing the power consumption is to construct the hardware so that the performance is optimal for the application. The demand of performance is dependent of the tasks that the device will be performing. This is where scalable structure of the hardware is an idea to solve the problem.

This master thesis serve as a starting point for developing a digital signal processor with scalable structure. The digital signal processor is a common and important part of digital processing. Scalable struture is in this case adding and removing parts of the memory and/or the instruction set, and to make the data wordlength variable. The development is simplified by modeling it on an existing processor. The result of this master thesis is an instruction simulator written in C language. The simulator will be a model for development of the hardware.

The P3RMA (Programmable, Parallel, and Predictable Random Memory Access) processor, currently being developed at Linköping University Sweden, is an attempt to solve the problems of parallel computing by utilizing a parallel memory subsystem and splitting the complexity of address computations with the complexity of data computations. It is targeted at embedded low power low cost computing for mobile phones, handsets and basestations among many others. By studying the radix-2 FFT using the P3RMA concept we have shown that even algorithms with a complex addressing pattern can be adapted to fully utilize a parallel datapath while only requiring additional simple addressing hardware. By supporting this algorithm with a SIMT instruction almost 100% utilization of the datapath can be achieved. A simulator framework for this processor has been proposed and implemented. This simulator has a very flexible structure featuring modular addition of new instructions and configurable hardware parameters. The simulator might be used by hardware developers and firmware developers in the future.

The purpose of this thesis is to construct a"Program Address Generator"(PAG) to a 24-bit Harvard type, RISC DSP processor using the VHDL language. The PAG is a part of the program control unit, and should consist of the following units:

A system stack for storing jump and loop information. A program counter, a status register, a stack pointer, an operating mode register and two registers called loop address and loop counter register, to support hardware loops.

The PAG handles the fetch stage of the processor pipeline, and should handle instructions such as the jump, subroutine jump, return from subroutine/interrupt and loop instructions, among others.

The PAG was successfully designed, and its function verified through extensive tests, where common combinations of ASM instructions were tested. Files for automated testing was created, to support easy testing if only small changes are applied to the PAG.

The Division of Computer Engineering at Linköping's university is currently researching the possibility to create a highly parallel DSP platform, that can keep up with the computational needs of upcoming standards for various applications, at low cost and low power consumption. The architecture is called ePUMA and it combines a general RISC DSP master processor with eight SIMD co-processors on a single chip. The master processor will act as the main processor for general tasks and execution control, while the co-processors will accelerate computing intensive and parallel DSP kernels.This thesis investigates the performance potential of the co-processors by implementing matrix algebra kernels for QR decomposition, LU decomposition, matrix determinant and matrix inverse, that run on a single co-processor. The kernels will then be evaluated to find possible problems with the co-processors' microarchitecture and suggest solutions to the problems that might exist. The evaluation shows that the performance potential is very good, but a few problems have been identified, that causes significant overhead in the kernels. Pipeline mismatches, that occurs due to different pipeline lengths for different instructions, causes pipeline hazards and the current solution to this, doesn't allow effective use of the pipeline. In some cases, the single port memories will cause bottlenecks, but the thesis suggests that the situation could be greatly improved by using buffered memory write-back. Also, the lack of register forwarding makes kernels with many data dependencies run unnecessarily slow.

The goal of this bachelor thesis has been to investigate if the laboratory exercises in the courses digital filters and linear systems can be moved from matlab to a digital signal processor. The processor is a TMS320C6713 floating point processor mounted on a development board.

The original laboratories have been implemented and analyzed and some suggested changes have been presented for the digital filter laboration. For the laboration in linear systems, the exercise can be implemented as it is today. Furthermore, a transmultiplexer has been implemented and tested for real time execution.

Finally, an application programming interface has also been implemented, with common functions, used in the laboratories.

Att ansluta en digital signalprocessor kräver ett omfattande arbete. Innehållet i denna rapport sammanfattar teoretiska metoder för att integrera den digitala signalprocessorn ADAU1701 i talförstärkaren MMT-4, utvecklad av företaget Xena Medical. Arbetet har till största delen bestått i att finna en lämplig DSP och studera dess datamanual för att anpassa den till talförstärkaren.

Mycket av rapporten sammanfattar beräkningar av komponentvärden och anpassning av ADAU1701 för MMT-4:s behov. ADAU1701 beskrivs utifrån det så kallade selfboot-läget där processorn kan arbeta som fristående processor.

This thesis describes how to integrate a digital signal processor (DSP) in the speech amplifier MMT-4. This is to improve the sound quality and prevent feedback. Much of the task consisted of selecting a suitable DSP design and components to get it work as a standalone processor in MMT-4. Following this report gives the reader an introduction how to design systems with a DSP and a full description of the DSP ADAU1701.

There is a lot of applications for DSPs (Digital Signal Processor) in the most rapidly growing areas in the industry right now as wireless communication along with audio and video products are getting more and more popular. In this report, a DSP, developed at the division of Computer Engineering at the University of Linköping, is optimized and verified.

Register Forwarding was implemented on a general architecture level to avoiddata hazards that may arise when implementing instruction pipelining in a processor.

The very common FFT algorithm is also optimized but on instruction setlevel. That means the algorithm is carefully analyzed to find operations that mayexecute in parallel and then create new instructions for these parallel operations.The optimization is concentrated on the butterfly operation as it is such a majorpart of the FFT computation. Comparing the accelerated butterfly with the unaccelerated gives an improvement of 30% in terms of clock cycles needed for thecomputation.

In the report there are also some discussions about the benefits and drawbacksof changing from a hardware to a software stack, mostly in terms of interrupts andthe return instruction.

Another important property of the processor is scalability. That is, it is possibleto attach extra peripherals to the core, which accelerates certain tasks. Aninterface towards these peripherals is developed along with two template designsthat may be used to develop other peripherals.

After all these modifications, a new test bench is developed to verify the functionality.

H.264 is a video coding standard which offers high data compression rate at the cost of a high computational load. This thesis evaluates how well parts of the H.264 standard can be implemented for a new multi-core digital signal processing processor architecture called ePUMA. The thesis investigates if real-time encoding of high definition video sequences could be performed. The implementation consists of the motion estimation, motion compensation, discrete cosine transform, inverse discrete cosine transform, quantization and rescaling parts of the H.264 standard. Benchmarking is done using the ePUMA system simulator and the results are compared to an implementation of an existing H.264 encoder for another multi-core processor architecture called STI Cell. The results show that the selected parts of the H.264 encoder could be run on 6 calculation cores in 5 million cycles per frame. This setup leaves 2 calculation cores to run the remaining parts of the encoder.

There is a lot of literature already available describing well-structured approach for embeddeddesign and implementation of Application Specific Integrated Processor (ASIP) micro processorcore.

This concept features hardware structured approach for implementation of processor core fromminimal instruction set, encoding standards, hardware mapping, and micro architecture design,coding conventions, RTL,verification and burning into a FPGA. The goal is to design an ASIPprocessor core (Micro architecture design and RTL) which can perform DSP task, e.g., FIR. Thereport is a well structured approach of design and implementation of an ASIP DSP processor forDSP applications like FIR. This report contains design flow starting from Instruction set design,micro architecture design and RTL implementation of the core. Details of the power simulationsof FPGA are also listed and analyzed.

The thesis work is conducted in the division of computer engineering at thedepartment of electrical engineering in Linköping University. During the thesiswork, a configurable Direct Memory Access (DMA) controller was designed andimplemented. The DMA controller runs at 200MHz under 65nm digital CMOS technology. The estimated gate count is 26595.

The DMA controller has two address generators and can provide two clocksources. It can thus handle data read and write simultaneously. There are 16channels built in the DMA controller, the data width can be 16-bit, 32-bit and64-bit. The DMA controller supports 2D data access by configuring its intelligentlinking table. The DMA is designed for advanced DSP applications and it is notdedicated for cache which has a fixed priority.

This thesis is about a number of improvements and additions done to a soft CPU optimized for field programmable gate arrays (FPGAs). The goal has been to implement the changes without substantially lowering the CPU's ability to operate at high clock frequencies. The result of the thesis is a number of high clock frequency modules, which when added completes the CPU hardware functionality in certain areas. The maximum frequency of the CPU is however somewhat lowered after the modules have been added.

Detta examensarbete handlar om ett antal förbättringar och utökningar av en mjuk processor speciellt anpassad för fältprogrammerbara grindmatriser (FPGA). Målet har varit att göra förändringarna utan att göra större avkall på processorns förmåga att operera i höga klockfrekvenser. Resultatet av examensarbetet är ett antal moduler som klarar av höga frekvenser och kompletterar processorns hårdvarufunktioner. Dock reduceras maxfrekvensen på processorn något med modulerna tillagda.