Log in

Relevant bibliographies by topics / DSP processor / Journal articles

To see the other types of publications on this topic, follow the link: DSP processor.

Journal articles on the topic 'DSP processor'

Author: Grafiati

Published: 4 June 2021

Last updated: 15 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'DSP processor.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Saastamoinen, Piia, Ilkka Saastamoinen, and Jari Nurmi. "Code compression in DSP processor systems." International Journal of Embedded Systems 3, no. 4 (2008): 256. http://dx.doi.org/10.1504/ijes.2008.022396.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Lapsley, P., and G. Blalock. "How to estimate DSP processor performance." IEEE Spectrum 33, no. 7 (July 1996): 74–78. http://dx.doi.org/10.1109/6.526871.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

de Dinechin, Benoit Dupont, Christophe Monat, Patrick Blouet, and Christian Bertin. "DSP-MCU processor optimization for portable applications." Microelectronic Engineering 54, no. 1-2 (December 2000): 123–32. http://dx.doi.org/10.1016/s0167-9317(00)80064-7.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Mochida, Yukou, and Toshitaka Tsuda. "Special edition Digital signal processor. DSP applications." Journal of the Institute of Television Engineers of Japan 41, no. 3 (1987): 234–41. http://dx.doi.org/10.3169/itej1978.41.234.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Yu, Xiao Bo, Yun Feng Zhang, and Yao Gang Fu. "Research on Applied Technology in Digital Signal Processor (DSP)." Advanced Materials Research 978 (June 2014): 193–96. http://dx.doi.org/10.4028/www.scientific.net/amr.978.193.

Full text

Abstract:

Based on the advance of computer and modern electronic technology, technology of digital signal processor (DSP) and DSP chips have mutual promotion. And the functions of DSP chips have been improved greatly and the fields in which they are applied have also been increasingly expanded. Nowadays, they can be applied in all aspects of modern people’s life and work such as computer enclosure, communication and industrial control.

APA, Harvard, Vancouver, ISO, and other styles

6

Lian, Jin Hua. "A New Microprocessor Protection Scheme Based on Digital Signal Processor." Applied Mechanics and Materials 397-400 (September 2013): 1854–57. http://dx.doi.org/10.4028/www.scientific.net/amm.397-400.1854.

Full text

Abstract:

Based on the demand of power department, a protection & monitoring device for the power distribution line is studied. The device using DSP as the core technology is a new industrial control unit, which adopts the of dual CPU of DSP+DSP and consists of chip selection unit, A/D conversion, data storage, watchdog circuit, press key, switch quantity detection, control output, communication, display and clock etc. The software system includes two parts: tracking software and protection software. The device ensures the high reliability and feasibility, at same time incarnates the advantage of microprocessor protection by intelligent designs.

APA, Harvard, Vancouver, ISO, and other styles

7

Glinski, S., and D. Roe. "Spoken language recognition on a DSP array processor." IEEE Transactions on Parallel and Distributed Systems 5, no. 7 (July 1994): 697–703. http://dx.doi.org/10.1109/71.296316.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Fan, Jia Liang, and Qiang Yang. "A New Radar Signal Processing Architecture Based on Multi-Core Processor." Applied Mechanics and Materials 556-562 (May 2014): 1618–21. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1618.

Full text

Abstract:

Most radar systems based on the structure that contains many DSP chips. The system structure is always complex, and it is difficult to update. Nowadays, multi-core processor develops very fast. Compared with DSP chips, multi-core processor has better performance in signal processing field. In this paper, we present a signal processing architecture which based on multi-core processor. Pulse compression algorithms and PCI-E bus are discussed as two important technologies. Adaptive beamforming test results show that multi-core processor is able to achieve radar signal processing.

APA, Harvard, Vancouver, ISO, and other styles

9

Bormann, Frank. "Teaching DSP in Digital Control." International Journal of Electrical Engineering & Education 49, no. 3 (July 2012): 291–301. http://dx.doi.org/10.7227/ijeee.49.3.8.

Full text

Abstract:

The paper describes an approach to introduce digital signal processors (DSPs) in teaching digital control for undergraduates in electrical engineering. The article focuses first on the increasing demand for computational power from new mathematical approaches to digital control techniques, such as digital power supply, digital motor control, photovoltaic inverters, inverters for solar arrays and LED illuminating. The challenge for educators is to provide both a basic understanding of hardware and software modules on processor technology and a reasonable mathematical background to the underlying theory. Over the last decade the author has developed a set of teaching modules based on the C2000 family of digital signal controllers. As an example of students' work, the paper also describes a project based on an autonomous driving car.

APA, Harvard, Vancouver, ISO, and other styles

10

Park, Sung-Wook. "A Design of Superscalar Digital Signal Processor." Journal of Korean Institute of Intelligent Systems 18, no. 3 (June 25, 2008): 323–28. http://dx.doi.org/10.5391/jkiis.2008.18.3.323.

Full text

APA, Harvard, Vancouver, ISO, and other styles

11

Deng, Shu Zhang. "Research on DSP Embedded Digital Signal Processing System for Ship Navigation Radar." Applied Mechanics and Materials 556-562 (May 2014): 4718–21. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.4718.

Full text

Abstract:

Development of digital signal processing and embedded technologies today, to the development of radar technology has brought new opportunities. Relative to the simulation of radar, digital radar has good performance, features, ease of operation, and other benefits. Design based on embedded processor and digital signal processor (DSP) dual processor shipboard navigation radar system, and focuses on digital shipborne navigational radar system architecture, hardware design and software algorithms for digital signal processing module, gives the overall scheme for DSP systems.

APA, Harvard, Vancouver, ISO, and other styles

12

Sinha, Amitabha, Mitrava Sarkar, Soumojit Acharyya, and Suranjan Chakraborty. "A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays." ACM SIGARCH Computer Architecture News 41, no. 2 (May 29, 2013): 1–8. http://dx.doi.org/10.1145/2490302.2490304.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Savadi, Anuradha, Raju Yanamshetti, and Jyoti Godihal. "Design and Synthesis of High Performance Vedic DSP Processor." International Journal of Computer Applications 168, no. 6 (June 15, 2017): 27–32. http://dx.doi.org/10.5120/ijca2017914469.

Full text

APA, Harvard, Vancouver, ISO, and other styles

14

Giridhar, J., and K. M. M. Prabhu. "Implementation of MTD-WVD on a TMS320C30 DSP processor." Microprocessors and Microsystems 22, no. 1 (June 1998): 1–12. http://dx.doi.org/10.1016/s0141-9331(98)00068-4.

Full text

APA, Harvard, Vancouver, ISO, and other styles

15

Cheah, Hui Yan, Fredrik Brosser, Suhaib A. Fahmy, and Douglas L. Maskell. "The iDEA DSP Block-Based Soft Processor for FPGAs." ACM Transactions on Reconfigurable Technology and Systems 7, no. 3 (August 2014): 1–23. http://dx.doi.org/10.1145/2629443.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

ARIVAZHAGAN, S., D. GNANADURAI, J. R. ANTONY VANCE, K. M. SAROJINI, and L. GANESAN. "IMPLEMENTATION OF ZERO TREE WAVELET CODERS IN DSP PROCESSOR." International Journal of Wavelets, Multiresolution and Information Processing 02, no. 01 (March 2004): 75–86. http://dx.doi.org/10.1142/s0219691304000366.

Full text

Abstract:

With the fast evolution of Multimedia systems, Image compression algorithms are very much needed to achieve effective transmission and compact storage by removing the redundant information of the image data. Wavelet transforms have received significant attention, recently, due to their suitability for a number of important signal and image compression applications and the lapped nature of this transform and the computational simplicity, which comes in the form of filter bank implementations. In this paper, the implementation of image compression algorithms based on discrete wavelet transform such as embedded zero tree wavelet (EZW) coder, set partitioning in hierarchical trees coder without lists (SPIHT — No List) and packetizable zero tree wavelet (PZW) coder in DSP processor is dealt in detail and their performance analysis is carried out in terms of different compression ratios, execution timing and for different packet losses. PSNR is used as the criteria for the measurement of reconstructed image quality.

APA, Harvard, Vancouver, ISO, and other styles

17

Muller, U. A., A. Gunzinger, and W. Guggenbuhl. "Fast neural net simulation with a DSP processor array." IEEE Transactions on Neural Networks 6, no. 1 (1995): 203–13. http://dx.doi.org/10.1109/72.363436.

Full text

APA, Harvard, Vancouver, ISO, and other styles

18

Kidode, Masatsugu. "Special edition Digital signal processor. Future trends of DSP." Journal of the Institute of Television Engineers of Japan 41, no. 3 (1987): 242–47. http://dx.doi.org/10.3169/itej1978.41.242.

Full text

APA, Harvard, Vancouver, ISO, and other styles

19

MINGESZ, R., P. BARA, Z. GINGL, and P. MAKRA. "DIGITAL SIGNAL PROCESSOR (DSP) BASED 1/fa NOISE GENERATOR." Fluctuation and Noise Letters 04, no. 04 (December 2004): L605—L616. http://dx.doi.org/10.1142/s0219477504002233.

Full text

Abstract:

1/f noise is present in many natural and artificial systems, and even though it was discovered decades ago, it is still not completely understood. Due to the lack of an universal model, the main methods of investigating a system where 1/f noise is present are numerical simulations and real measurements. The second method can lead to more adequate results, since it is free from numerical artifacts. In the case of real measurements, we need reliable, wide-band noise generators. Many ways of generating noise are known; most of them have several limitations on the frequency bandwidth or on spectral properties. We wanted to create a device which is easy to use, which can generate any kind of 1/fa (0 < a < 2) noise and whose bandwidth is wide enough to make our investigations. We used a DSP (ADSP2181) to numerically generate the desired noise, and a D/A converter to convert it to an analogue signal. The noise generation algorithm was based on the known method of filtering a Gaussian white noise with a series of first-order digital filters. We enhanced this method to get a better spectral shape and to compensate for the side effects of the digital-to-analogue conversion.

APA, Harvard, Vancouver, ISO, and other styles

20

Ramadevi T, Reena, and Raghavaiah B. "Implementation of Low Power RISC Based Flexible DSP Processor." International Journal of Engineering Trends and Technology 49, no. 3 (July 25, 2017): 186–91. http://dx.doi.org/10.14445/22315381/ijett-v49p230.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Wan, Xiong, Dong Gang Yao, Zhi Min Zhang, Hua Ming Zhang, and Wen Bo Xiao. "Design of Data Acquisition System Based on DSP and Optical Fiber Bundle." Advanced Materials Research 629 (December 2012): 725–29. http://dx.doi.org/10.4028/www.scientific.net/amr.629.725.

Full text

Abstract:

This paper introduces the design of a DSP-based acquisition system with high parallelism of the beam. The system uses fiber arrays connected to spatial filters as the detection devices. A TMS320LF2407A DSP is adopted as the primary embedded processor, which connects Analog to Digital (A/D) converters via I/O ports. Simultaneously, the processor realizes the parallel processing of data storage, transmission and calculation. The design of the main processor control module, the signal processing module and its corresponding software, are discussed in detail.

APA, Harvard, Vancouver, ISO, and other styles

22

LIU, WANLI, DAVID H. ALBONESI, JOHN GOSTOMSKI, LLOYD PALUM, DAVE HINTERBERGER, RICK WANZENRIED, and MARK INDOVINA. "AN EVALUATION OF A CONFIGURABLE VLIW MICROARCHITECTURE FOR EMBEDDED DSP APPLICATIONS." Journal of Circuits, Systems and Computers 13, no. 06 (December 2004): 1321–45. http://dx.doi.org/10.1142/s0218126604001994.

Full text

Abstract:

The last decade has witnessed a significant increase in processor offerings geared towards embedded DSP applications. Such processors are commonly VLIW architectures with special ISA and/or microarchitecture features for speeding up signal processing functions and customization options to improve cost/performance. The Jazz Programmable System Architecture from Improv Systems is one such processor offering. Jazz employs a VLIW architecture which is well-suited to the characteristics of embedded DSP applications such as voice over packet, media processing, and home connectivity. The microarchitecture incorporates overlaid datapaths, distributed register file and memory systems, code compression, and parallel computation and memory access. Jazz permits design-time configuration in an attempt to bridge the gap between the flexibility of a programmable processor and the cost-benefit of full customization. In this paper, we explore the cost/performance tradeoffs of the Jazz microarchitecture on various embedded multimedia applications using a detailed cycle-level simulator as well as area and power models. Through a comparison of the performance, power, and area of different hardware configurations running these applications, we demonstrate how the configurability of the architecture affords a cost-performance benefit over a fixed microarchitecture. Key features of the microarchitecture are quantitatively evaluated in terms of their influence on performance. The relationship between compiler optimizations and processor performance is also explored.

APA, Harvard, Vancouver, ISO, and other styles

23

Zhang, Xiao Ling, Peng Xie, and Bao Feng Zhang. "DSP Transplantation of Motion Object Detection Algorithm Based on TMS320DM642." Applied Mechanics and Materials 577 (July 2014): 790–93. http://dx.doi.org/10.4028/www.scientific.net/amm.577.790.

Full text

Abstract:

To build motion object detection system based on DSP (Digital Signal Processor), the motion object detection algorithm by existing is transplanted to the DSP development environment based on adopted DSP hardware system.DSP migration process of the moving object detection algorithm is expounded. First of all, Real-time Workshop tool module in Simulink to establish CCS project file which can be identified by TMS320DM642, then testis processor in the loop (PIL) to verify its correctness. Create system model by Simulink instead of the traditional programming to create DSP project files shorten the development cycle and improve the enforceability of the program. Theresults show that the project files generated by the Simulink can meet the requirements in terms of complete moving object detection.

APA, Harvard, Vancouver, ISO, and other styles

24

Kong, Su Ran. "FPGA + DSP-Based Real-Time Image Acquisition System Research and Design." Advanced Materials Research 433-440 (January 2012): 5482–88. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.5482.

Full text

Abstract:

Image processing system to calculate the volume, real-time high and the requirements of small size, using the DSP-based processor, FPGA approach, supplemented by the processor design of a high-performance real-time image processing system, and the system In the process of image acquisition and transmission of noise, using the PCB's anti-jamming design. Practice shows that two chips using FPGA + DSP, the algorithm is divided into two parts by the FPGA and DSP processing; effectively improve the efficiency of the algorithm. System real-time high, adaptability, real-time image acquisition system can meet the design requirements.

APA, Harvard, Vancouver, ISO, and other styles

25

Dahnoun, N., and J. Brand. "Teaching DSP Implementation: The Big Picture." International Journal of Electrical Engineering & Education 49, no. 3 (July 2012): 202–9. http://dx.doi.org/10.7227/ijeee.49.3.2.

Full text

Abstract:

Starting a digital signal processing (DSP) implementation course can be a daunting task, especially with the advanced DSP algorithms, complex DSP processor architectures and sophisticated development tools that are developed to satisfy consumer demands. These courses can be split into disciplines such as control, audio and video. In this paper the authors are addressing the concerns associated with fast-growing DSP chips and tools and the impact they have on teaching DSP implementation. The authors also provide solutions, advice and suggestions on how to select a DSP, set a DSP implementation course and the associated laboratory hardware and software that fit a specific application.

APA, Harvard, Vancouver, ISO, and other styles

26

Wu, Xun, Yue Song Mei, Jian Qiao Yu, Tian Peng Yu, and Jing Xu Li. "A Design of UART Serial Communication between the TMS320C6748 DSP and PC." Applied Mechanics and Materials 380-384 (August 2013): 3657–60. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3657.

Full text

Abstract:

The digital signal processor (DSP: Digital Signal Proceeding) are widely used in industrial, military, communications and the other fields, so the research and design work about DSP is one of the hot spots of scholars and research. Communication and data transfer between the DSP and peripherals is one of the DSP function in the process of using which is the basic but important. This paper introduces a TMS320C6748 DSP with PC serial communication method based on the UART module. The hardware connection and software programming were highlights description. Finally, this paper gives some key code about TMS320C6748 DSP and PC serial communication programming.

APA, Harvard, Vancouver, ISO, and other styles

27

CHIHARA, Kunihiro, Hiroshi TAKENO, and Kimisuke SHIRAE. "A DSP Chip-Based Processor for Ultrasonic Bloodflow Doppler Signals." Transactions of the Institute of Systems, Control and Information Engineers 1, no. 3 (1988): 100–107. http://dx.doi.org/10.5687/iscie.1.100.

Full text

APA, Harvard, Vancouver, ISO, and other styles

28

Cai, Wei-guang, Qing-dong Yao, and Peng Liu. "Early Detection of Instruction Data Dependence for RISC-DSP Processor." Journal of Electronics & Information Technology 32, no. 12 (January 24, 2011): 3046–50. http://dx.doi.org/10.3724/sp.j.1146.2010.00102.

Full text

APA, Harvard, Vancouver, ISO, and other styles

29

Anapagamini, S. A., and R. Rajavel. "Hardware implementation of ECG denoising system using TMS320C6713 DSP processor." International Journal of Biomedical Engineering and Technology 21, no. 1 (2016): 95. http://dx.doi.org/10.1504/ijbet.2016.076735.

Full text

APA, Harvard, Vancouver, ISO, and other styles

30

Patil, S., and E. W. Abel. "Real time continuous wavelet transform implementation on a DSP processor." Journal of Medical Engineering & Technology 33, no. 3 (January 2009): 223–31. http://dx.doi.org/10.1080/03091900802697867.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Fine, Bob, and Gerald McGuire. "Considerations for selecting a DSP processor (ADSP-2101 vs. TMS320C50)." Microprocessors and Microsystems 18, no. 6 (January 1994): 351–62. http://dx.doi.org/10.1016/0141-9331(94)90050-7.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

Miyazaki, Takashi, Takao Nishitani, Masato Edahiro, Ikuko Ono, and Kaoru Mitsuhashi. "DCT/IDCT processor for HDTV developed with dsp silicon compiler." Journal of VLSI signal processing systems for signal, image and video technology 5, no. 2-3 (April 1993): 151–58. http://dx.doi.org/10.1007/bf01581292.

Full text

APA, Harvard, Vancouver, ISO, and other styles

33

Sharma, P. K. "Design of a Communication System Using DSP Processor DSK C6713." Bioscience Biotechnology Research Communications 13, no. 15 (December 25, 2020): 185–88. http://dx.doi.org/10.21786/bbrc/13.15/30.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

Klilou, Abdessamad, and Assia Arsalane. "Parallel implementation of pulse compression method on a multi-core digital signal processor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 6 (December 1, 2020): 6541. http://dx.doi.org/10.11591/ijece.v10i6.pp6541-6548.

Full text

Abstract:

Pulse compression algorithm is widely used in radar applications. It requires a huge processing power in order to be executed in real time. Therefore, its processing must be distributed along multiple processing units. The present paper proposes a real time platform based on the multi-core digital signal processor (DSP) C6678 from Texas Instruments (TI). The objective of this paper is the optimization of the parallel implementation of pulse compression algorithm over the eight cores of the C6678 DSP. Two parallelization approaches were implemented. The first approach is based on the open multi processing (OpenMP) programming interface, which is a software interface that helps to execute different sections of a program on a multi core processor. The second approach is an optimized method that we have proposed in order to distribute the processing and to synchronize the eight cores of the C6678 DSP. The proposed method gives the best performance. Indeed, a parallel efficiency of 94% was obtained when the eight cores were activated.

APA, Harvard, Vancouver, ISO, and other styles

35

Coombs, Joseph, Rahul Prabhu, and Greg Peake. "Overcoming the Challenges of Porting OpenCV to TI's Embedded ARM + DSP Platforms." International Journal of Electrical Engineering & Education 49, no. 3 (July 2012): 260–74. http://dx.doi.org/10.7227/ijeee.49.3.6.

Full text

Abstract:

The growing performance and decreasing price of embedded processors are opening many doors, for both developers in the industry and in academia. However, the complexities of these systems can create serious developmental bottlenecks. Sophisticated software packages such as OpenCV can assist in both the functional development and educational aspects of these otherwise complex applications; such tools lend themselves very well to use by the academic community, in particular in providing examples of algorithm implementation. However the task of migrating this software to embedded platforms poses its own challenges. This paper will review how to mitigate some of these issues, including C++ implementation, memory constraints, floating-point support, and opportunities to maximise performance using vendor-optimised libraries and integrated accelerators or co-processors. Finally, we will introduce a new effort by Texas Instruments to optimise vision systems by running OpenCV on the C6000™ digital signal processor architecture. Benchmarks will show the advantage of using the DSP by comparing the performance of a DSP+ARM® system-on-chip (SoC) processor against an ARM-only device.

APA, Harvard, Vancouver, ISO, and other styles

36

Li, Peng, Yu Lu, Shen Li, and Hongxing Wei. "Realization of Embedded Multimedia System Based On Dual-Core Processor OMAP5910." International Journal of Computers Communications & Control 1, no. 4 (October 1, 2006): 85. http://dx.doi.org/10.15837/ijccc.2006.4.2310.

Full text

Abstract:

This paper focuses on the realization of a complete embedded system using the dual-core processor OMAP5910. Detailed description of how to compose the hardware system is presented with a description of the software system on our platform. Tasks communication between the two cores is realized using the DSP driver. The system bootloader and the DSP bootloader are described in detail. The implementation of the MPEG-4 video decoder has been realized on the presented system. Higher speed can be achieved and less power is needed for MPEG-4 video processing on the dual-core platform. This dual-core system can be applied to 3G wireless communication, robot control and vision systems.

APA, Harvard, Vancouver, ISO, and other styles

37

Liu, Yang, Yong Tie, Shun Na, and Dong Li. "Correlation Analyzer Project for Teaching Digital Signal Processing with MATLAB and DSP Processor." Applied Mechanics and Materials 263-266 (December 2012): 139–42. http://dx.doi.org/10.4028/www.scientific.net/amm.263-266.139.

Full text

Abstract:

Digital signal processing (DSP) has become one of key enabling technologies for communications, condition monitoring, multimedia computing, wireless networks and other areas requiring signal and information processing. With the rapid growth of applications of digital signal processing in the world, it has become necessary to introduce these concepts to graduates and undergraduates. Teaching of digital signal processing is carried out not only at the electrical and electronic engineering departments as the most traditional interested in this subject, but also others technical universities are carried out lectures and tutorials. In this paper, a digital signal processing development process is described. It starts from the conceptual algorithm design and computer simulation using MATLAB. After verification of the algorithm, a fixed-point C program is developed for a specific fixed-point DSP processor. This application covers most topics included in a DSP courses performing independent multiple simple experiments. The used methodology enables students and engineers to understand and develop complex fixed-point applications on hardware implementations.

APA, Harvard, Vancouver, ISO, and other styles

38

Wu, Jing Ran, Zhen Guo Sun, Qi Dong Ma, and Wen Zeng Zhang. "Embedded Attitude Estimation System for Quad-Rotor UAVs." Applied Mechanics and Materials 321-324 (June 2013): 528–31. http://dx.doi.org/10.4028/www.scientific.net/amm.321-324.528.

Full text

Abstract:

An embedded attitude estimation system is developed for the autonomous flight of Quad-Rotor UAVs. The system hardware is composed of a DSP processor and low-cost MEMS sensors including a 3-axis gyroscope and a 3-axis accelerometer. A Complementary Filter fused the advantages of the gyroscope and accelerometer is designed and embedded on the DSP processor to estimate the real-time attitude. Ground testing experiments show that the system could meet the accuracy and robustness requirements for the Quad-Rotor UAVs attitude estimation.

APA, Harvard, Vancouver, ISO, and other styles

39

Sankai, Yoshiyuki, Tetsuya Nii, and Shinichi Kariya. "Robot Objective Parallel Calculation and Real-time Control Using a Digital Signal Processor." Journal of Robotics and Mechatronics 10, no. 6 (December 20, 1998): 505–14. http://dx.doi.org/10.20965/jrm.1998.p0505.

Full text

Abstract:

We propose an objective parallel computation/control method, developing the following to solve conventional problems and installing a controller on a robot with links decomposed to objects: 1) parallel calculation for twodimensional link dynamics, 2) downsizing of a high-speed controller using a digital signal processor (DSP), 3) a common robot control library, and 4) parallel calculation control of a multilink system. Evaluating parallel computation/control using the DSP, we verified fine compact controller efficiency in real-time control of multi-DOF systems and control performance comparing overall system control by linear quadratic optimal control.

APA, Harvard, Vancouver, ISO, and other styles

40

Benyettou, Loutfi. "Performance Evaluation of A Multi-Sensor System Using Fixed Point DSP For Water Leak Detection." Indonesian Journal of Electrical Engineering and Computer Science 4, no. 3 (December 18, 2016): 555. http://dx.doi.org/10.11591/ijeecs.v4.i3.pp555-560.

Full text

Abstract:

<p>DSPs (Digital Processors Signal) are processors specifically designed for digital signals processing. The fixed-point DSPs are processors operating in integer arithmetic whose characteristics are often limited but not less powerful with respect to floating-point DSPs. In this article, it is a question of checking the performances provided by the fixed-point DSP, the TMS320C541. This one is used in a detection and remote locating system ensuring a control of water leaks on the pipes. The acoustic correlation technique used as means of detection of these leaks represents the key element of the suggested system. In fact the DSP which deals the acquisition and processing of the signals emanating from the leaks. The had aim consists in initially to confirm the choice of such a processor for such an application. A simulation study to evaluate its performances as regards of computational accuracy and computing speed is carried out. A floating-point DSP of last generation, more accurate and faster, taken as reference element, is used for this purpose.</p>

APA, Harvard, Vancouver, ISO, and other styles

41

Zhang, Zeng Nian, Zun Yi Wang, Mian Mian Chen, and Jiong Shi. "Intelligent Transportation Video Detecting System Based on DSP." Applied Mechanics and Materials 701-702 (December 2014): 498–504. http://dx.doi.org/10.4028/www.scientific.net/amm.701-702.498.

Full text

Abstract:

This paper proposes a method of realizing a moving vehicle video detecting system based on DSP processor, and describes the system's hardware architecture and software design in detail. Based on the characteristic of dual-core of DM6437 processor, the methods of communication protocol between ARM and DSP, as well as the double-buffer switching method are presented. Background modeling is made on the traffic video data from DM6437 via difference accumulation. Background subtraction is used to detect vehicle movement areas. With the adoption of algorithms such as Otsu, morphological filtering and region growing, the whole system is finally realized on the DM6446 hardware platform. Experimental results show that the system achieves good performance on moving vehicle detection.

APA, Harvard, Vancouver, ISO, and other styles

42

Rakanovic, Damjan M., Vuk Vranjkovic, and Rastislav J. R. Struharik. "Argus CNN Accelerator Based on Kernel Clustering and Resource-Aware Pruning." Elektronika ir Elektrotechnika 27, no. 3 (June 28, 2021): 57–70. http://dx.doi.org/10.5755/j02.eie.28922.

Full text

Abstract:

Paper proposes a two-step Convolutional Neural Network (CNN) pruning algorithm and resource-efficient Field-programmable gate array (FPGA) CNN accelerator named “Argus”. The proposed CNN pruning algorithm first combines similar kernels into clusters, which are then pruned using the same regular pruning pattern. The pruning algorithm is carefully tailored for FPGAs, considering their resource characteristics. Regular sparsity results in high Multiply-accumulate (MAC) efficiency, reducing the amount of logic required to balance workloads among different MAC units. As a result, the Argus accelerator requires about 170 Look-up tables (LUTs) per Digital Signal Processor (DSP) block. This number is close to the average LUT/DPS ratio for various FPGA families, enabling balanced resource utilization when implementing Argus. Benchmarks conducted using Xilinx Zynq Ultrascale + Multi-Processor System-on-Chip (MPSoC) indicate that Argus is achieving up to 25 times higher frames per second than NullHop, 2 and 2.5 times higher than NEURAghe and Snowflake, respectively, and 2 times higher than NVDLA. Argus shows comparable performance to MIT’s Eyeriss v2 and Caffeine, requiring up to 3 times less memory bandwidth and utilizing 4 times fewer DSP blocks, respectively. Besides the absolute performance, Argus has at least 1.3 and 2 times better GOP/s/DSP and GOP/s/Block-RAM (BRAM) ratios, while being competitive in terms of GOP/s/LUT, compared to some of the state-of-the-art solutions.

APA, Harvard, Vancouver, ISO, and other styles

43

Chen, Lin, Hai Hong Pan, and Han Ling Mao. "Real-Time Solution of Inverse Kinematics for 6R Robot Manipulators Using Digital Signal Processor." Applied Mechanics and Materials 423-426 (September 2013): 2788–91. http://dx.doi.org/10.4028/www.scientific.net/amm.423-426.2788.

Full text

Abstract:

It is a challenge to get real-time solutions for the inverse kinematics problem of 6R robot. In this study, a digital signal processor (DSP) was adopted as the central processor for the algorithm inverse kinematics. Based on it, the robot end-effector carried out the interpolation of point-to-point spatial straight line, and the inverse kinematics solving of 6R robot manipulators end-effector was achieved. The deflection variations of the 6 joints were acquired during the interpolation in a Cartesian coordinate. The results show that inverse Kinematics solution for each interpolation point only cost 0.06588 millisecond using DSP 6711. This hard structure can ensure the real-time performance of control for robot and content the real-time control performance expected of industrial manipulators.

APA, Harvard, Vancouver, ISO, and other styles

44

Wei, Chi Pin, Zhao Lin Li, Hao Liu, and Zhi Xiang Chen. "Design of a Random Test Platform for DSP Serials Used in Embedded Systems." Advanced Materials Research 267 (June 2011): 98–103. http://dx.doi.org/10.4028/www.scientific.net/amr.267.98.

Full text

Abstract:

Embedded systems with digital signal processor (DSP) become more and more popular for the increasing requirement of supercomputing these days. Efficient development of DSP serials used in embedded systems shortens the embedded system R&D cycle. Functional verification is one of the most complex and expensive tasks during DSP serials design process. A random test platform which is urged for DSP serials verification is proposed in this paper. The platform can automatically generate the random test program. The platform also realized the recording and checking of simulation results, which make the verification more effective. In order to improve the efficiency of DSP verification, a testing experience library has been generated through the testing procedure. This platform can be transplanted for different DSP models easily by updating few modules. According to the verification results, this platform has satisfactory coverage of DSP models.

APA, Harvard, Vancouver, ISO, and other styles

45

Nandan, Durgesh. "An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor." Traitement du Signal 37, no. 1 (February 29, 2020): 77–83. http://dx.doi.org/10.18280/ts.370110.

Full text

APA, Harvard, Vancouver, ISO, and other styles

46

Hu, Wen Bin. "The Design of Embedded Video Monitoring System Based on DSP Processor." Advanced Materials Research 989-994 (July 2014): 3003–6. http://dx.doi.org/10.4028/www.scientific.net/amr.989-994.3003.

Full text

Abstract:

This paper designs a embedded video monitoring system based on ARM processor Ep9315 and TMS320DM642, and using embedded Linux operating system. In the system, video capturing module uses the video decoder TW2814. In order to capture better data, the control of TW2814 is needed. Through the imitation of I2C bus, the driver provide the application with the function of the setting of capturing parameters such as hue, color saturation, contrast and brightness, and the check of video losing.

APA, Harvard, Vancouver, ISO, and other styles

47

Giridhar, J., and K. M. M. Prabhu. "Erratum to “Implementation of MTD–WVD on a TMS320C30 DSP processor”." Microprocessors and Microsystems 22, no. 9 (March 1999): 573. http://dx.doi.org/10.1016/s0141-9331(98)00113-6.

Full text

APA, Harvard, Vancouver, ISO, and other styles

48

Priya, K. Hari, and Chinthakindi Roja Sree. "Design of 32 Bit Low Power RISC Processor for DSP Applications." International Journal of Engineering Trends and Technology 34, no. 1 (April 25, 2016): 5–14. http://dx.doi.org/10.14445/22315381/ijett-v34p202.

Full text

APA, Harvard, Vancouver, ISO, and other styles

49

Battaiotto, P. E., R. J. Mantz, and P. F. Puleston. "A Wind Turbine Emulator Based on a Dual DSP Processor System." IFAC Proceedings Volumes 28, no. 19 (September 1995): 249–54. http://dx.doi.org/10.1016/s1474-6670(17)45088-9.

Full text

APA, Harvard, Vancouver, ISO, and other styles

50

Hagiwara, Yoshimune, Akira Kikuchi, and Koichi Iida. "Special edition Digital signal processor. System build-up method by DSP." Journal of the Institute of Television Engineers of Japan 41, no. 3 (1987): 225–33. http://dx.doi.org/10.3169/itej1978.41.225.

Full text

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!