Academic literature on the topic 'Duty Cycle Corrector'
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Journal articles on the topic "Duty Cycle Corrector"
Lin, Chien Yu, and Heng Shou Hsu. "Design of a High Frequency Duty-Cycle Corrector within 20%–80% Correction Range." International Journal of Information and Electronics Engineering 9, no. 2 (June 2019): 59–62. http://dx.doi.org/10.18178/ijiee.2019.9.2.706.
Full textKao, Shao-Ku, and Yong-De You. "Clock buffer with duty cycle corrector." Microelectronics Journal 42, no. 5 (May 2011): 740–44. http://dx.doi.org/10.1016/j.mejo.2011.02.001.
Full textKao, Shao-Ku. "Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency." Electronics 10, no. 1 (January 3, 2021): 71. http://dx.doi.org/10.3390/electronics10010071.
Full textHuang, Hong-Yi, and Chia-Ming Liang. "Frequency multiplier using 50% duty cycle corrector." IEICE Electronics Express 5, no. 22 (2008): 990–94. http://dx.doi.org/10.1587/elex.5.990.
Full textWu, J. H., J. H. Gu, L. Z. Zhang, and M. Zhang. "Full-MOSFET mixed-mode duty cycle corrector." Electronics Letters 47, no. 19 (2011): 1067. http://dx.doi.org/10.1049/el.2011.1660.
Full textPatil, Meghana, Kiran Bailey, and Rajanikanth Anuvanahally. "Duty Cycle Corrector Using Pulse Width Modulation." International Journal of VLSI Design & Communication Systems 10, no. 03 (June 29, 2019): 01–17. http://dx.doi.org/10.5121/vlsic.2019.10301.
Full textJeong, Chan-Hui, Ammar Abdullah, Young-Jae Min, In-Chul Hwang, and Soo-Won Kim. "All-Digital Duty-Cycle Corrector With a Wide Duty Correction Range for DRAM Applications." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24, no. 1 (January 2016): 363–67. http://dx.doi.org/10.1109/tvlsi.2015.2394486.
Full textKao, Shao-Ku, and Shen-Iuan Liu. "All-Digital Fast-Locked Synchronous Duty-Cycle Corrector." IEEE Transactions on Circuits and Systems II: Express Briefs 53, no. 12 (December 2006): 1363–67. http://dx.doi.org/10.1109/tcsii.2006.885396.
Full textJovanovic, Goran, and Mile Stojcev. "Pulse width control loop as a duty cycle corrector." Serbian Journal of Electrical Engineering 1, no. 2 (2004): 215–26. http://dx.doi.org/10.2298/sjee0402215j.
Full textKao, Shao-Ku. "A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock." Electronics 10, no. 7 (April 5, 2021): 860. http://dx.doi.org/10.3390/electronics10070860.
Full textDissertations / Theses on the topic "Duty Cycle Corrector"
Breisel, Jonas. "Evaluering av en Klockkorrigerare av klockpulsbredd." Thesis, Linköping University, Department of Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15791.
Full textDet här examensarbetet presenterar en evaluering av en Klockkorrigerare av klockpulsbredd. Den består främst av en korrigerare av klockpulsbredd (Duty Cycle Corrector DCC) och även en fördröjningslåst loop (Delayed Locked Loop DLL). Det finns många olika korrigerare av klockpulsbredden designade förut, de två populäraste arkitekturerna då har varit enkel eller dubbel återkopplings loop. Den huvudsakliga skillnaden mellan dem är att enkel återkopplings loop använder sig av en öppen loop medan den dubbla varianten istället har en stängd loop. I det här projektet kommer en ny arkitektur att presenteras. Konceptet i den nya designen är att dela upp korrigeraren av klockpulsbredden i två delar, en korrigerare och en detektor. Detektorn får utsignalen från den fördröjningslåsta loopen som insignal och talar om för korrigeraren via två utsignaler ifall signalen behöver justeras. Detektorn är uppdelad i två likadana fördröjningselement, som båda är klockade av utsignalen och dess invers från den fördröjningslåsande loopen, fast i omvänd ordning. Det här gör det möjligt att avgöra om klockpulsbredden av signalen är över eller under 50 %. Om så är fallet kommer den att justeras av korrigeraren för att sedan skickas som insignal till den fördröjningslåsande loopen.
Abstraktionsnivån för det här projektet har varit systemnivå, detta för att kunna vara riktigt säker på att arkitekturen verkligen fungerar innan ett riktigt chip tillverkas. Tips på framtida projekt är att gå vidare till schemanivå för att slutligen göra en implementering och mätningar på ett riktigt chip av den här Klockkorrigeraren av klockpulsbredd när det är känt att idén fungerar.
Morais, Douglas Carvalho. "Retificador trifásico boost semi-controlado, com elevado fator de potência e controle por razão cíclica variável." Universidade Estadual Paulista (UNESP), 2018. http://hdl.handle.net/11449/153785.
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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
Este trabalho tem como objetivo a proposição de um retificador trifásico boost semi-controlado, com correção ativa do fator de potência, que faça uso de técnicas de controle de razão cíclica variável, visando reduzir o conteúdo harmônico de corrente em baixa frequência. O conversor proposto opera em modo de condução descontínua, desta forma, a corrente de entrada segue uma envoltória senoidal. Além disso, devido ao modo de condução, o conversor apresenta a entrada em condução da chave com corrente nula, diminuindo assim, as perdas por chaveamento. Inicialmente, são apresentados, estudos teóricos da topologia em questão e, por meio de gráficos e equações, verifica-se a distorção harmônica imposta devida à operação com razão cíclica constante. Funções que permitam a variação permanente da razão cíclica, durante um ciclo da rede, serão apresentadas. Tais funções possuem o intuito de minimizar a distorção harmônica da corrente de entrada, com foco principal na 5ª componente harmônica. Resultados de simulação demonstram eficácia das técnicas de controle por razão cíclica variável e apontam redução no conteúdo harmônico de corrente. Resultados experimentais demonstram conteúdo harmônico de corrente em torno de 18% para operação do conversor com razão cíclica constante. A utilização de razão cíclica variável proporciona uma redução no conteúdo harmônico de corrente para 13%, resultando em um aumento do fator de potência.
This work aims propose a three-phase rectifier boost half-controlled, with power factor correction, that makes use variable duty cycle control techniques, in order to reduce the harmonic content of current in low frequency. The proposed converter operates in a discontinuous current conduction mode, this way, the input current is naturally corrected. Moreover, due to the conduction mode, the converter presents entry in conduction of switch with null current, thus decreasing, the losses by switching. Initially, are presented theoretical studies of the topology in question and, through of graphs and equations, the harmonic distortion imposed by operation due constant duty cycle is verified. Functions that allow permanently the variation of duty cycle, during a network cycle, are presented. These functions have as main objective minimize the harmonic distortion in the input current, with focus in the 5th harmonic component. Simulation results demonstrate efficacy of techniques by variable duty cycle control and indicate a reducing of harmonic content of current. Experimental results demonstrate a reducing around 18% for operation with constant duty cycle. The use of variable duty cycle provides a reducing around 13%, resulting in an increase of the power factor.
Han-Lin, Chen, and 陳翰霖. "Duty Cycle Corrector Circuit Design." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/22495195702590410329.
Full text聖約翰科技大學
電子工程系碩士班
102
In recent years as the operation of electrical circuit towards higher speed it has the request for generating higher accuracy of circuit timing signals. However the timing signal will suffer the operation period offset problem due to the complexity of the electrical circuits and the mismatch among transistors; consequently it becomes vitally important in the design of circuit to correct or improve the operation period of the circuit. In this paper we propose to implement frequency divider and frequency doubling operations to design a circuit to correct and improve the circuit operation period. The designed circuit can solve the operation period offset problem when the timing signal passes through a series of clock buffers. We use 0.18um 1P6M CMOS process to simulate and layout the circuit; the circuit operating frequency is from 150MHz to 2GHz. When the duty-cycle of an input clock signal is from 25% to 75%, the resulted circuit can correct it into an output clock signal with duty-cycle in the range 50% 3%. When the working frequency is 2GHz the power consumption is 1.62mW and the layout of core circuit area is 0.213* 0.216 mm2.
Liang, Chia-Ming, and 梁家銘. "High-Bandwidth Wide-Range Duty Cycle Corrector." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/90504269859090077102.
Full text輔仁大學
電子工程學系
95
This work presents singled-ended and differential wide input range 50% duty cycle corrector with high bandwidth and low jitter performance. The Singled-ended duty cycle corrector adopts ratioless control stage and gain-boosting charge pump to increase the performance. Gain-boosting charge pump increases the stability of the closed-loop performance and decreases jitter and output duty error as well. The Differential duty cycle corrector uses a second order differential low-pass filter to increase the stability of the closed loop. A combined charge pump is proposed to stabilize the current charge and current sink. A simplified low-voltage amplifier increases the input common-mode range and bandwidth. Both architectures are implemented in a 0.18μm CMOS process. Both of the proposed duty cycle corrector achieves 50% output duty and operates from 20-MHz to 2.5-GHz with wide input duty cycle range and low jitter performance.
Chen, Shi-Wei, and 陳世崴. "Duty Cycle Corrector Based on Pulse Shrinking/Stretching Mechanism." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/64732985219389742835.
Full text國立臺灣科技大學
電子工程系
95
The duty cycle correctors (DCCs) are widely used to adjust the clock duty cycle to 50% for DDR (double data rate)-SDRAM, double-sampling ADC, DLL (delay locked loop) and PLL (phase locked loop), where both clock rising and falling edges are used for operation. There are two major categories, digital and analog, for DCC realization in literatures. The digital DCCs can be further classified into the feedback type and the non-feedback type. The analog DCCs are usually implemented as feedback type to get better duty cycle accuracy at the expense of long locking time. In this thesis, a simple analog DCC with negative feedback is proposed. The pulse shrinking/stretching mechanism is utilized to achieve the duty cycle correction. Neither the complicated circuit in digital DCCs nor the charge pump in analog ones is required. A duty cycle corrector based on pulse shrinking/stretching mechanism is presented. The proposed DCC has been fabricated in a TSMC 0.35μm standard CMOS process. An input duty cycle range of 30%~70% is achieved. The duty cycle error is between -1.0% to +1% for the widest frequency operation range of 3MHz~660MHz ever fulfilled which makes the circuit best suited for ultra wide band applications. The chip area is merely 0.3 × 0.2 mm2 and the power consumption is 1.1mW at 550 MHz.
Chu, Wen-Yu, and 朱汶鈺. "A Fast-Locking Duty Cycle Corrector With Deskew Capability." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/26144604445639018225.
Full text國立雲林科技大學
電機工程系碩士班
100
In this paper, a fast-locking all-digital duty cycle corrector has simple architecture is proposed. It is using the feature of two Half Delay Line (HDL) which is a delay of HDL is equal to a half of input clock period for correcting the output clock duty cycle to 50%. And then, it could set the other Half Delay Line to decrease the phase error between input and output clock. In order to load the controlled code of Successive Approximation Register to the Synchronous Adder easily, a Hybrid-SAR was proposed combining the Successive Approximation Register with Up/Down Counter to reach to simple architecture without extra circuits and small area. A test chip was fabricated in TSMC 0.18-μm 1P6M technology. The circuit can operate at the input clock from 150 to 540 MHz, and tolerate the input duty cycle variation from 15% to 85% to generate 50% output clock with the skew within -3.21ps ~ 9.87ps. It adopts Synchronous Adder to reach close-loop controlled as the system has been locked.
陳律昂. "The Design of High Speed Duty Cycle Corrector Circuitry." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/8awdfc.
Full text逢甲大學
電子工程學系
105
This paper presents a high speed duty cycle corrector circuit. The propose circuit is designed in 0.18- m CMOS process and the simulation result to prove the extant of improvement. The duty cycle of the input clock can accept between 10% to 90%, corrector the duty cycle of input clock to 50%, error is less than 1%. The propose circuit operation frequency at 200MHz to 1.4GHz.
CHEN, TSUNG-TZE, and 陳聰澤. "Design of High-Speed All-Digital Duty Cycle Corrector." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/jw628u.
Full textHsueh, Sheng Hung, and 薛聖弘. "A Synchronous Fast-Locked All-Digital Duty Cycle Corrector." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/54575679034355854436.
Full text長庚大學
電機工程學系
100
The primary function of the duty cycle corrector(DCC) is to correct the duty cycle to 50% from unbalanced duty cycle. Many applications such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Double-Sampling Analog-to-Digital Converters(Double-Sampling ADC), and Clock and Data Recovery (CDR),both rising and falling edges of the clock are utilized to double the data rate. In these applications, the duty cycle corrector plays an important role in maintaining the duty cycle at 50%. This paper proposed a synchronous 50% all-digital duty-cycle corrector (ADDCC). The proposed ADDCC has many features, including fast-locked, a wider acceptable duty-cycle range of input clock, synchronizing output phase with input phase. The proposed ADDCC is implemented in a 0.18-μmCMOS process. The circuit can operate from 500 to 900 MHz, and accommodates a wide range of input duty cycle ranging from 15% to 85%. The duty-cycle error of the output signal is less than 2.7%. The RMS and peak-to-peak jitters are 1.9 ps and 14.7 ps at 900MHz, respectively. The circuit operated from a 1.8-V supply voltage, the circuit dissipates 7.3 mA at 900MHz. This fully-integrated DCC chip area is 0.55 mm × 0.7 mm, the core area is 0.2 mm × 0.25 mm.
Lai, Juan-Shan, and 賴濬紳. "Highly Accurate Duty Cycle Corrector Based on Vernier Principle." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/70934769332009465178.
Full text國立臺灣科技大學
電子工程系
96
The duty cycle corrector (DCC) is widely adopted by DDR (double data rate)-SDRAM, half-rate CDR (clock data recovery), and Double-Sampling ADC. The clock siognlals generated DLL (delay locked loop) and PLL (phase locked loop) usually face with asymmetric duty cycle problems and must be corrected by duty cycle correctors. According to the literatures, the implemention of DCC can be divided into two catagories: the digital type and the analog type. The digital DCCs adopt non-feedback control to gain faster locking speed at the expense of less accuracy. On the contrary, the analog DCCs utilize feedback control to get better accuracy but longer locking time. To gain the advantages of both types, a mixed-type feedback DCC based on vernier principle is proposed in this thesis to achieve extremely high accuracy. With mixed-type operation, it needs only 10 clock cycles for locking, which is much less than those of the conventional analog versions. Furthermore, the effective resolution of the DCC is made to be the difference of two delay cells and the accuracy is substantially improved from those of the conventional digital ones. The proposed circuit has been fabricated in a TSMC 0.18-μm CMOS technology. The operation frequency range and duty-cycle correctable range are 250MHz ~ 1GHz and 40% ~ 60% respectively. The measured error is proven to be merely -0.86%~+0.51%. The chip area is 0.668 × 0.593mm2 only and the power consumption is 16.8mW at 800 MHz.
Book chapters on the topic "Duty Cycle Corrector"
Padiya, S. D., and V. S. Gulhane. "Analysis of Bluetooth Versions (4.0, 4.2, 5, 5.1, and 5.2) for IoT Applications." In Advances in Wireless Technologies and Telecommunication, 153–78. IGI Global, 2022. http://dx.doi.org/10.4018/978-1-7998-6988-7.ch010.
Full textConference papers on the topic "Duty Cycle Corrector"
Hong-Yi Huang, Chia-Ming Liang, and Shi-Jia Sun. "Low-power 50% duty cycle corrector." In 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008. IEEE, 2008. http://dx.doi.org/10.1109/iscas.2008.4541929.
Full textKao, Shao-Ku, and Yong-De You. "Clock buffer with duty cycle corrector." In 2010 IEEE International SOC Conference (SOCC). IEEE, 2010. http://dx.doi.org/10.1109/socc.2010.5784648.
Full textChen, Bo-jiun, Shao-ku Kao, and Shen-juan Liu. "An All-Digital Duty Cycle Corrector." In 2006 International Symposium on VLSI Design, Automation and Test. IEEE, 2006. http://dx.doi.org/10.1109/vdat.2006.258158.
Full textJaiswal, Ashok, Yuan Fang, Kashif Nawaz, and Klaus Hofmann. "A wide range programmable duty cycle corrector." In 2013 IEEE 26th International SoC Conference (SOCC). IEEE, 2013. http://dx.doi.org/10.1109/socc.2013.6749686.
Full textBabazadeh, Hadiseh, Arash Esmaili, Khayrollah Hadidi, and Abdollah Khoei. "A wide-range programmable duty cycle corrector (DCC)." In 2013 21st Iranian Conference on Electrical Engineering (ICEE). IEEE, 2013. http://dx.doi.org/10.1109/iraniancee.2013.6599655.
Full textLin, Chien Yu, and Heng Shou Hsu. "Design of A 0.8GHz-3GHz Duty-Cycle Corrector With a 20%-80% Input Duty Cycle." In 2019 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW). IEEE, 2019. http://dx.doi.org/10.1109/icce-tw46550.2019.8991833.
Full textSim, Jincheol, Hyunsu Park, Youngwook Kwon, Seongcheol Kim, and Chulwoo Kim. "A 1-3.2 GHz 0.6 mW/GHz Duty-Cycle-Corrector Using Bangbang Duty-Cyle-Detector." In 2021 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2021. http://dx.doi.org/10.1109/iscas51556.2021.9401792.
Full textZeng, Xianjun, Rong Ji, Shizhen Huang, Liang Chen, Gang Luo, and Junfeng Zhang. "A Novel Clock Duty-Cycle Corrector of DSP Systems." In 2008 Congress on Image and Signal Processing. IEEE, 2008. http://dx.doi.org/10.1109/cisp.2008.706.
Full textJung, Eun-Young, and Won-Young Lee. "A Fast Locking Duty Cycle Corrector with High Accuracy." In 2020 International SoC Design Conference (ISOCC). IEEE, 2020. http://dx.doi.org/10.1109/isocc50952.2020.9332963.
Full textPrakash S.R., Jaya, and Sujatha S. Hiremath. "Dual loop clock duty cycle corrector for high speed serial interface." In 2017 International Conference On Smart Technologies For Smart Nation (SmartTechCon). IEEE, 2017. http://dx.doi.org/10.1109/smarttechcon.2017.8358509.
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