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1
Breisel, Jonas. "Evaluering av en Klockkorrigerare av klockpulsbredd." Thesis, Linköping University, Department of Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15791.
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Det här examensarbetet presenterar en evaluering av en Klockkorrigerare av klockpulsbredd. Den består främst av en korrigerare av klockpulsbredd (Duty Cycle Corrector DCC) och även en fördröjningslåst loop (Delayed Locked Loop DLL). Det finns många olika korrigerare av klockpulsbredden designade förut, de två populäraste arkitekturerna då har varit enkel eller dubbel återkopplings loop. Den huvudsakliga skillnaden mellan dem är att enkel återkopplings loop använder sig av en öppen loop medan den dubbla varianten istället har en stängd loop. I det här projektet kommer en ny arkitektur att presenteras. Konceptet i den nya designen är att dela upp korrigeraren av klockpulsbredden i två delar, en korrigerare och en detektor. Detektorn får utsignalen från den fördröjningslåsta loopen som insignal och talar om för korrigeraren via två utsignaler ifall signalen behöver justeras. Detektorn är uppdelad i två likadana fördröjningselement, som båda är klockade av utsignalen och dess invers från den fördröjningslåsande loopen, fast i omvänd ordning. Det här gör det möjligt att avgöra om klockpulsbredden av signalen är över eller under 50 %. Om så är fallet kommer den att justeras av korrigeraren för att sedan skickas som insignal till den fördröjningslåsande loopen.
Abstraktionsnivån för det här projektet har varit systemnivå, detta för att kunna vara riktigt säker på att arkitekturen verkligen fungerar innan ett riktigt chip tillverkas. Tips på framtida projekt är att gå vidare till schemanivå för att slutligen göra en implementering och mätningar på ett riktigt chip av den här Klockkorrigeraren av klockpulsbredd när det är känt att idén fungerar.
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Morais, Douglas Carvalho. "Retificador trifásico boost semi-controlado, com elevado fator de potência e controle por razão cíclica variável." Universidade Estadual Paulista (UNESP), 2018. http://hdl.handle.net/11449/153785.
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RETIFICADOR TRIFÁSICO BOOST SEM PONTE DE DIODOS, COM ELEVADO FATOR DE POTÊNCIA E CONTROLE POR RAZÃO CÍCLICA VARIÁVEL.pdf: 3578931 bytes, checksum: 59462e5e8af8153b4c38efb1636c59de (MD5)Approved for entry into archive by Cristina Alexandra de Godoy null (cristina@adm.feis.unesp.br) on 2018-04-27T12:43:58Z (GMT) No. of bitstreams: 1 morais_dc_me_ilha.pdf: 3578931 bytes, checksum: 59462e5e8af8153b4c38efb1636c59de (MD5)
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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
Este trabalho tem como objetivo a proposição de um retificador trifásico boost semi-controlado, com correção ativa do fator de potência, que faça uso de técnicas de controle de razão cíclica variável, visando reduzir o conteúdo harmônico de corrente em baixa frequência. O conversor proposto opera em modo de condução descontínua, desta forma, a corrente de entrada segue uma envoltória senoidal. Além disso, devido ao modo de condução, o conversor apresenta a entrada em condução da chave com corrente nula, diminuindo assim, as perdas por chaveamento. Inicialmente, são apresentados, estudos teóricos da topologia em questão e, por meio de gráficos e equações, verifica-se a distorção harmônica imposta devida à operação com razão cíclica constante. Funções que permitam a variação permanente da razão cíclica, durante um ciclo da rede, serão apresentadas. Tais funções possuem o intuito de minimizar a distorção harmônica da corrente de entrada, com foco principal na 5ª componente harmônica. Resultados de simulação demonstram eficácia das técnicas de controle por razão cíclica variável e apontam redução no conteúdo harmônico de corrente. Resultados experimentais demonstram conteúdo harmônico de corrente em torno de 18% para operação do conversor com razão cíclica constante. A utilização de razão cíclica variável proporciona uma redução no conteúdo harmônico de corrente para 13%, resultando em um aumento do fator de potência.
This work aims propose a three-phase rectifier boost half-controlled, with power factor correction, that makes use variable duty cycle control techniques, in order to reduce the harmonic content of current in low frequency. The proposed converter operates in a discontinuous current conduction mode, this way, the input current is naturally corrected. Moreover, due to the conduction mode, the converter presents entry in conduction of switch with null current, thus decreasing, the losses by switching. Initially, are presented theoretical studies of the topology in question and, through of graphs and equations, the harmonic distortion imposed by operation due constant duty cycle is verified. Functions that allow permanently the variation of duty cycle, during a network cycle, are presented. These functions have as main objective minimize the harmonic distortion in the input current, with focus in the 5th harmonic component. Simulation results demonstrate efficacy of techniques by variable duty cycle control and indicate a reducing of harmonic content of current. Experimental results demonstrate a reducing around 18% for operation with constant duty cycle. The use of variable duty cycle provides a reducing around 13%, resulting in an increase of the power factor.
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Han-Lin, Chen, and 陳翰霖. "Duty Cycle Corrector Circuit Design." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/22495195702590410329.
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碩士聖約翰科技大學
電子工程系碩士班
102
In recent years as the operation of electrical circuit towards higher speed it has the request for generating higher accuracy of circuit timing signals. However the timing signal will suffer the operation period offset problem due to the complexity of the electrical circuits and the mismatch among transistors; consequently it becomes vitally important in the design of circuit to correct or improve the operation period of the circuit. In this paper we propose to implement frequency divider and frequency doubling operations to design a circuit to correct and improve the circuit operation period. The designed circuit can solve the operation period offset problem when the timing signal passes through a series of clock buffers. We use 0.18um 1P6M CMOS process to simulate and layout the circuit; the circuit operating frequency is from 150MHz to 2GHz. When the duty-cycle of an input clock signal is from 25% to 75%, the resulted circuit can correct it into an output clock signal with duty-cycle in the range 50% 3%. When the working frequency is 2GHz the power consumption is 1.62mW and the layout of core circuit area is 0.213* 0.216 mm2.
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Liang, Chia-Ming, and 梁家銘. "High-Bandwidth Wide-Range Duty Cycle Corrector." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/90504269859090077102.
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碩士輔仁大學
電子工程學系
95
This work presents singled-ended and differential wide input range 50% duty cycle corrector with high bandwidth and low jitter performance. The Singled-ended duty cycle corrector adopts ratioless control stage and gain-boosting charge pump to increase the performance. Gain-boosting charge pump increases the stability of the closed-loop performance and decreases jitter and output duty error as well. The Differential duty cycle corrector uses a second order differential low-pass filter to increase the stability of the closed loop. A combined charge pump is proposed to stabilize the current charge and current sink. A simplified low-voltage amplifier increases the input common-mode range and bandwidth. Both architectures are implemented in a 0.18μm CMOS process. Both of the proposed duty cycle corrector achieves 50% output duty and operates from 20-MHz to 2.5-GHz with wide input duty cycle range and low jitter performance.
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Chen, Shi-Wei, and 陳世崴. "Duty Cycle Corrector Based on Pulse Shrinking/Stretching Mechanism." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/64732985219389742835.
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碩士國立臺灣科技大學
電子工程系
95
The duty cycle correctors (DCCs) are widely used to adjust the clock duty cycle to 50% for DDR (double data rate)-SDRAM, double-sampling ADC, DLL (delay locked loop) and PLL (phase locked loop), where both clock rising and falling edges are used for operation. There are two major categories, digital and analog, for DCC realization in literatures. The digital DCCs can be further classified into the feedback type and the non-feedback type. The analog DCCs are usually implemented as feedback type to get better duty cycle accuracy at the expense of long locking time. In this thesis, a simple analog DCC with negative feedback is proposed. The pulse shrinking/stretching mechanism is utilized to achieve the duty cycle correction. Neither the complicated circuit in digital DCCs nor the charge pump in analog ones is required. A duty cycle corrector based on pulse shrinking/stretching mechanism is presented. The proposed DCC has been fabricated in a TSMC 0.35μm standard CMOS process. An input duty cycle range of 30%~70% is achieved. The duty cycle error is between -1.0% to +1% for the widest frequency operation range of 3MHz~660MHz ever fulfilled which makes the circuit best suited for ultra wide band applications. The chip area is merely 0.3 × 0.2 mm2 and the power consumption is 1.1mW at 550 MHz.
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Chu, Wen-Yu, and 朱汶鈺. "A Fast-Locking Duty Cycle Corrector With Deskew Capability." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/26144604445639018225.
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碩士國立雲林科技大學
電機工程系碩士班
100
In this paper, a fast-locking all-digital duty cycle corrector has simple architecture is proposed. It is using the feature of two Half Delay Line (HDL) which is a delay of HDL is equal to a half of input clock period for correcting the output clock duty cycle to 50%. And then, it could set the other Half Delay Line to decrease the phase error between input and output clock. In order to load the controlled code of Successive Approximation Register to the Synchronous Adder easily, a Hybrid-SAR was proposed combining the Successive Approximation Register with Up/Down Counter to reach to simple architecture without extra circuits and small area. A test chip was fabricated in TSMC 0.18-μm 1P6M technology. The circuit can operate at the input clock from 150 to 540 MHz, and tolerate the input duty cycle variation from 15% to 85% to generate 50% output clock with the skew within -3.21ps ~ 9.87ps. It adopts Synchronous Adder to reach close-loop controlled as the system has been locked.
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陳律昂. "The Design of High Speed Duty Cycle Corrector Circuitry." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/8awdfc.
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碩士逢甲大學
電子工程學系
105
This paper presents a high speed duty cycle corrector circuit. The propose circuit is designed in 0.18- m CMOS process and the simulation result to prove the extant of improvement. The duty cycle of the input clock can accept between 10% to 90%, corrector the duty cycle of input clock to 50%, error is less than 1%. The propose circuit operation frequency at 200MHz to 1.4GHz.
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CHEN, TSUNG-TZE, and 陳聰澤. "Design of High-Speed All-Digital Duty Cycle Corrector." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/jw628u.
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Hsueh, Sheng Hung, and 薛聖弘. "A Synchronous Fast-Locked All-Digital Duty Cycle Corrector." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/54575679034355854436.
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碩士長庚大學
電機工程學系
100
The primary function of the duty cycle corrector(DCC) is to correct the duty cycle to 50% from unbalanced duty cycle. Many applications such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Double-Sampling Analog-to-Digital Converters(Double-Sampling ADC), and Clock and Data Recovery (CDR),both rising and falling edges of the clock are utilized to double the data rate. In these applications, the duty cycle corrector plays an important role in maintaining the duty cycle at 50%. This paper proposed a synchronous 50% all-digital duty-cycle corrector (ADDCC). The proposed ADDCC has many features, including fast-locked, a wider acceptable duty-cycle range of input clock, synchronizing output phase with input phase. The proposed ADDCC is implemented in a 0.18-μmCMOS process. The circuit can operate from 500 to 900 MHz, and accommodates a wide range of input duty cycle ranging from 15% to 85%. The duty-cycle error of the output signal is less than 2.7%. The RMS and peak-to-peak jitters are 1.9 ps and 14.7 ps at 900MHz, respectively. The circuit operated from a 1.8-V supply voltage, the circuit dissipates 7.3 mA at 900MHz. This fully-integrated DCC chip area is 0.55 mm × 0.7 mm, the core area is 0.2 mm × 0.25 mm.
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Lai, Juan-Shan, and 賴濬紳. "Highly Accurate Duty Cycle Corrector Based on Vernier Principle." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/70934769332009465178.
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碩士國立臺灣科技大學
電子工程系
96
The duty cycle corrector (DCC) is widely adopted by DDR (double data rate)-SDRAM, half-rate CDR (clock data recovery), and Double-Sampling ADC. The clock siognlals generated DLL (delay locked loop) and PLL (phase locked loop) usually face with asymmetric duty cycle problems and must be corrected by duty cycle correctors. According to the literatures, the implemention of DCC can be divided into two catagories: the digital type and the analog type. The digital DCCs adopt non-feedback control to gain faster locking speed at the expense of less accuracy. On the contrary, the analog DCCs utilize feedback control to get better accuracy but longer locking time. To gain the advantages of both types, a mixed-type feedback DCC based on vernier principle is proposed in this thesis to achieve extremely high accuracy. With mixed-type operation, it needs only 10 clock cycles for locking, which is much less than those of the conventional analog versions. Furthermore, the effective resolution of the DCC is made to be the difference of two delay cells and the accuracy is substantially improved from those of the conventional digital ones. The proposed circuit has been fabricated in a TSMC 0.18-μm CMOS technology. The operation frequency range and duty-cycle correctable range are 250MHz ~ 1GHz and 40% ~ 60% respectively. The measured error is proven to be merely -0.86%~+0.51%. The chip area is 0.668 × 0.593mm2 only and the power consumption is 16.8mW at 800 MHz.
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Chang, Wenlung, and 張文龍. "VLSI Design And Implementation Of An All Digital Duty Cycle Corrector." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/02309853494120625963.
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碩士國立金門大學
電資研究所
100
Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) were widely used in communication systems, especially for the circuit design of high-speed communication and SOC (System on a Chip). The PLL or DLL circuits have the functions of clock deskew, clock recovery and clock synchronization. The frequency and phase of input clock can be locked by the PLL or DLL circuits. But the duty cycle of the clock may not be 50%. In order to achieve 50% duty cycle, the duty cycle corrector circuit will be used. This thesis will propose a VLSI chip of an all digital duty cycle correction circuit with the ability to lock at 50% duty cycle which is realized in TSMC 0.18 μm process. In our proposed work, the duty cycle correction circuit will be verified by functional simulation and post-simulation. The power consumption、 area and locking time of our proposed circuits are 16.6mW、5149. 267282 μm2 and 7 clocks, respectively.
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Hsieh, Yi Hsien, and 謝儀憲. "An All-Digital Duty Cycle Corrector with Synchronization and Frequency Doubling." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/74112265181389175895.
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碩士長庚大學
電機工程學系
101
The integrated circuits (IC) have been having higher speed and better performance with the progress of complementary metal-oxide-semiconductor (CMOS) process in recent years. In most digital and analog circuits, a large number of clock signals are used to trigger circuits. The accuracies of clock frequency, phase, and pulse width are very important under high operating frequency. Phase-locked loops (PLLs) and delay-locked loops (DLLs) are widely used in microprocessors, memory, and communication IC to generate clock. But whether PLLs or DLLs, they only can correct the signal frequency and phase. The duty cycle cannot be corrected. So that is why the duty cycle correctors (DCCs) are developed. Recent studies on the synchronization of output and input clocks and efficiency of time-to-digital converter (TDC) of all-digital duty cycle corrector (ADDCC) were rarely mentioned. This thesis presents an ADDCC with synchronization, reusable TDC, and frequency doubling. It is implemented in a 0.18 μm CMOS technology. The chip area is 0.517 mm x 0.873 mm. The input frequency range is from 150 MHz to 900 MHz and the output frequency range is from 300 MHz to 900 MHz. The output duty cycle is corrected to 50 ± 1.5% as the input duty cycle ranges from 25 to 75%. It dissipates 16.2 mW from a 1.8 V supply at 900 MHz. The peak-to-peak jitter at 900 MHz is 14 ps.
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Jhou, Jhong-Yi, and 周仲逸. "Fast-Locking Duty Cycle Corrector with Deskewing and Self-Resetting Capability." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/fc2n49.
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碩士國立雲林科技大學
電機工程系
103
ABSTRACT In this thesis, the design goal is to implement an all-digital duty cycle corrector (DCC) with deskewing and self-resetting capability. The coarse tuning codes are acquired from the cyclic time-to-digital coverter (CTDC). And the circuit of fine tuning section uses successive-approximation register (SAR) searching method to obtain the merit of fast-locking. When both the duty cycle correction and deskew phases are completed. The circuit becomes an delay-locked loop (DLL) for closed-loop control to align the phase error with the aid of counter mode. At the same time, the self-resetting circuitry starts to detect the frequency change with the aid of CTDC. When the difference between the recorded cycle time and the newly detected cycle time with frequency deviation is greater than the two clock cycles that is generated inside the CTDC, the resetting circuitry will restart to work for both the duty cycle correction and deskew phases. The proposed circuit is simulated with UMC 0.18μm 1P6M process. The operating frequency is within 73 ~ 500MHz; The tolerable range of the input duty cycle is from 20% to 65%. The deviation of the output duty cycle is within 49% to 52%. The minimum cyclic time difference of the alternant frequency is 802ps. Keywords： duty cycle corrector (DCC), cyclic time-to-digital converter (CTDC), successive-approximation register (SAR)
14
Chen, Shou-Zhi, and 陳首志. "High Accuracy Duty Cycle Corrector Based on SAR Loading Capacitor Adjustment." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/23314816104586355979.
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碩士國立臺灣科技大學
電子工程系
97
Nowadys the reference clock of electronic systems or chips is usually generated by phase-locked loop (PLL) or delay-locked loop (DLL). Due to the process, voltage and temperature (PVT) variations, the duty cycle of PLL or DLL output can be hardly achieved as 50%. It will seriously deteriorate the performance of the systems whose both rising and falling edges are used for triggering or strobing, such as Double data rate SDRAM, DDR SRAM, Double-Sampling ADC, Dynamic logic, Clock Data Recovery. The performance of the above systems can be substantially improved by adopting duty cycle correctors to calibrate the duty cycle of the reference clock back to 50%. Conventionally, the duty cycle correctors can be further divided into analog type and digital type. The digital DCC can also be sub-divided into non-feedback type and feedback type. Digital DCCs of both types own fast locking capability at the expense of relatively poor accuracy. The analog DCC is usually implemented as feedback type whose locking speed is slow owns comparatively high accuracy. In this thesis, a digital duty cycle corrector based on SAR loading capacitor adjustment will be proposed to achieve both fast locking and high accuracy. The test chips have been fabricated in TSMC 0.18μm standard CMOS process. The operation frequency range is within 1GHz~1.6GHz and the correctable duty cycle range is between 30%~70% respectively. The error measurement is -0.44%~+0.54% which is the best among current DCCs. Theoretically, the duty cycle correction can be completed within 8 reference clocks. The chip area is merely 0.215 x 0.2 mm2 and the power consumption is 22.5mW at 1GHz.
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Lin, Chien-Yu, and 林建佑. "Design of a 0.8 GHz-4 GHz Duty-Cycle Corrector Within 20%–80% Correction Range." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/ww6amm.
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碩士逢甲大學
電子工程學系
107
An analog duty cycle correction circuit using a novel pulse-width modification cell. We correct the duty-cycle by changing the phase of the voltage. Our calibration allows the input duty cycle to range from 20% to 80%, and the circuit corrects the duty cycle to 50%. The proposed circuit operates at a frequency of 0.8 GHz to 3 GHz and the simulation result error is less than 1%. The circuit is implemented in a 1.8V 180nm CMOS technology at 25°C. The chip area is 0.946*0.923〖mm〗^2 and the power consumption is 10.85mW at input frequency of 1GHz . Table 1 shows the duty cycle range for acceptable input signals. In the simulation results, the duty cycle range for accepting input signals is found to be: input signal frequency is 0.8 GHz-1 GHz, input signal range is 30% - 70%; input signal frequency is 1 GHz - 3 GHz, input signal range is 20% - 80%; input signal frequency is 3 GHz - 4 GHz, input signal range is 30% - 70%.
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Li, Larry, and 李文益. "A Low Jitter Delay-Locked Loop with a Realignment Duty Cycle Corrector." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/38993357589156898520.
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碩士國立中興大學
電機工程學系
93
In this thesis, a new delay-locked loop (DLL) architecture is proposed to effectively improve the DLL jitter performance. A novel realignment duty cycle corrector (RDCC) is proposed for the DLL. The RDCC circuit can make the output waveform of the DLL maintain a 50% duty cycle in a lock mode. The RDCC circuit has advantages of low power consumption, small chip area and high operating frequency. The proposed DLL adopts the clean ref-clock signal and the locked signal to do the “realignment” operation, which improves the jitter performance. The DLL is designed using the TSMC 0.35um 2P4M CMOS technology. HSPICE simulation results show that the proposed DLL jitter is effectively reduced 61% at 250MHz with a 3.3V supply.
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Kao, Shao-Ku, and 高少谷. "Design and implementation of all-digital DLL and duty cycle corrector circuit." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/57662523668170518196.
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博士國立臺灣大學
電子工程學研究所
95
This thesis describes digital implemented the analog circuit with advanced standard sub-micro CMOS technology to solves of clock skew and duty cycle. The digital implemented IC can achieve a fine performance compare to the analog. It has high portability and scalability across different technology process. Its high integrity, low power, and low jitter performance can be easily incorporated into a single chip and successful realization of the system-on-a-chip (SOC). A clock with 50% duty cycle is extremely important in many double-rate systems such as DDR-SDRAMs and analog-to-digital converters. Therefore duty-cycle corrector (DCC) is needed to correct duty cycle as 50%. This dissertation provides an all-digital pulsewidth control loop (PWCL) with adjustable duty cycle. The output clock is not only achieved 50% duty cycle, but can adjust from 30%~70% in steps of 10%. A pulsewidth detector using the sequential time-to-digital conversion is employed to detect the duty cycle of input clock. Then, we proposed the PWCL is embedded with an all-digital delay-locked loop. Therefore, the output of clock can synchronize with input clock and also with variable duty cycle. Both experimental chips have been fabricated in a 0.35um CMOS process. The operation frequency range is from 400 MHz to 600 MHz. Next, we develop all-digital duty cycle corrector circuit; the first test chip generates the 50% duty cycle and synchronizes with input clock. The measurement results shows the proposed circuit operates with input frequency range with 0.8~1.2GHz and input 40%~60% duty cycle. The second test chip, a period monitor is used to track the period of input to keep 50% duty cycle, when the period of input clock is changed. The proposed circuit works for the input duty cycle of 10%~90% and the measured operation frequency range is from 1 GHz to 1.6 GHz. The all-digital duty cycle corrector circuits have been verified on silicon using 0.18um CMOS technology.
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Kao, Shao-Ku. "Design and implementation of all-digital DLL and duty cycle corrector circuit." 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-0607200714104900.
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Peng, Jyun-Hua, and 彭俊樺. "Design of a De-Skew Wide-Range Half-Delay-Line Duty Cycle Corrector." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/54833609514167856731.
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碩士國立暨南國際大學
電機工程學系
97
In recent years, with the progress of the semiconductor process technology, the circuit density is increased, the circuit capability is much stronger, and the operating frequency of integrated circuit also moves toward multi-gigahertz. In many high-speed SoCs, the clock signal usually suffers not only duty cycle distortion but also phase skew problem due mainly to the mismatch between pull-up and pull-down network of the circuits and unmatched clock signal routing. The clocking circuitry, including the duty-cycle adjustment circuits and phase alignment circuits, plays an important role for the success of an SoC. In this thesis, we proposed a new 50% all digital duty-cycle corrector (AD-DCC). There are three significant design concepts in this duty-cycle corrector. The first is an edge-triggered half-delay-line architecture. The second is a depth-first search algorithm. The third is a low-power path-symmetrical SR Latch. The achievements of the AD-DCC include a de-skewed output clock, a more accurate duty-cycle correction, a larger operating frequency range, a wider acceptable duty-cycle range for the input clock, a higher power efficiency, a reduced circuit complexity, a faster duty-cycle correction speed and an extended application scope, compared to conventional DCC’s. The proposed AD-DCC is designed with a 0.18-µm CMOS 1P6M 1.8V process technology. The operating frequency of the proposed AD-DCC ranging from 68MHz to 470MHz is confirmed through HSPICE circuit simulation. Simulation results also show that the proposed AD-DCC takes only 17 clock cycles to do both duty-cycle correction and phase alignment in the worst case. Besides, the corrected duty-cycle varies from 47.73% to 50.45% and the static phase error is as small as 100 ps. Furthermore, the acceptable duty- cycle of the input signal ranges from 10% to 90% and the maximal power consumption is about 2.38 mW at 470 MHz.
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Chen, Yi-Jin, and 陳怡瑾. "Low Jitter Wide Range Duty Cycle Corrector Based on Pulse Shrinking/Stretching Mechanism." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/24750481251519139239.
Full textAbstract:
碩士國立臺灣科技大學
電子工程系
97
The Duty cycle correctors (DCCs) are widely used to adjust the clock duty cycle to 50% for DDR (double data rate)-SDRAM, Double-Sampling ADC, DLL (delay locked loop) and PLL (phase locked loop) where both clock rising and falling edges are used for operation since clock signals with 50% duty cycle are extremely important for high-performance IC or system designs. The implementations of DCCs are divided into two categories in literature: the digital and the analog structures. The realization of digital-structure DCCs is further categorized as feedback type and nonfeedback type. Both own fast locking speed ate the expense of relatively poor accuracy. The analog-structure DCCs are usually implemented as feedback type to get better accuracy with relatively long locking time. In this thesis, an analog feedback duty cycle corrector with an extremely simple structure will be presented. The pulse width of the input clock is properly shrunk or stretched by a pulse shrinking/stretching delay line to ensure 50% duty cycle for the output signal. The proposed DCC has been implemented in a TSMC 0.18μm CMOS digital process. An input duty cycle range of 20%~80% is achieved. The duty cycle error is between -0.56% to +6% for the widest dynamic frequency operation range of 100MHz~1.4GHz. The chip area is merely 0.18 × 0.14 mm2. The power consumption is 1mW at 1GHz and the peak-to-peak output jitter is measured to be 9.3ps @ 1.4 GHz only.
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Tseng, Shang Ning, and 曾上寧. "All-Digital Synchronous Fast-Locked Duty Cycle Corrector With Self-Calibration Delay-line." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/61311079473792043389.
Full textAbstract:
碩士長庚大學
電機工程學系
103
The integrated circuits (IC) have been having higher speed and better performance with the progress of complementary metal-oxide-semiconductor (CMOS) process in recent years. In most digital and analog circuits, a large number of clock signals are used to trigger circuits. The accuracies of clock frequency, phase, and pulse width are very important under high operating frequency. Phase-locked loops(PLLs) and delay-locked loops(DLLs) are widely used in microprocessors, memory, and communication IC to generate clock. But whether PLLs or DLLs, they only can correct the signal frequency and phase. The duty cycle cannot be corrected. So that is why the duty cycle correctors(DCCs) are developed. The purpose of this thesis is to design an all-digital duty cycle corrector by using a set of digital code to control two delay lines. One of the delay lines is one and half times as big as the other. The conventional all-digital duty cycle corrector quantize the period of input clock into digital code, and then digital code is divided by two to get half period delay time of input clock. By using this method, if the digital code is odd number, it will produce a quantization error with loss half delay time from the delay cell. We avoid the problem by using just a set of digital code to control two delay lines, therefore the digital is no need to divide by 2. Then, we form an all-digital duty cycle corrector with synchronized、fast locking and 50% duty cycle through this half period delay time. It is implemented in a 0.18 μm CMOS technology. The chip area is 0.95485mm*0.79985mm. The operating frequency range is 800 MHz to 1.4 GHz. The output duty cycle is corrected to 50 ± 1% as the input duty cycle ranges from 20% to 80%. It dissipates 28.8mW from a 1.8 V supply at 1.4 GHz. The peak-to-peak jitter at 1.4 GHz is 10.25 ps.
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Shen, Sung-En, and 沈頌恩. "A Wide-Range All-Digital Duty-Cycle Corrector with Output Clock Phase Alignment in 65nm CMOS Technology." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/59047555443971297202.
Full textAbstract:
碩士國立中正大學
資訊工程研究所
99
A Wide-Range All-Digital Duty-Cycle Corrector (ADDCC) with Output Clock Phase Alignment in 65nm Technology is presented in this dissertation. In high speed data transmitter application, such as double data rate (DDR) SDRAM and double sampling analog-to-digital converter (ADC), the positive edge and the negative edge of system clock are utilized for sampling the data. Thus, theses systems require an exact 50% duty-cycle of system clock. Nevertheless, system clock is affected by the unbalanced rise time and fall time of the clock buffers with process, voltage and temperature (PVT) variations, which cause error data latching when clock duty-cycle is not equal to 50%. We summarize some researches and architectures in prior years, moreover, discuss these differences and how to improve them. In this thesis, we use all-digital control method not only speed-up locking time than voltage control method, but also solve the leakage current problem of the voltage charge-pump control. Besides, we presented the novel high resolution ADDCC which can solve the restricted resolution of time-to-digital converter (TDC). The half-cycle delay line (HCDL) generates output clock signal by another mirror circuit will cause mismatch problem in nano-meter CMOS process when there has on-chip variations (OCVs). The proposed ADDCC is implemented on a standard performance (SP) 65nm CMOS process with standard cell library, and verify the performance of the proposed circuit.
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Jiang, Jun, and 江軍. "Design and Implementation of Fast Locking all-digital duty cycle corrector circuit with wide range input frequency." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/33770397878115771040.
Full textAbstract:
碩士長庚大學
電機工程學系
99
With the continuous scaling of CMOS technology, the demand of high speed and high-density integration for VLSI system had exponential growth recently. However, since the feature size of the transistors scales down year by year, the short channel effects and the presence of the process, voltage, temperature and load (PVTL) variations become the issues. Moreover, the enlarged clock skew makes the circuit hard to design. The all-digital design has high portability and scalability across different process of technology. Its high integrity, low power, and low jitter performance can be easily incorporated into several systems. A clock with 50% duty-cycle is extremely important in many double-rate systems such as DDR-SDRAMs and analog-to-digital converters. Therefore, the duty-cycle corrector (DCC) loop is needed to correct duty cycle as 50%. The major purpose of this paper is the design and implementation of all-digital duty-cycle corrector (ADDCC). In order to reduce the locked time and save the area of the delay line, a cycle-controlled delay (CCD) is adopted. The clock pulse generator is adopted to produce the 0° and 180° phases, which are provided to pulse generator and later are converted to the duty cycle of the output clock. The features of the proposed duty cycle corrector include a wide operation-frequency range, a wide duty cycle range for the input clock, and a faster correction speed. The proposed duty- cycle corrector is based on the 0.35µm CMOS process, the chip area is 0.67 *1.36mm², the input signal frequency is from 10MHz to 100MHz, and the duty-cycle range of input is from 30% to 70% with the error less than 1%. It can complete the correction in six cycles. Furthermore, the proposed delay line plays not only a time-to-digital converter (TDC) but also a digital-to-time converter (DTC). Hence it can obviously reduce the chip area.
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Li, Chang-Jun, and 李長潤. "A 0.5V/1.0V Low-Power Delay-Recycled All-Digital Duty-Cycle Corrector with Unbalanced Process Variations Tolerance." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/37616770641066423586.
Full textAbstract:
碩士國立中正大學
資訊工程研究所
101
Due to the unbalanced rise time and fall time of the clock tree buffers, the duty-cycle of the on-chip clock may be distorted when it is distributed through the clock buffers to every module. However, for high speed data communication applications, such as double data rate synchronous dynamic random access memory (DDR SDRAM) and double sampling analog-to-digital converter (ADC), it requires to sample the input data via the positive and negative edges of the reference clock. Duty-cycle error causes malfunction in these applications. For the sake of this requirement, a duty-cycle corrector (DCC) is employed in the system-on-a-chip (SoC) to correct the distorted clock. With the growing recognition of energy savings, designing low-power electronic devices is demanded. According to the dynamic power dissipation equation, P=C(V^2)f, if we reduce the supply voltage to one-half of the nominal voltage, it can reduce 75% of power dissipations. However, the operating voltage near to the threshold voltage makes transistors charging and discharging slower. Hence, the intrinsic delay of logic gates becomes longer and directly affects the overall chip performance. Hence, an all-digital duty-cycle corrector (ADDCC) with dual supply voltage mode and unbalanced process variation tolerance is presented in this thesis. The proposed ADDCC is implemented in TSMC 90nm CMOS process with standard cells. The proposed ADDCC has following characteristics: fast lock-in time, low area cost, low power consumption and high precision in duty-cycle correcting. Therefore, it is very suitable for low-power applications. Index Terms — All-Digital Duty-Cycle Corrector, Delay-Recycled Half-Cycle Delay Line, Time-to-Digital Converter, Unbalanced Process Variations Tolerance.
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WU, GUAN-WEI, and 吳冠葳. "The Design of 0.2-1.8GHz Duty Cycle Correction Circuit." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/95ce9s.
Full textAbstract:
碩士逢甲大學
電子工程學系
106
In this thesis, we propose an analog high speed circuit which is fast locking and low error. It is necessary to have precise signal transmission in the modern high speed signal transmission circuit and any signal circuit which need correction. In order to avoid the instability of the circuit system caused by the distortion of the clock signal, PLL(Phase Lock Loops) can be used in the circuit for controlling phase and frequency. PLL(Phase Lock Loops) is generally widely used in the field of electronic communication, for example, computer memory, radio frequency technology, microprocessor, etc. The proposed circuit operation frequency is at 0.2GHz to 1.8GHz, the errors are less than ±1%. The correction circuit is implemented in a 1.8V, and 180nm CMOS technology.
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CHEN, YU-JHE, and 陳昱喆. "A SAR-based Delay-Locked Loop with Duty-Cycle Correction." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/g2gb3w.
Full textAbstract:
碩士國立雲林科技大學
電機工程系
107
All-digital delay-locked loops (ADDLLs) have been widely applied in clock synchronization due to the advantage of smaller area, lower power and shorter locking time. The successive approximation register-controlled delay-locked loop (SARDLL) adopts the binary search algorithm to set the digital control codes such that the locking time is proportional to the number of bits in the digital-controlled delay line. A clock with 50% duty-cycle is extremely important in double-rate system. Therefore, the duty-cycle correction circuit is needed to correct the duty-cycle of the clock. The general duty-cycle correction circuit uses two half delay line or three half delay line to sample the cycle time, but the cost of the increase in area and operating time must be paid. The circuit proposed in this thesis solves the problem by using a single control delay line with the multiplexer as a recycle delay line. The chip is designed and simulated in a TSMC 90nm process provided by TSRI. Its operating frequency range is within 80~600MHz. The duty cycle of input clock frequency is within 30~70%. The deviation of the output duty cycle is within 48.9~50.6%. the maximum power consumption is 5.6mW, and the locking time is 48 reference clock cycles. Keywords：Successive Approximation Register(SAR), Delay-Locked Loop(DLL), Duty-Cycle Correction(DCC)
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Bo-Jiun, Chen. "All-Digital Fast-Locking Delay-Locked Loop with Duty Cycle Correction." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1207200620264800.
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Chen, Bo-Jiun, and 陳柏均. "All-Digital Fast-Locking Delay-Locked Loop with Duty Cycle Correction." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/60142693822760595477.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
94
With the evolution and continuing scaling of CMOS technologies, the demand of high speed and high integration density VLSI systems have the exponential growth recently. However, the synchronization problem among IC modules is undoubtedly important and becoming one of the bottlenecks for high performance systems. Phase-locked loops (PLLs) and delay-locked loops（DLLs）have been widely employed for the purpose of synchronization. Due to the difference of their configurations, the DLLs are preferred for their unconditional stability and faster locking time than the PLLs. Additionally, a DLL offers better jitter performance than a PLL because noise in the voltage-controlled delay line (VCDL) does not accumulate over many clock cycles. The all-digital design has high portability and scalability across different technology process. Its high integrity, low power, and low jitter performance can be easily incorporated into several systems. A clock with 50% duty-cycle is extremely important in many double-rate systems such as DDR-SDRAMs and analog-to-digital converters. Therefore duty-cycle corrector (DCC) is needed to correct duty cycle as 50%. This thesis contains three design and realization of the all-digital DLL and DCC circuits. First of all, an all-digital 50% DCC is presented. The features of the proposed DCC include a wide operation frequency range, a wide input duty cycle range for the input clock, and a faster correction speed. The acceptable duty cycle and frequency range of the input clock is 25%-75% and 250MHz-600MHz, respectively. The correction time is 8ns at 500MHz. Besides, this DCC can save power consumption by turning off half of the delay cells. Secondly, a fast-locking all-digital DLL with 50% duty cycle is proposed. Based on the proposed architecture, not only the phase alignment of input and output clocks can be achieved, but also the duty cycle of the output clock can be corrected to 50%. It can synchronize in four cycles. Besides, the proposed delay line plays not only delay cells but also a time-to-digital converter (TDC). So it reduces active area and power effectively. The input frequency range can operate within 300MHz-500MHz. The accepted input duty cycle range is 40%-60%. Thirdly, a wide-range anti-reset all-digital DLL is presented. The total system does not need any outside-reset signal to reset the system when the input clock frequency changes a lot, due to the dynamic frequency detector. The proposed binary TDC can reduce effectively hardware compared with a traditional TDC. Besides, the while system is a closed loop and it can track PVT variations. The input frequency range can operate within 62.5MHz-625MHz. It spends four to six cycles to get synchronization.
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Yu, Jen-Tsung, and 游仁宗. "A Compact Delay-Recycled Clock Skew-Compensation And/Or Duty-Cycle-Correction Circuit." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/34570195575256761660.
Full textAbstract:
碩士國立暨南國際大學
電機工程學系
99
A clock skew-compensation and/or duty-cycle correction circuit (CSADC) is indispensably required to maximize the performance of a synchronous double edge clocking system. Most conventional CSADC adopted a cascade structure that inherits a lower performance property that is causing a slower the locking procedure, meanwhile the dual loop design results in more design complexity. In this thesis, a compact delay-recycled CSADC was proposed. There are two significant design concepts in the CSADC. The first is a fast locking and low power measure-and-tuned architecture. The second is a bandwidth augmentation technique. Compared to conventional CSADCs, the proposed circuit achieves at least a 4.24 times reduction in power, a 7.93 times reduction in power bandwidth ratio, and a 1.11 times reduction in lock-in cycles. In TSMC 0.18-μm 1P6M 1.8V CMOS process, the “input signal frequency range” of the proposed CSADC from 300MHz to 2GHz, and the corrected duty cycle variation ranges from 48.41% to 55.51% are confirmed through HSPICE circuit simulation. When the clock frequency is 2GHz, the acceptable input duty cycles ranges from 30% to 70%. Besides, the aligned phase error and power consumption are 67ps and 5.87mW, respectively.
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Chang, Feng-Chia, and 張峰嘉. "A Wide Range Delay Locked-Loop with Built-in Duty Cycle Correction Circuit." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/98153723799468878945.
Full textAbstract:
碩士臺灣大學
電子工程學研究所
96
With the demand for high-speed and high integration density VLSI systems has grown tremendously, the evolution and continuing scaling of CMOS technologies enable the designers to implement high performance and complex systems on a single chip with millions of transistors and interconnections. However, the synchronization problem has become the most challenging task in such complex systems. This paper presents a novel delay-locked loop (DLL) with wide-range operation, fixed latency of one cycle and still preserve 50% duty cycle. This DLL uses 1/2n outputs of voltage-controlled delay line (VCDL) (n is an integer) to enlarge the Operating frequency range and eliminate stuck or harmonic problem. Theoretically, the operating frequency range of the proposed DLL can be from 0 to 3*2n*Tref, where Tref is the period of input reference clock. Meanwhile, the duty cycle can be detected and corrected by using the phase information from 1/2 VCDL output signal. This circuit is implemented in a TSMC 0.35-μm CMOS technology. The DLL occupies an active area of 0.9 x 0.8 mm2 , operating frequency range from 300MHz to 650Mhz and consumes a maximum power of 60mW at 500MHz.
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SIANG, PEL-LUN, and 向培綸. "All-Digital Delay-Locked Loop with Duty-Cycle Correction using Standard Cell Library." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/2x787v.
Full textAbstract:
碩士國立雲林科技大學
電機工程系
106
In this thesis, an all-digital delay-locked loop with duty-cycle correction is proposed and implemented with the cell-based design flow. The proposed circuit utilizes the two half-delay line architecture to realize the function of duty cycle correction. After the period acquisition is done, the delay time of the half-delay line is set to be equal to one half of the input clock period, and the duty cycle of the output clock is synthesized to be 50%. The half-delay line comprises a coarse delay line and a fine delay line connected in series so as to obtain higher resolution. In addition, a multi-phase cyclic time-to-digital converter is presented here to generate the control codes with the aid of the oscillator outputs with different phases. And the successive approximation register control mechanism also assists in reducing the phase error to achieve fast-locking capability. A test chip is designed and simulated in UMC CMOS 0.18μm process. The circuit can operate at the input clock frequency from 90 ~ 600 MHz with the duty cycle range of 20% ~ 70%, and the skew is reduced to be within -31.88ps ~ +6.01ps. The deviation of the output duty cycle is within 49.64% ~ 52.23%. The required lock time is less than 40 cycles. The proposed circuit will enter the closed-loop control mode after locking. The output clock can be re-calibrated via the counter if the delay of the input clock is changed.
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Chen, Chris, and 陳春源. "A Fixed Frequency, Fixed Duty Cycle Boost Converter with Ripple Free Input Inductor Current for Power Factor Correction." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/90954686442643108760.
Full textAbstract:
碩士國立海洋大學
電機工程學系
88
A fixed frequency, fixed duty cycle boost converter with continuous input inductor current for power factor correction operation is introduced in this paper. Thus, the proposed topology has much lower input harmonics and much better EMI performance than the conventional boost converter. By using coupled inductor technique, the input inductor current ripple can be free, the high frequency harmonic distortion can be avoided, and the low frequency input current waveform distortion is analyzed. Simulation results are presented that the proposed boost topology has the advantages of lower switch voltage stress, lower switch current stress and lower voltage stress on the capacitor.
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Chao-Ching, Chi. "A 70-500 MHz 50% Duty-Cycle Correction Circuit with a Frequency-Domain Measurement Technique in 0.35-Mum CMOS." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-0801200715583100.
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Chi, Chao-Ching, and 紀昭慶. "A 70-500 MHz 50% Duty-Cycle Correction Circuit with a Frequency-Domain Measurement Technique in 0.35-μm CMOS." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/43091014053269275843.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
95
A 50% duty-cycle correction (DCC) circuit is reported in this thesis. The proposed DCC circuit consists of a clock generator and a delay detector. The clock generator is edge-triggered by the input and produces an output whose pulse width is adjusted to half of the signal period by the delay detector. Meanwhile, the input phase information is maintained. The proposed new DCC circuit has many features, including a wider acceptable duty-cycle range of the input clock, a larger operating frequency, synchronizing output phase with input phase. The circuit is implemented in a 0.35-μm CMOS process. To evaluate the output duty-cycle accuracy, a single-sideband mixing test method is adopted. This circuit operates from 70 MHz to 500 MHz, and accommodates duty cycles ranging from 5% to 95% at 500 MHz. The output signal is corrected to 50% ± 1.4%. Operated from a 3.3-V supply, the circuit dissipates 2 mA at 70 MHz and the circuit dissipates 7 mA at 500 MHz. This fully-integrated DCC chip area is 1.1 mm*1.1 mm, including pads, mixer, and an on-chip loop capacitor (100 pF), the core area is 0.5 mm*0.55 mm.
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Zhong, Deng-Hao, and 鍾登皓. "A Wide-Range All-Digital Delay-Locked Loop Using Three kinds of Fast-Lock Binary Search Algorithms with Duty Cycle Correction." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/66677634045277476397.
Full textAbstract:
碩士國立臺灣科技大學
電機工程系
98
With the progress of the CMOS technologies, the complexity and higher clock signal frequency of memory are increasing day after day. Therefore, the reliability of the clock signal in synchronous system becomes more and more important. How to reduce clock skew will be the most important topic of the clock synchronization circuit. Delay-locked loops (DLLs) are widely used to solve the issue of clock synchronization due to its un-conditionally stable, faster transient response and less jitter accumulation than the phase-locked loops (PLLs). However, the narrow operating frequency range and no supply noise suppression become the major drawbacks for the DLLs. Therefore the variable successive approximation register-controlled (VSAR) algorithm [6] was reported to solve the problems, but the lock time is too long. Thus the subject of this dissertation is to overcome the defects, to break the limitations and to make a flexible use for the conventional DLLs circuit. This paper presents an all-digital implemented delay-locked loop with a fast-lock characteristic using three modified binary search algorithms. First, the phenomenon of repetitive search in the VSAR algorithm is removed by the proposed fast VSAR (FVSAR) algorithm. Second, the recursive SAR (RSAR) algorithm applies the binary search algorithm to the delay length adjustment in the VASR algorithm. However, the phenomenon of repetitive search takes place in the RSAR algorithm as well. Therefore the fast recursive SAR (FRSAR) is proposed to speed up the locking process. Finally, the SAR Algorithm Delay-Lock Loop with Length Detection (LDSAR) resolve the FVSAR and the FRSAR algorithm shortcomings, LDSAR algorithm applies the Length Detection Circuit to speed up the locking time and the wide range phase detector to overcome the Non 50% duty cycle problems.
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Raja, Immanuel. "Fully Integrated CMOS Transmitter and Power Amplifier for Software-Defined Radios and Cognitive Radios." Thesis, 2017. http://etd.iisc.ernet.in/2005/3559.
Full textAbstract:
Software Defined Radios (SDRs) and Cognitive Radios (CRs) pave the way for next-generation radio technology. They promise versatility, flexibility and cognition which can revolutionize communications systems. However they present greater challenges to the design of radio frequency (RF) front-ends. RF front-ends for the radios in use today are narrow-band in their frequency response and are optimized and tuned to the carrier frequency of interest. SDRs and CRs demand front-ends which are versatile, configurable, tunable and be capable of transmitting and receiving signals with different bandwidths and modulation schemes. Integrating power amplifiers (PAs) with transmitters in CMOS has many advantages and challenges. This thesis deals with the design of an RF transmitter front-end for SDRs and CRs in CMOS.
The thesis begins with an introduction to SDRs and the requirements they place on transmitters and the challenges involved in designing them in CMOS. After a brief overview of the existing techniques, the proposed architecture is presented and explained. A digitally intensive transmitter solution is proposed. The transmitter covers a wide frequency range of 750 MHz to 2.5 GHz. The inputs to the proposed transmitter are in-phase and quadrature (I & Q) data bit streams. Multiple stages of up-sampling and filtering are used to remove all spurs in the spectrum such that only the harmonics of the carrier remain.
Differential rail-to-rail quadrature clocks are generated from a continuous wave signal at twice the carrier frequency. The clocks are corrected for their duty cycle and quadrature impairments.
The heart of the transmitter is an integrated reconfigurable CMOS power amplifier (PA). A methodology to design reconfigurable Class E PAs with a series fixed inductor has been presented. A CMOS power amplifier that can span a wide frequency range with sufficient output power and efficiency, supporting varying envelope complex modulation signals, with good linearity has been designed. Digital pre-distortion (DPD) is used to linearize the PA.
The full transmitter and the clock correction blocks have been designed and fabricated in a commercial 130-nm CMOS process and experimentally characterized. The PA delivers a maximum power of 13 dBm with an efficiency of 27% at 1 GHz. While transmitting a 16-QAM signal at 1 GHz, the measured EVM is 4%. It delivers a maximum power of around 11-13 dBm from 750 MHz to 1.5 GHz and up to 6.5 dBm of power till 2.5 GHz.
Comparing the proposed system with recently published literature, it can be seen that the proposed design is one of the very few transmitters which has an integrated matching network, tunable across the frequency range. The proposed PA produces the highest output power and with largest efficiency for systems with on-chip output networks.