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Journal articles on the topic 'Duty Cycle Corrector'

Author: Grafiati

Published: 4 June 2021

Last updated: 3 February 2022

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1

Lin, Chien Yu, and Heng Shou Hsu. "Design of a High Frequency Duty-Cycle Corrector within 20%–80% Correction Range." International Journal of Information and Electronics Engineering 9, no. 2 (June 2019): 59–62. http://dx.doi.org/10.18178/ijiee.2019.9.2.706.

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2

Kao, Shao-Ku, and Yong-De You. "Clock buffer with duty cycle corrector." Microelectronics Journal 42, no. 5 (May 2011): 740–44. http://dx.doi.org/10.1016/j.mejo.2011.02.001.

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3

Kao, Shao-Ku. "Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency." Electronics 10, no. 1 (January 3, 2021): 71. http://dx.doi.org/10.3390/electronics10010071.

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This paper presents a fast locking and wide range input frequency all-digital duty cycle corrector (ADDCC). The proposed ADDCC circuit comprises a pulse generator and a clock generator. The pulse generator is edge-triggered by an input signal to produce a 0 degree and 180 degree phase. The clock generator uses a 0 degree and 180 degree phase to produce the 50% duty cycle output signal. It corrects the duty cycle of the input signal in six clock cycles. The proposed ADDCC is implemented in a 0.35 µm CMOS process. The circuit can operate from 10 MHz to 100 MHz, and accommodates a wide range of input duty cycles ranging from 30% to 70%. The duty-cycle error of the output signal is less than ±1%.

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4

Huang, Hong-Yi, and Chia-Ming Liang. "Frequency multiplier using 50% duty cycle corrector." IEICE Electronics Express 5, no. 22 (2008): 990–94. http://dx.doi.org/10.1587/elex.5.990.

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5

Wu, J. H., J. H. Gu, L. Z. Zhang, and M. Zhang. "Full-MOSFET mixed-mode duty cycle corrector." Electronics Letters 47, no. 19 (2011): 1067. http://dx.doi.org/10.1049/el.2011.1660.

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6

Patil, Meghana, Kiran Bailey, and Rajanikanth Anuvanahally. "Duty Cycle Corrector Using Pulse Width Modulation." International Journal of VLSI Design & Communication Systems 10, no. 03 (June 29, 2019): 01–17. http://dx.doi.org/10.5121/vlsic.2019.10301.

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7

Jeong, Chan-Hui, Ammar Abdullah, Young-Jae Min, In-Chul Hwang, and Soo-Won Kim. "All-Digital Duty-Cycle Corrector With a Wide Duty Correction Range for DRAM Applications." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24, no. 1 (January 2016): 363–67. http://dx.doi.org/10.1109/tvlsi.2015.2394486.

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8

Kao, Shao-Ku, and Shen-Iuan Liu. "All-Digital Fast-Locked Synchronous Duty-Cycle Corrector." IEEE Transactions on Circuits and Systems II: Express Briefs 53, no. 12 (December 2006): 1363–67. http://dx.doi.org/10.1109/tcsii.2006.885396.

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9

Jovanovic, Goran, and Mile Stojcev. "Pulse width control loop as a duty cycle corrector." Serbian Journal of Electrical Engineering 1, no. 2 (2004): 215–26. http://dx.doi.org/10.2298/sjee0402215j.

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The clock distribution and generation circuitry forms a critical component of current synchronous digital systems. A digital system?s clocks must have not only low jitter, low skew, but also well-controlled duty cycle in order to facilitate versatile clocking techniques. In high-speed CMOS clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a multistage buffer because the circuit is not pure digital [8]. In this paper, we propose a pulse width control loop referred as MPWCL (modified pulse width control loop) that adopts the same architecture as the conventional PWCL, but with a new pulse generator and new charge pump circuit as a constituent of the duty cycle detector. Thanks to using new building blocks the proposed pulse width control loop can control the duty cycle in a wide range, and what is more important it becomes operative in saturation region too, what provides conditional for fast locking time. For 1.2 ?m double-metal double-poly CMOS process with Vdd = 5 V and operating frequency of 133 MHz, results of SPICE simulation show that the duty cycle can be well controlled in the range from 20 % up to 80 % if the loop parameters are properly chosen.

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10

Kao, Shao-Ku. "A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock." Electronics 10, no. 7 (April 5, 2021): 860. http://dx.doi.org/10.3390/electronics10070860.

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This paper proposes an all-digital duty cycle corrector with synchronous fast locking, and adopts a new quantization method to effectively produce a phase of 180 degrees or half delay of the input clock. By taking two adjacent rising edges input to two delay lines, the total delay time of the delay line is twice the other delay line. This circuit uses a 0.18 μm CMOS process, and the overall chip area is 0.0613 mm2, while the input clock frequency is 500 MHz to 1000 MHz, and the acceptable input clock duty cycle range is 20% to 80%. Measurement results show that the output clock duty cycle is 50% ± 2.5% at a supply voltage of 1.8 V operating at 1000 MHz, the power consumed is 10.1 mW, with peak-to-peak jitter of 9.89 ps.

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11

K, Sindhuja. "All Digital Wide Range Msar Controlled Duty-Cycle Corrector." Advanced Computing: An International Journal 5, no. 4 (July 31, 2014): 9–16. http://dx.doi.org/10.5121/acij.2014.5402.

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12

JO, Y., H. PARK, S. YANG, S. KIM, and K. H. BAEK. "Digitally Controlled Duty Cycle Corrector with 1 ps Resolution." IEICE Transactions on Electronics E90-C, no. 9 (September 1, 2007): 1841–43. http://dx.doi.org/10.1093/ietele/e90-c.9.1841.

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13

Han, S., and J. Kim. "Hybrid duty-cycle corrector circuit with dual feedback loop." Electronics Letters 47, no. 24 (2011): 1311. http://dx.doi.org/10.1049/el.2011.2710.

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14

Wu, Jianhui, Junhui Gu, and Zhengchang Du. "1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector." Analog Integrated Circuits and Signal Processing 71, no. 3 (July 20, 2011): 531–38. http://dx.doi.org/10.1007/s10470-011-9699-1.

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15

DU, Zhengchang, Jianhui WU, Shanli LONG, Meng ZHANG, and Xincun JI. "Duty Cycle Corrector for Pipelined ADC with Low Added Jitter." IEICE Transactions on Electronics E92-C, no. 6 (2009): 864–66. http://dx.doi.org/10.1587/transele.e92.c.864.

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16

Junhui Gu, Jianhui Wu, Danhong Gu, Meng Zhang, and Longxing Shi. "All-Digital Wide Range Precharge Logic 50% Duty Cycle Corrector." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 4 (April 2012): 760–64. http://dx.doi.org/10.1109/tvlsi.2011.2111424.

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17

Chung, Ching-Che, Duo Sheng, and Chang-Jun Li. "A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, no. 11 (November 2015): 2487–96. http://dx.doi.org/10.1109/tvlsi.2014.2370631.

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18

Attia, Hussain. "Artificial neural network based unity power factor corrector for single phase DC-DC converters." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (August 1, 2020): 4145. http://dx.doi.org/10.11591/ijece.v10i4.pp4145-4154.

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Due to the negative effects of the non-linear semiconductor devices and the passive electrical components (inductor and capacitor) in the converter circuits, and that are deteriorating the power factor (PF) and total harmonics distortion (THD) of grid current, this study proposes a novel unity PF correction controller based on a new algorithm of neural network to improve the performance of a single phase boost DC-DC converter with respect to the mentioned concerns. The controller guarantees stable load voltage. The PF corrector, firstly measures the phase shift between grid voltage and grid current waveforms, then through a new artificial neural network (ANN) algorithm, a suitable duty cycle is predicted to guide and control the converter to reduce the phase shift between grid voltage and grid current as possible to have maximum PF which is unity PF, and to improve the THD level of grid current. The proposed system is simulated and evaluated via Simulink of MATLAB, the simulation results are collected at constant duty cycle and at controlled duty cycle through the proposed PF controller using different loads. The presented PF controller guarantees the unity power factor, and enhances the grid alternating current THD.

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19

BABAZADEH, HADISEH, ARASH ESMAILI, KHAYROLLAH HADIDI, and ABDOLLAH KHOEI. "A WIDE-RANGE PROGRAMMABLE PULSE WIDTH CONTROLLER." Journal of Circuits, Systems and Computers 23, no. 05 (May 8, 2014): 1450075. http://dx.doi.org/10.1142/s0218126614500753.

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A very simple, wide range and programmable pulse width controller or duty cycle corrector (DCC) is presented. Simulating the circuit in 0.35 μm Complementary MOSFET (CMOS) technology shows that the frequency range of the input signal can be within 250 MHz to 1.6 GHz, with a duty cycle of 30–70%. The proposed circuit generates an output signal with programmable duty cycle in the range of 30–70% with steps of 10% which could be extended to more steps by simple variations. The systematic peak-to-peak jitter at center frequency (1 GHz) is 1ps, while adding a random noise source of 5% of the power supply, increases it to 13 ps. the power consumption at maximum speed (1.6 GHz) is 4.9 mW. Monte Carlo simulations show maximum of 3.4% error at the 1.5 GHz input frequency and 70% output duty cycle.

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20

Qiu, Yusong, Yun Zeng, and Feng Zhang. "1–5 GHz duty‐cycle corrector circuit with wide correction range and high precision." Electronics Letters 50, no. 11 (May 2014): 792–94. http://dx.doi.org/10.1049/el.2014.0170.

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21

Ma, Rui, Zhangming Zhu, Maliang Liu, Ping Gan, and Yintang Yang. "Analog-Based CMOS Duty Cycle Corrector with 50–800 MHz Operating Range." Journal of Circuits, Systems and Computers 24, no. 07 (June 17, 2015): 1550100. http://dx.doi.org/10.1142/s0218126615501005.

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In this paper, a novel accurate analog-based 50% duty cycle corrector (DCC) for high-speed and high-resolution operations is presented. Due to the performance limitations of conventional DCCs, such as a confined locking range and overtone locking, a novel delay line using forward-body-bias technique and reset circuit are adopted to enlarge the locking range of the proposed DCC. Simulated results based on the standard 0.18 μm 1.8 V standard CMOS process show that output duty cycle error is less than ±1% over an input frequency range of 50–800 MHz. The peak-to-peak jitter at 800 MHz is 789.77 fs with a power consumption of 11.09 mW. The active layout area of the proposed DCC is 0.21 × 0.21 mm2.

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22

Chung, Ching-Che, Duo Sheng, and Sung-En Shen. "High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, no. 5 (May 2014): 1096–105. http://dx.doi.org/10.1109/tvlsi.2013.2260186.

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23

S.V, Mrs KIRUTHIKA, and Dr (Mrs ). R. SUDARMANI. "A High Resolution All Digital Duty Cycle Corrector Using Reversible Multiplexer Logic." International Journal of Engineering Trends and Technology 22, no. 1 (April 25, 2015): 27–30. http://dx.doi.org/10.14445/22315381/ijett-v22p207.

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24

Kim, Esther, Youngjoo Lee, and Taehyoun Oh. "A 2–8-GHz adaptive duty-cycle corrector loop with background calibration." International Journal of Electronics 104, no. 9 (April 11, 2017): 1578–88. http://dx.doi.org/10.1080/00207217.2017.1312713.

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25

Lim, Ji-Hoon, Jun-Hyun Bae, Jaemin Jang, Hae-Kang Jung, Hyunbae Lee, Yongju Kim, Byungsub Kim, Jae-Yoon Sim, and Hong-June Park. "A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs." IEEE Transactions on Circuits and Systems II: Express Briefs 63, no. 2 (February 2016): 141–45. http://dx.doi.org/10.1109/tcsii.2015.2468911.

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26

Young-Jae Min, Chan-Hui Jeong, Kyu-Young Kim, Won Ho Choi, Jong-Pil Son, Chulwoo Kim, and Soo-Won Kim. "A 0.31–1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 8 (August 2012): 1524–28. http://dx.doi.org/10.1109/tvlsi.2011.2158011.

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27

Liu, Minjie, Yingzi Jiang, Siwan Dong, Zhangming Zhu, and Yintang Yang. "A low-jitter wide-range duty cycle corrector for high-speed high-precision ADC." Microelectronics Journal 46, no. 5 (May 2015): 333–42. http://dx.doi.org/10.1016/j.mejo.2015.02.005.

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28

Ryu, Kyungho, Dong-Hoon Jung, and Seong-Ook Jung. "Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector." IEEE Transactions on Circuits and Systems II: Express Briefs 61, no. 1 (January 2014): 1–5. http://dx.doi.org/10.1109/tcsii.2013.2291052.

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29

Kang, Kyung-Tae, Sang-Yun Kim, Sung Jin Kim, Dongsoo Lee, Sang-Sun Yoo, and Kang-Yoon Lee. "A 0.33–1 GHz Open-Loop Duty Cycle Corrector With Digital Falling Edge Modulator." IEEE Transactions on Circuits and Systems II: Express Briefs 65, no. 12 (December 2018): 1949–53. http://dx.doi.org/10.1109/tcsii.2018.2811412.

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30

Jalalifar, Majid, and Gyung-Su Byun. "A low-power low-jitter DLL with a differential closed-loop duty cycle corrector." Analog Integrated Circuits and Signal Processing 93, no. 1 (May 5, 2017): 149–55. http://dx.doi.org/10.1007/s10470-017-0984-5.

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31

Akram, Muhammad Abrar, Kyeong-Woo Kim, Jin-Hee Bae, and In-Chul Hwang. "All digital duty-cycle corrector for integrated phase noise improvement in phase-locked loop." Analog Integrated Circuits and Signal Processing 101, no. 3 (October 18, 2019): 641–49. http://dx.doi.org/10.1007/s10470-019-01554-3.

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32

Han, Sangwoo, and Jongsun Kim. "A CMOS Duty Cycle Corrector Using Dynamic Frequency Scaling for Coarse and Fine Tuning Adjustment." Journal of the Institute of Electronics Engineers of Korea 49, no. 10 (October 25, 2012): 142–47. http://dx.doi.org/10.5573/ieek.2012.49.10.142.

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33

Jiang, Jian Feng, Xi Jun Yang, Jian Guo Jiang, and Huai Gang Lei. "Research on High-Power Power Factor Corrector of Power Electronic Transformer." Advanced Materials Research 354-355 (October 2011): 1342–46. http://dx.doi.org/10.4028/www.scientific.net/amr.354-355.1342.

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Power electronic transformer (PET) which has a big potential application value in smart grid is an electrical power transformer device adopting power electronic converter and high frequency switch transformer. A new PET with power factor correctors (PFC) is proposed in this paper. Due to high power level of PET, PFC should have a high power level as well. Therefore, the multi-phase interleaved PFC is employed. The paper describes the one cycle control principle, proposes a current synthesis method based on IGBT current, and then analyses the relationship between ripple current and duty cycle of IGBT. In addition, the whole PFC system is simulated completely by means of Matlab/Simulink. In order to verify the theoretical analysis and simulation analysis, a four-phase interleaved PFC with a rated output power of 8.0kW is designed and implemented based on the an analog control chip. The obtained results show that the interleaved PFC by means of one cycle control and current synthesis is feasible, capable of reaching a good suppression effect of ripple current.

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34

Han, Sangwoo, and Jongsun Kim. "A 0.5-2.0 GHz Dual-Loop SAR-controlled Duty-Cycle Corrector Using a Mixed Search Algorithm." JSTS:Journal of Semiconductor Technology and Science 13, no. 2 (April 30, 2013): 152–56. http://dx.doi.org/10.5573/jsts.2013.13.2.152.

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35

Chung, Ching-Che, Duo Sheng, and Sung-En Shen. "A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology." IEICE Electronics Express 8, no. 15 (2011): 1245–51. http://dx.doi.org/10.1587/elex.8.1245.

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36

Hwang, Heejae, and Jongsun Kim. "A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links." IEICE Electronics Express 16, no. 19 (2019): 20190505. http://dx.doi.org/10.1587/elex.16.20190505.

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37

Jang, Young-Chan. "A digital phase corrector with a duty cycle detector and transmitter for a Quad Data Rate I/O scheme." IEICE Electronics Express 7, no. 3 (2010): 146–52. http://dx.doi.org/10.1587/elex.7.146.

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38

Chae, Joo-Hyung, Hyeongjun Ko, Jihwan Park, and Suhwan Kim. "A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, no. 4 (April 2019): 978–82. http://dx.doi.org/10.1109/tvlsi.2018.2883730.

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39

Tsai, Chih-Wei, Yu-Lung Lo, Chia-Chen Chang, Han-Ying Liu, Wei-Bin Yang, and Kuo-Hsing Cheng. "All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application." Japanese Journal of Applied Physics 56, no. 4S (January 30, 2017): 04CF02. http://dx.doi.org/10.7567/jjap.56.04cf02.

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40

Demartinos, Andreas-Christos, Andreas Tsimpos, Spyridon Vlassis, and George Souliotis. "Analogue feedback inverter based duty-cycle correction." Analog Integrated Circuits and Signal Processing 90, no. 3 (January 4, 2017): 711–16. http://dx.doi.org/10.1007/s10470-016-0921-z.

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41

Shi, Lei, Hong Kun He, Lin Bo Wang, Jin Jin Yang, and Qian Ni Feng. "A Duty Cycle Adjustment Strategy for Embedded Boost Power Factor Correction." Applied Mechanics and Materials 392 (September 2013): 682–86. http://dx.doi.org/10.4028/www.scientific.net/amm.392.682.

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The embedded boost power factor correction (PFC), which is realized by a storable duty cycle control method, has been verified that it can achieve good performance when the input voltage is standard sinusoidal signal. But the input current can not keep the good sinusoidal waveform all the time when the amplitude of the input voltage changes. In order to solve the problem, this paper presents a duty cycle adjustment strategy for embedded boost power factor correction. This strategy can adjust the duty cycle data synchronously when the amplitude of the input voltage changes. Its test results show that the adjustment strategy can achieve better performance to make the input current follow the shape and phase of the input voltage. The proposed duty cycle adjustment strategy can get the embedded boost power factor correction more effective and practical.

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42

Barcellona, Simone, Morris Brenna, Federica Foiadelli, Michela Longo, and Luigi Piegari. "Analysis of Ageing Effect on Li-Polymer Batteries." Scientific World Journal 2015 (2015): 1–8. http://dx.doi.org/10.1155/2015/979321.

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Lithium-ion batteries are a key technology for current and future energy storage in mobile and stationary application. In particular, they play an important role in the electrification of mobility and therefore the battery lifetime prediction is a fundamental aspect for successful market introduction. Numerous studies developed ageing models capable of predicting battery life span. Most of the previous works compared the effect of the ageing factors to a battery’s cycle life. These cycles are identical, which is not the case for electric vehicles applications. Indeed, most of the available information is based on results from laboratory testing, under very controlled environments, and using ageing protocols, which may not correctly reflect the actual utilization. For this reason, it is important to link the effect of duty cycles with the ageing of the batteries. This paper proposes a simple method to investigate the effect of the duty cycle on the batteries lifetime through tests performed on different cells for different kinds of cycle. In this way, a generic complex cycle can be seen as a composition of elemental cycles by means of Rainflow procedures. Consequently, the ageing due to any cycle can be estimated starting from the knowledge of simpler cycles.

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43

Yoo, C., C. Jeong, and J. Kih. "Open-loop full-digital duty cycle correction circuit." Electronics Letters 41, no. 11 (2005): 635. http://dx.doi.org/10.1049/el:20050776.

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44

Shibib, Khalid, Mohammed Munshid, Mohammed Abdul-Rayyak, and Luma Salman. "Transient analytical solution of temperature distribution and fracture limits in pulsed solid-state laser rod." Thermal Science 21, no. 3 (2017): 1213–22. http://dx.doi.org/10.2298/tsci141011090s.

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The exact analytical solution of axis-symmetry transient temperature and Tresca failure stress in pulsed mode solid-state laser rod is derived using integral transform method. The result obtained from this work is compared with previously published data and good agreement is found. The effect of increasing period is studied, and it is found that at constant pulse width as the period is increased, the allowable pumping power is increased too. Furthermore, the effect of changing pulse width with a constant period is studied, and it is found that as the pulse width is increased, the allowable pumping power is decreased. The effect of duty cycle is studied also and it is found that as duty cycle is increased the allowable pumping power is decreased. This work permits proper selection of pulse width, period and duty cycle to avoid laser rod fracture while obtaining maximum output laser power in the designing of laser system. <br><br><font color="red"><b> This article has been corrected. Link to the correction <u><a href="http://dx.doi.org/10.2298/TSCI170731162E">10.2298/TSCI170731162E</a><u></b></font>

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45

Ogawa, Toru, and Kenji Taniguchi. "A 50% duty-cycle correction circuit for PLL output." Electronics and Communications in Japan (Part II: Electronics) 86, no. 2 (January 15, 2003): 1–8. http://dx.doi.org/10.1002/ecjb.10085.

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46

NAM, J. J. "An All-Digital CMOS Duty Cycle Correction Circuit with a Duty-Cycle Correction Range of 15-to-85% for Multi-Phase Applications." IEICE Transactions on Electronics E88-C, no. 4 (April 1, 2005): 773–77. http://dx.doi.org/10.1093/ietele/e88-c.4.773.

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47

Shin, Dongsuk, Soo-Won Kim, and Chulwoo Kim. "Wide frequency range duty cycle correction circuit for DDR interface." IEICE Electronics Express 5, no. 8 (2008): 254–59. http://dx.doi.org/10.1587/elex.5.254.

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48

Jang, Seong-Jin, Young-Hyun Jun, Jae-Goo Lee, and Bai-Sun Kong. "ASMD with duty cycle correction scheme for high-speed DRAM." Electronics Letters 37, no. 16 (2001): 1004. http://dx.doi.org/10.1049/el:20010717.

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49

Jang, Y. C., S. J. Bae, and H. J. Park. "CMOS digital duty cycle correction circuit for multi-phase clock." Electronics Letters 39, no. 19 (2003): 1383. http://dx.doi.org/10.1049/el:20030908.

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50

Zuo, Shi, Jianzhong Zhao, and Yumei Zhou. "A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme." Electronics 10, no. 7 (March 29, 2021): 805. http://dx.doi.org/10.3390/electronics10070805.

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This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μμW at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz.

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