Relevant bibliographies by topics / Dynamic comparator

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Dynamic comparator'

Author: Grafiati
Published: 4 June 2021
Last updated: 16 June 2025

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Journal articles on the topic "Dynamic comparator"

1

Song, Bangyu, and Yi Zhao. "A comparative research of innovative comparators." Journal of Physics: Conference Series 2221, no. 1 (2022): 012021. http://dx.doi.org/10.1088/1742-6596/2221/1/012021.

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Abstract This paper studies four novel design comparators and gives a detailed analysis and summary of them. edge-pursuit comparator (EPC) improved energy efficiency and noise over conventional comparators by a circuit loop consisting of numbers of delay units. The triple-tail fully dynamic comparator minimizes the comparator’s total delay time and enhances the sample rate. The dynamic bias architecture of the double-tail latch-type comparator can provide a relatively high voltage gain while ensuring a low power consumption by stabilizing the static operating point. It also has advantages over
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Liu, Yuchuan. "An Review of Dynamic CMOS Comparators." Highlights in Science, Engineering and Technology 44 (April 13, 2023): 113–20. http://dx.doi.org/10.54097/hset.v44i.7273.

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CMOS dynamic comparators contributes a major role on the implementation of mixed signal successive approximation register (SAR) type of analog to digital converters (ADC). High precision, dynamic range, low voltage operation, high speed, low power consumption, reliability and offset voltage are the critical factors to be considered while designing CMOS dynamic comparators. This paper reviewed the performance of some popular dynamic CMOS comparators such as StrongARM latch comparator, double- tail dynamic-latched comparator, dynamic bias comparator and triple stage somparator.
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Du, Chengze. "Performance analysis of high-speed, low-power comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 292–301. http://dx.doi.org/10.54097/hset.v27i.3770.

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This article mainly presents a summary of development of dynamic comparators and the optimization to conventional comparator in recent years. By comparing the design of two different comparators, the design method of less power consumption, high speed or small delay, and low input referred noise can be concluded. The Dynamic comparator is designed to have small delay and less power consumption compared with two-stage comparator. The dynamic-bias comparator spends less power for operation the circuit compared with double-tail comparator. The FIA comparator operates under the controlling of logi
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Sun, Yuan. "A brief review on novel comparator design." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 418–27. http://dx.doi.org/10.54097/hset.v27i.3785.

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This paper reviewed three different kinds of comparators to show their respective advantage range. The Dynamic-bias comparator extends its pre-amplifier part with a capacitor and has a smaller power with a smaller input referred noise than Elzakker’s comparator but has a higher delay. The Quad high-speed comparator introduced the Quad into the comparator’s latch part. It has a lower delay and also make the calculation of the output voltage easier for it only depends on the skew factor. The low-power dynamic bias has a cross-couple device on its pre-amplifier part which slows down the discharge
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Li, Yichen. "The Performance analysis of Low-Power High-Speed comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 72–82. http://dx.doi.org/10.54097/hset.v27i.3723.

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Comparators are the essential block for planning high-speed analog and. This paper presents three inventive designs of the comparators in recent years. First, innovated by classic two-stage comparator, the comparator with a transconductance-enhanced latching stage is suitable for low-power, high-speed operation. Second, triple-latch feed-forward(TLFF) fully dynamic comparator guarantees the maximum possible gain and speed for a specific power across the entire input range. Finally, the comparator with a dynamic floating inverter maximizes efficiency by reusing the current.
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Sharmila Vallem. "Design of a High speed Low Low-Power Latched Comparator for Medical Implants." Communications on Applied Nonlinear Analysis 32, no. 8s (2025): 87–104. https://doi.org/10.52783/cana.v32.3610.

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The latched dynamic comparator is a fundamental component in all ADC architectures. Thermal effects, kickback, and offset voltage influence it. The kickback noise of the latched comparator in medical implant ADCs can impact the resolution, precision, and settling period. The current study examines a latching comparator that aims to reduce kickback noise. This research presents a low-power latched comparator for medical implants functioning at 1 V. This investigation implements a comparator utilising the sampling switching approach. This method successfully minimises kick-back noise and clockin
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Fan, Jiangfeng. "Performance Analysis of Low-Power CMOS Dynamic Comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 62–71. http://dx.doi.org/10.54097/hset.v27i.3722.

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This paper studies four structures of CMOS dynamic comparators introduced in recent years. Based on conventional double-tail comparator, a comparator with a tail capacitor prevents output nodes of preamplifier from completely discharging to reduce energy consumption. Another comparator with a cross-coupled pairs achieves the same purpose of the first design. A comparator adds a floating inverter amplifier (FIA) to realize both dynamic bias and current reuse, achieve low energy consumption and be insensitive to the VCM. The triple-latch feed-forward (TLFF) comparator decreases delay conspicuous
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Du, Qinghang. "Analysis and comparison of several types of low-power, low offset comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 120–32. http://dx.doi.org/10.54097/hset.v27i.3728.

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This paper studies several excellent works of comparator constructions of comparators and compares them with the Double-tail latch-type comparator. Based on the Elzakker comparator, the comparator with a dynamic bias reduced the use of energy by partly discharging the preamplifier's output nodes. Edge-Pursuit Comparator(EPC) demonstrates a new approach to reducing energy consumption by automatic energy optimization. Apart from the designs that optimize energy consumption. Low-Noise Self-Calibrating Dynamic Comparator provides the low-offset feature while in relatively low power consumption.
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Gajawada, Varun sai, and Mohana J. "Construction of CMOS Logic Double Tail Comparator for Lower Power Consumption Compared with Dynamic Comparator." ECS Transactions 107, no. 1 (2022): 13873–85. http://dx.doi.org/10.1149/10701.13873ecst.

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The aim of the study is to construct and analyze innovative CMOS based double tail comparators and compare them with a dynamic comparator using VLSI technology. Materials and methods: The comparator is designed by using the tanner tool for simulation and verification. By varying the length of a transistors the power values were obtained. There are two groups in the study. CMOS double tail comparator is the experimental group and dynamic tail comparator is the control group. This experiment is performed for 20 different values of length. Results: The power consumption of a CMOS logic double tai
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Wang, Sudong. "Review of Four Improving Designs of Dynamic Latch Comparator." Highlights in Science, Engineering and Technology 44 (April 13, 2023): 129–37. http://dx.doi.org/10.54097/hset.v44i.7287.

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In this paper, four disparate designs of dynamic latch comparators are discussed consecutively. By improving the design of the pre-amplifier stage, the double tail comparator provides a good power-speed trade-off. Further, Differential pair amplifiers are implemented in the second design, which has better comparison speed and energy dissipation. Next, a bulk-driven structure is employed on the comparator design to improve the comparison speed. Finally, a dynamic comparator utilizes a floating reservoir capacitor and a positive feedback bulk structure is introduced to achieve higher energy effi
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Dissertations / Theses on the topic "Dynamic comparator"

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Hedayati, Raheleh. "A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology." Thesis, Linköpings universitet, Elektroniska komponenter, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72767.

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In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converter in medical application such as pacemaker. The demand for long battery life-time in these applications poses the requirement for designing ultra-low power SAR ADCs. This thesis work initially investigates and compares different structures of SAR control logics including the conventional structures and the delay line based controller. Additionally, it focuses on selection of suitable dynamic comparator architecture.  Based on this analysis, dynamic two-stage comparator is select
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Muralidharan, Vaishali. "Logic Encryption Using Dynamic Keys." University of Cincinnati / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1613751124204643.

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Camurani, Andrea. "Metodi di calibrazione e sistema di misura di Timing Mismatch per un convertitore RFDAC realizzato con architettura a current steering in tecnologia FinFET." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2020. http://amslaurea.unibo.it/20229/.

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Il presente lavoro di tesi, svolto presso Xilinx in Irlanda, è focalizzato alla calibrazione e misura delle non idealità dinamiche presenti nei convertitori digitali-analogici (Digital to Time Converter) a radio frequenza, con architettura a Current-Steering. Questa architettura, controllata da una logica combinata di bit termometrici (6 MSB) e bit binari (10 LSB), permette di avere alte prestazioni di velocità. Le non idealità consistono nel disallineamento temporale di questi bit, che aumentano tanto più la frequenza del dato in ingresso aumenta. La necessità di metodi di calibrazione per
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Ganguli, Ameya Vivekanand. "Cmos Design of an 8-bit 1MS/s Successive Approximation Register ADC." DigitalCommons@CalPoly, 2019. https://digitalcommons.calpoly.edu/theses/2074.

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Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance. This thesis p
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BONIFAZI, MAURIZIO. "Analog circuits design for cellular neural network." Doctoral thesis, Università degli Studi di Roma "Tor Vergata", 2008. http://hdl.handle.net/2108/705.

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Il paradigma delle Reti Neurali Artificiali (ANN) consiste nell’applicazione del modello neurale “biologico” per la risoluzione di problemi che spesso sono troppo complessi per un’architettura di Von Neumann. La letteratura offre differenti approcci per l’implementazione di ANN. Qualche implementazione è di tipo software, altre sono soluzioni circuitali come circuiti digitali full-custom o FPGA (Field Programmable Gate Array), come pure circuiti analogici, e il tipo di implementazione di certo dipende dal tempo di esecuzione adeguato al tipo di applicazione. Questa tesi riguarda la progettaz
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Fuentes, Alejandro. "Cultural diversity and indigenous peoples' land claims: argumentative dynamics and jurisprudential approach in the Americas." Doctoral thesis, Università degli studi di Trento, 2012. https://hdl.handle.net/11572/367661.

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The present study is divided in two differentiable but conceptually interrelated sections. Within the first section (Chapters I, II, and III), the focus is on the assessment of the argumentative logic behind the multiculturalist proposal for equally divided societies, among equally positioned ethno-cultural groups. A critical and analytical review of the multiculturalist argumentative constructions shows that its justification lies on the dogmatic assumption of the equal worth or dignity of cultures, which is ontologically incorrect. Cultures cannot be axiologically compared. Instead, this stu
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Fuentes, Alejandro. "Cultural diversity and indigenous peoples' land claims: argumentative dynamics and jurisprudential approach in the Americas." Doctoral thesis, University of Trento, 2012. http://eprints-phd.biblio.unitn.it/767/1/AF_Doctoral_Thesis.pdf.

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The present study is divided in two differentiable but conceptually interrelated sections. Within the first section (Chapters I, II, and III), the focus is on the assessment of the argumentative logic behind the multiculturalist proposal for equally divided societies, among equally positioned ethno-cultural groups. A critical and analytical review of the multiculturalist argumentative constructions shows that its justification lies on the dogmatic assumption of the equal worth or dignity of cultures, which is ontologically incorrect. Cultures cannot be axiologically compared. Instead, this stu
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Benedetto, Alessandra. "Pre-contractual agreements in international commercial contracts: legal dynamics and commercial expediency." Doctoral thesis, Universita degli studi di Salerno, 2012. http://hdl.handle.net/10556/1302.

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2010 - 2011<br>La materia dei contratti internazionali è andata acquisendo sempre maggiore importanza e diffusione negli ultimi anni. Questo fatto costituisce, in qualche modo, la conseguenza dei profondi cambiamenti che hanno interessato il mondo delle relazioni commerciali. Oggigiorno, grazie alla creazione di un mercato unico europeo e, soprattutto, quale conseguenza diretta della globalizzazione, la gran parte dei businessmen tendono a spingere i propri affari ben oltre i confini nazionali, quando non accantonano addirittura la dimensione “geografica” e si avvalgono dei più moderni strume
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CANTELE, FRANCESCA ORTENSIA. "THE IMPACT OF Α-SYNUCLEIN ON MICROTUBULES:FROM DYNAMICS TO ULTRASTRUCTURE." Doctoral thesis, Università degli Studi di Milano, 2018. http://hdl.handle.net/2434/579716.

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α-Synuclein is a presynaptic protein supposed to be involved in the control of neuronal synapse functions. It is widely expressed in brain tissue and associated to Parkinson's disease. When free in the cytoplasm, α-synuclein is unstructured, while it adopts a α-helical conformation when bound to vesicles. Its variable structure allows α-synuclein to interact with multiple partners and makes difficult to understand its physiological role, which remains elusive despite decades of intense study. Here, we looked at the interaction between α-synuclein and microtubules, using both wild type and muta
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Matěj, Jan. "Návrh a optimalizace spínaného komparátoru v 250 nm CMOS technologii." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-318180.

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This diploma thesis deals with design methods and optimization techniques of dynamic latched comparators. It compares latched and continuous comparators and describes their principle. Then it analyses three popular latched comparator structures with respect to offset, speed and kickback noise. It shows practical comparator design focused on offset precision.
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Books on the topic "Dynamic comparator"

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Analysis of Dynamic Latched Comparator with Reduced Delay and Energy for High Speed ADCs. ASDF International, 2017.

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The dynamics of economic growth: Policy insights from comparatve analyses in Asia. Edward Elgar, 2013.

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Book chapters on the topic "Dynamic comparator"

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Sowmya, K. B., and Meghashree Doddamani. "Swift Double-Tail Dynamic Comparator." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-1906-0_41.

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Soram, Julia, and Shyam Akashe. "A Relative Investigation of TIQ Comparator and Dynamic Latched Comparator." In Springer Proceedings in Physics. Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2367-2_37.

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Ramkaj, Athanasios T., Marcel J. M. Pelgrom, Michiel S. J. Steyaert, and Filip Tavernier. "Ultrahigh-Speed High-Sensitivity Dynamic Comparator." In Analog Circuits and Signal Processing. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-22709-7_4.

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Gandhi, Priyesh P., and Niranjan M. Devashrayee. "Low-Offset High-Speed CMOS Dynamic Voltage Comparator." In Advances in Intelligent Systems and Computing. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-5903-2_23.

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Kushwaha, Ritesh Kumar, Prem Kumar, and P. Karuppanan. "Study and Analysis of Low Power Dynamic Comparator." In Lecture Notes in Electrical Engineering. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9775-3_40.

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Pravalika, P., P. Narendra, T. Srilakshmi, Ch Bhavani, and P. Kishore Kumar. "The Development of a CMOS Logic Double Tail Comparator that uses Less Power than a Dynamic Comparator." In Recent Developments in Microbiology, Biotechnology and Pharmaceutical Sciences. CRC Press, 2025. https://doi.org/10.1201/9781003618140-96.

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Bandla, Kasi, Atharva Dinakar, and Dipankar Pal. "A Novel Dynamic Latch Comparator Design and Analysis for ADCs." In Intelligent Computing and Communication. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-1588-0_11.

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Kunal, Anurag Yadav, and Subodh Wairya. "Design and Analysis of High-Speed Low-Power Dynamic Comparator." In Intelligent Systems and Smart Infrastructure. CRC Press, 2023. http://dx.doi.org/10.1201/9781003357346-13.

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Singh, Tejender, and Suman Lata Tripathi. "Design and analysis of a shared charged dynamic latch comparator." In Intelligent Circuits and Systems. CRC Press, 2021. http://dx.doi.org/10.1201/9781003129103-60.

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Murali Krishna, G., G. Karthick, and N. Umapathi. "Design of Dynamic Comparator for Low-Power and High-Speed Applications." In Lecture Notes in Electrical Engineering. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-7961-5_110.

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Conference papers on the topic "Dynamic comparator"

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Sundari T, Jaspar Vinitha, Lavanya E, Kiruthika S, and Purnitha T. "Low power Energy efficient Dynamic Latched Comparator." In 2024 5th IEEE Global Conference for Advancement in Technology (GCAT). IEEE, 2024. https://doi.org/10.1109/gcat62922.2024.10924077.

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Sundari T, Jaspar Vinitha, Lavanya E, Kiruthika S, and Purnitha T. "Performance optimization techniques of dynamic latched comparator." In 2024 5th IEEE Global Conference for Advancement in Technology (GCAT). IEEE, 2024. https://doi.org/10.1109/gcat62922.2024.10924082.

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Jiang, Jiaquan, Qingsen Wu, Yuan Wang, et al. "Automated Design of a Strong-ARM Dynamic Comparator." In 2024 2nd International Symposium of Electronics Design Automation (ISEDA). IEEE, 2024. http://dx.doi.org/10.1109/iseda62518.2024.10617721.

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Sai, Pala Lakshman, V. Surya Prathik, M. Roopa Rajan, and Kirti S. Pande. "Delay-Optimized High-Speed Dynamic Comparator with Temperature Compensation." In 2025 8th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech). IEEE, 2025. https://doi.org/10.1109/iementech65115.2025.10959548.

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R, Pooja C., Panwala Fenil Chetankumar, and Ravi H. K. "Design and Analysis of Two-Stage Comparator with Telescopic Amplifier and Dynamic Comparator for Low-Voltage Applications." In 2025 3rd International Conference on Smart Systems for applications in Electrical Sciences (ICSSES). IEEE, 2025. https://doi.org/10.1109/icsses64899.2025.11009925.

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Conrad, Joschua, John Kauffman, Simon Wilhelmstatter, Rohan Asthana, Vasileios Belagiannis, and Maurits Ortmanns. "Confidence Estimation and Boosting for Dynamic-Comparator Transient-Noise Analysis." In 2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS). IEEE, 2024. http://dx.doi.org/10.1109/newcas58973.2024.10666354.

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Kannaujiya, Aryan, Vipul Sahu, and Ambika Prasad Shah. "High-Performance Stacked Dynamic Comparator for Analog to Digital Converters." In 2024 28th International Symposium on VLSI Design and Test (VDAT). IEEE, 2024. http://dx.doi.org/10.1109/vdat63601.2024.10705708.

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Zhang, Hejiu, Xinrui Yao, Ningmei Yu, and Nan Lv. "A Low-Noise Energy-Efficient Double-Tail Dynamic Latch Comparator." In 2024 9th International Conference on Integrated Circuits and Microsystems (ICICM). IEEE, 2024. https://doi.org/10.1109/icicm63644.2024.10814241.

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Santosh, T., G. Swathi, J. Likitha, B. Poojitha, and B. Madhuri. "Optimized Dynamic Comparator Design for Enhanced Speed and Power Efficiency." In 2025 Fourth International Conference on Smart Technologies, Communication and Robotics (STCR). IEEE, 2025. https://doi.org/10.1109/stcr62650.2025.11019620.

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Agustin, Jazzmyne Rona M., Harreez M. Villaruz, Nieva M. Mapula, and Gene Fe P. Palencia. "High Speed Low Power Dynamic CMOS Comparator for SAR ADCs." In TENCON 2024 - 2024 IEEE Region 10 Conference (TENCON). IEEE, 2024. https://doi.org/10.1109/tencon61640.2024.10903011.

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