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Dissertations / Theses on the topic 'Dynamic comparator'

Author: Grafiati

Published: 4 June 2021

Last updated: 26 July 2025

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1

Hedayati, Raheleh. "A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology." Thesis, Linköpings universitet, Elektroniska komponenter, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72767.

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In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converter in medical application such as pacemaker. The demand for long battery life-time in these applications poses the requirement for designing ultra-low power SAR ADCs. This thesis work initially investigates and compares different structures of SAR control logics including the conventional structures and the delay line based controller. Additionally, it focuses on selection of suitable dynamic comparator architecture. Based on this analysis, dynamic two-stage comparator is select

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2

Muralidharan, Vaishali. "Logic Encryption Using Dynamic Keys." University of Cincinnati / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1613751124204643.

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Camurani, Andrea. "Metodi di calibrazione e sistema di misura di Timing Mismatch per un convertitore RFDAC realizzato con architettura a current steering in tecnologia FinFET." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2020. http://amslaurea.unibo.it/20229/.

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Il presente lavoro di tesi, svolto presso Xilinx in Irlanda, è focalizzato alla calibrazione e misura delle non idealità dinamiche presenti nei convertitori digitali-analogici (Digital to Time Converter) a radio frequenza, con architettura a Current-Steering. Questa architettura, controllata da una logica combinata di bit termometrici (6 MSB) e bit binari (10 LSB), permette di avere alte prestazioni di velocità. Le non idealità consistono nel disallineamento temporale di questi bit, che aumentano tanto più la frequenza del dato in ingresso aumenta. La necessità di metodi di calibrazione per

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4

Ganguli, Ameya Vivekanand. "Cmos Design of an 8-bit 1MS/s Successive Approximation Register ADC." DigitalCommons@CalPoly, 2019. https://digitalcommons.calpoly.edu/theses/2074.

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Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance. This thesis p

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5

BONIFAZI, MAURIZIO. "Analog circuits design for cellular neural network." Doctoral thesis, Università degli Studi di Roma "Tor Vergata", 2008. http://hdl.handle.net/2108/705.

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Il paradigma delle Reti Neurali Artificiali (ANN) consiste nell’applicazione del modello neurale “biologico” per la risoluzione di problemi che spesso sono troppo complessi per un’architettura di Von Neumann. La letteratura offre differenti approcci per l’implementazione di ANN. Qualche implementazione è di tipo software, altre sono soluzioni circuitali come circuiti digitali full-custom o FPGA (Field Programmable Gate Array), come pure circuiti analogici, e il tipo di implementazione di certo dipende dal tempo di esecuzione adeguato al tipo di applicazione. Questa tesi riguarda la progettaz

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Fuentes, Alejandro. "Cultural diversity and indigenous peoples' land claims: argumentative dynamics and jurisprudential approach in the Americas." Doctoral thesis, Università degli studi di Trento, 2012. https://hdl.handle.net/11572/367661.

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The present study is divided in two differentiable but conceptually interrelated sections. Within the first section (Chapters I, II, and III), the focus is on the assessment of the argumentative logic behind the multiculturalist proposal for equally divided societies, among equally positioned ethno-cultural groups. A critical and analytical review of the multiculturalist argumentative constructions shows that its justification lies on the dogmatic assumption of the equal worth or dignity of cultures, which is ontologically incorrect. Cultures cannot be axiologically compared. Instead, this stu

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Fuentes, Alejandro. "Cultural diversity and indigenous peoples' land claims: argumentative dynamics and jurisprudential approach in the Americas." Doctoral thesis, University of Trento, 2012. http://eprints-phd.biblio.unitn.it/767/1/AF_Doctoral_Thesis.pdf.

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The present study is divided in two differentiable but conceptually interrelated sections. Within the first section (Chapters I, II, and III), the focus is on the assessment of the argumentative logic behind the multiculturalist proposal for equally divided societies, among equally positioned ethno-cultural groups. A critical and analytical review of the multiculturalist argumentative constructions shows that its justification lies on the dogmatic assumption of the equal worth or dignity of cultures, which is ontologically incorrect. Cultures cannot be axiologically compared. Instead, this stu

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8

Benedetto, Alessandra. "Pre-contractual agreements in international commercial contracts: legal dynamics and commercial expediency." Doctoral thesis, Universita degli studi di Salerno, 2012. http://hdl.handle.net/10556/1302.

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2010 - 2011<br>La materia dei contratti internazionali è andata acquisendo sempre maggiore importanza e diffusione negli ultimi anni. Questo fatto costituisce, in qualche modo, la conseguenza dei profondi cambiamenti che hanno interessato il mondo delle relazioni commerciali. Oggigiorno, grazie alla creazione di un mercato unico europeo e, soprattutto, quale conseguenza diretta della globalizzazione, la gran parte dei businessmen tendono a spingere i propri affari ben oltre i confini nazionali, quando non accantonano addirittura la dimensione “geografica” e si avvalgono dei più moderni strume

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9

CANTELE, FRANCESCA ORTENSIA. "THE IMPACT OF Α-SYNUCLEIN ON MICROTUBULES:FROM DYNAMICS TO ULTRASTRUCTURE." Doctoral thesis, Università degli Studi di Milano, 2018. http://hdl.handle.net/2434/579716.

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α-Synuclein is a presynaptic protein supposed to be involved in the control of neuronal synapse functions. It is widely expressed in brain tissue and associated to Parkinson's disease. When free in the cytoplasm, α-synuclein is unstructured, while it adopts a α-helical conformation when bound to vesicles. Its variable structure allows α-synuclein to interact with multiple partners and makes difficult to understand its physiological role, which remains elusive despite decades of intense study. Here, we looked at the interaction between α-synuclein and microtubules, using both wild type and muta

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10

Matěj, Jan. "Návrh a optimalizace spínaného komparátoru v 250 nm CMOS technologii." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-318180.

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This diploma thesis deals with design methods and optimization techniques of dynamic latched comparators. It compares latched and continuous comparators and describes their principle. Then it analyses three popular latched comparator structures with respect to offset, speed and kickback noise. It shows practical comparator design focused on offset precision.

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11

Quo, Chang Feng. "Reverse engineering homeostasis in molecular biological systems." Thesis, Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/49144.

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This dissertation is an initial study of how modern engineering control may be applied to reverse engineer homeostasis in metabolic pathways using high-throughput biological data. This attempt to reconcile differences between engineering control and biological homeostasis from an interdisciplinary perspective is motivated not only by the observation that robust behavior in metabolic pathways resembles stabilized dynamics in controlled systems, but also by the challenges forewarned in achieving a true meeting of minds between engineers and biologists. To do this, a comparator model is developed

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12

SPREAFICO, MARTA. "Institutions and Growth: The Experience of the Former Soviet Union Economies." Doctoral thesis, Università Cattolica del Sacro Cuore, 2011. http://hdl.handle.net/10280/1113.

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Organizzata in tre saggi, questa tesi si pone l’obiettivo di consentire una migliore comprensione del legame tra crescita e istituzioni, e dei meccanismi attraverso cui gli assetti istituzionali possono condizionare i sentieri economici. Riconoscendo, sulla base di considerazioni storiche, il potere esemplificativo delle ex Repubbliche Socialiste Sovietiche e della loro comune esperienza passata, questo lavoro fornisce, da un lato, una struttura empirica di riferimento per esaminare l’impatto sulla performance economica di un insieme di istituzioni, concretamente legate al funzionamento dell’

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SPREAFICO, MARTA. "Institutions and Growth: The Experience of the Former Soviet Union Economies." Doctoral thesis, Università Cattolica del Sacro Cuore, 2011. http://hdl.handle.net/10280/1113.

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Organizzata in tre saggi, questa tesi si pone l’obiettivo di consentire una migliore comprensione del legame tra crescita e istituzioni, e dei meccanismi attraverso cui gli assetti istituzionali possono condizionare i sentieri economici. Riconoscendo, sulla base di considerazioni storiche, il potere esemplificativo delle ex Repubbliche Socialiste Sovietiche e della loro comune esperienza passata, questo lavoro fornisce, da un lato, una struttura empirica di riferimento per esaminare l’impatto sulla performance economica di un insieme di istituzioni, concretamente legate al funzionamento dell’

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14

Senapati, Prasanta Kumar. "Low power dynamic comparator design." Thesis, 2014. http://ethesis.nitrkl.ac.in/6386/1/E-21.pdf.

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In many applications there is a growing demand for the development of low voltage and low power circuits and systems. Low power consumption is of great interest because it increases the battery lifetime. One of the main building blocks in many applications is the analogue-to-digital converter (ADC) which serves as an interface between the analogue world and the digital processing unit. In all these designs the comparator of the ADC, which is one the most power hungry blocks, is always on. In order to reduce the power consumption of the ADC it is possible to turn the comparator off when the dec

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15

Jain, Nitin. "Low Power Dynamic Comparator Design Using Variable Resistor." Thesis, 2015. http://ethesis.nitrkl.ac.in/7785/1/2015_Mtech_Low_Jain.pdf.

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In today's reality, where claim for versatile battery functioned gadgets is expanding, a noteworthy plunge is given in the direction of low power approaches for rapid applications. To reduce the feature size is the cause to reduce the power. The comparator is one of the most versatile circuits in analog circuit design. It serves as an input stage of most of the ADCs. The comparator has noteworthy effect on the execution of the objective application which depends on the architecture and form of it. In this thesis, a clock based comparator is analysed in terms of average power dissipation, delay

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16

Wu, Po-Han, and 吳柏翰. "Low Power Flash ADC With a Gm-enhancement Low-Voltage Dynamic Comparator." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/98191663524753217091.

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碩士<br>國立東華大學<br>電機工程學系<br>103<br>Low supply voltage is a good way to achieve low power consumption. Besides, there are many applications about high-speed low-resolution analog-to-digital converter. For example: Disk Driver Front-end、High-speed Backplane、Ultrawideband Receiver and Millimeter-wave Receiver. The feature of ultra-low power is as needed as possible for portable devices. A Gm-enhancement low-voltage dynamic comparator is proposed. The speed can achieve 100 MHz at 0.6V in 0.18um CMOS process. And we realize a low-voltage low-power Flash ADC in UMC 180nm CMOS Logic &; Mixed Mode 1

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17

Wu, Hsin-Long, and 吳欣龍. "IC Design and Implementation of Fast Tagged Sorter and Dynamic 64-Bit Comparator." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/34906629714669250685.

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碩士<br>國立中山大學<br>電機工程學系研究所<br>88<br>Three different topics associated with their respective applications are proposed in this thesis. The first application is the implementation of a fast tagged sorter. A novel and high-speed realization of the tagged sorting algorithm is presented. Meanwhile, the problems to detect whether the queue is empty or full is also resolved without increasing any hardware cost. The second topic is focused on the implementation of a fast dynamic 64-bit comparator with small transistor count. The entire 64-bit comparator is composed of equality comparators and ze

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18

Velagaleti, Silpakesav. "A Novel High Speed Dynamic Comparator with Low Power Dissipation and Low Offset." Thesis, 2009. http://ethesis.nitrkl.ac.in/1376/1/207EC211_THESIS.pdf.

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A new fully differential CMOS dynamic comparator using positive feedback suitable for pipeline A/D converters with low power dissipation, low offset, low noise and high speed is proposed. Inputs are reconfigured from typical differential pair comparator such that near equal current distribution in the input transistors can be achieved for a meta stable point of the comparator. Restricted signal swing clock for the tail current is also used to ensure constant currents in the differential pairs. Nearly 18mV offset voltage is easily achieved with the proposed structure making it favorable for fla

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19

Yamamoto, Kentaro. "A 1-1-1-1 MASH Delta-Sigma ADC using Dynamic Comparator-based OTAs." Thesis, 2012. http://hdl.handle.net/1807/34974.

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Low intrinsic transistor gain in nanometer CMOS technologies imposes implementation difficulties of switched-capacitor (SC) circuits based on a conventional OTA used in delta-sigma ADCs. Zero-crossing-based circuits (ZCBCs) have been proposed as replacements for conventional OTAs in SC circuits, but the efficiency of existing ZCBC-based delta-sigma ADCs trails that of state-of-art conventional delta-sigma ADCs. The dynamic comparator-based OTA (DCBOTA) is a novel circuit block that performs an equivalent operation of a conventional OTA in a SC circuit by repeatedly detecting the input (Vg) s

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20

Bhattacharyya, Prasun. "Design of a novel high speed dynamic comparator with low power dissipation for high speed ADCs." Thesis, 2011. http://ethesis.nitrkl.ac.in/2770/1/209EC2123_PRASUN_BHATTACHARYYA_c.pdf.

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A new CMOS dynamic comparator using dual input single output differential amplifier as latch stage suitable for high speed analog-to-digital converters with High Speed, low power dissipation and immune to noise than the previous reported work is proposed. Backto- back inverter in the latch stage is replaced with dual-input single output differential amplifier. This topology completely removes the noise that is present in the input. The structure shows lower power dissipation and higher speed than the conventional comparators. The circuit is simulated with 1V DC supply voltage and 250 MHz clo

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21

Kuo, Bo-Jyun, and 郭柏均. "Implementation of Low Voltage, High Speed Dynamic Comparators." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/34201778882532732853.

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碩士<br>國立交通大學<br>電子研究所<br>101<br>This thesis presents two low voltage, high speed dynamic comparators. It improves the core circuit “latch architecture”, so the comparators can operate at low supply voltage. The comparators have the large enough overdrive voltage to keep the transconductance, so the comparators can maintain the high speed operation.And realizing comparators in 65nm CMOS. The first comparator operate at supply voltage is 0.6V, the operating speed is 1GHz, and the input referred offset(1&;#1049434;) is 6mV, the input referred noise(1&;#1049434;) is 0.65mV, and the sensitivity is

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22

GUPTA, DIKSHA. "SIMULATION AND ANALYSIS OF FLASH ADC USING DIFFERENT DYNAMIC COMPARATORS." Thesis, 2017. http://dspace.dtu.ac.in:8080/jspui/handle/repository/16277.

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Designing ADC is a new challenge these days owing to the rapid growth of digital technology. Digital signals impart several inherent advantages and are most preferred these days than their analog counterpart. The conversion of analog signal to digital signal is done by ADC. Flash ADC is fastest of all other ADCs and is used for high speed purposes. Comparator is the main building block of ADC. Dynamic comparators provide high speed, low power dissipation and are more area efficient as compared to pre-amplifier comparators. In this thesis, comparison of flash ADC using different dynamic comp

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23

Řehulka, Filip. "Komparace efektivity rozcvičení florbalistů." Master's thesis, 2017. http://www.nusl.cz/ntk/nusl-367828.

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Názevpráce Komparace efektivity rozcvičení florbalistů Cíle práce Zjistit, které z vybraných druhů rozcvičení má největší vliv na rychlostní výkon florbalisty. Metoda Data pro komparaci efektivity rozcvičení budou dosažena pomocí srovnávací studie, kdy probandi podstoupí různé druhy rozcvičení. Probandi budou testováni testovou baterií, která je součástí kondičních testů české reprezentace. Využity budou fotobuňky zapůjčené od České florbalové unie. Výsledky Zobrazují efektivitu jednotlivých druhů rozcvičení florbalistů. Klíčová slova Rozcvičení, dynamický strečink, florbal, experiment, kompar

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