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Journal articles on the topic 'Dynamic comparator'

Author: Grafiati

Published: 4 June 2021

Last updated: 26 July 2025

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1

Song, Bangyu, and Yi Zhao. "A comparative research of innovative comparators." Journal of Physics: Conference Series 2221, no. 1 (2022): 012021. http://dx.doi.org/10.1088/1742-6596/2221/1/012021.

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Abstract This paper studies four novel design comparators and gives a detailed analysis and summary of them. edge-pursuit comparator (EPC) improved energy efficiency and noise over conventional comparators by a circuit loop consisting of numbers of delay units. The triple-tail fully dynamic comparator minimizes the comparator’s total delay time and enhances the sample rate. The dynamic bias architecture of the double-tail latch-type comparator can provide a relatively high voltage gain while ensuring a low power consumption by stabilizing the static operating point. It also has advantages over

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2

Liu, Yuchuan. "An Review of Dynamic CMOS Comparators." Highlights in Science, Engineering and Technology 44 (April 13, 2023): 113–20. http://dx.doi.org/10.54097/hset.v44i.7273.

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CMOS dynamic comparators contributes a major role on the implementation of mixed signal successive approximation register (SAR) type of analog to digital converters (ADC). High precision, dynamic range, low voltage operation, high speed, low power consumption, reliability and offset voltage are the critical factors to be considered while designing CMOS dynamic comparators. This paper reviewed the performance of some popular dynamic CMOS comparators such as StrongARM latch comparator, double- tail dynamic-latched comparator, dynamic bias comparator and triple stage somparator.

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3

Du, Chengze. "Performance analysis of high-speed, low-power comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 292–301. http://dx.doi.org/10.54097/hset.v27i.3770.

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This article mainly presents a summary of development of dynamic comparators and the optimization to conventional comparator in recent years. By comparing the design of two different comparators, the design method of less power consumption, high speed or small delay, and low input referred noise can be concluded. The Dynamic comparator is designed to have small delay and less power consumption compared with two-stage comparator. The dynamic-bias comparator spends less power for operation the circuit compared with double-tail comparator. The FIA comparator operates under the controlling of logi

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4

Sun, Yuan. "A brief review on novel comparator design." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 418–27. http://dx.doi.org/10.54097/hset.v27i.3785.

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This paper reviewed three different kinds of comparators to show their respective advantage range. The Dynamic-bias comparator extends its pre-amplifier part with a capacitor and has a smaller power with a smaller input referred noise than Elzakker’s comparator but has a higher delay. The Quad high-speed comparator introduced the Quad into the comparator’s latch part. It has a lower delay and also make the calculation of the output voltage easier for it only depends on the skew factor. The low-power dynamic bias has a cross-couple device on its pre-amplifier part which slows down the discharge

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Li, Yichen. "The Performance analysis of Low-Power High-Speed comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 72–82. http://dx.doi.org/10.54097/hset.v27i.3723.

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Comparators are the essential block for planning high-speed analog and. This paper presents three inventive designs of the comparators in recent years. First, innovated by classic two-stage comparator, the comparator with a transconductance-enhanced latching stage is suitable for low-power, high-speed operation. Second, triple-latch feed-forward(TLFF) fully dynamic comparator guarantees the maximum possible gain and speed for a specific power across the entire input range. Finally, the comparator with a dynamic floating inverter maximizes efficiency by reusing the current.

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Sharmila Vallem. "Design of a High speed Low Low-Power Latched Comparator for Medical Implants." Communications on Applied Nonlinear Analysis 32, no. 8s (2025): 87–104. https://doi.org/10.52783/cana.v32.3610.

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The latched dynamic comparator is a fundamental component in all ADC architectures. Thermal effects, kickback, and offset voltage influence it. The kickback noise of the latched comparator in medical implant ADCs can impact the resolution, precision, and settling period. The current study examines a latching comparator that aims to reduce kickback noise. This research presents a low-power latched comparator for medical implants functioning at 1 V. This investigation implements a comparator utilising the sampling switching approach. This method successfully minimises kick-back noise and clockin

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7

Fan, Jiangfeng. "Performance Analysis of Low-Power CMOS Dynamic Comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 62–71. http://dx.doi.org/10.54097/hset.v27i.3722.

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This paper studies four structures of CMOS dynamic comparators introduced in recent years. Based on conventional double-tail comparator, a comparator with a tail capacitor prevents output nodes of preamplifier from completely discharging to reduce energy consumption. Another comparator with a cross-coupled pairs achieves the same purpose of the first design. A comparator adds a floating inverter amplifier (FIA) to realize both dynamic bias and current reuse, achieve low energy consumption and be insensitive to the VCM. The triple-latch feed-forward (TLFF) comparator decreases delay conspicuous

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8

Du, Qinghang. "Analysis and comparison of several types of low-power, low offset comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 120–32. http://dx.doi.org/10.54097/hset.v27i.3728.

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This paper studies several excellent works of comparator constructions of comparators and compares them with the Double-tail latch-type comparator. Based on the Elzakker comparator, the comparator with a dynamic bias reduced the use of energy by partly discharging the preamplifier's output nodes. Edge-Pursuit Comparator(EPC) demonstrates a new approach to reducing energy consumption by automatic energy optimization. Apart from the designs that optimize energy consumption. Low-Noise Self-Calibrating Dynamic Comparator provides the low-offset feature while in relatively low power consumption.

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9

Gajawada, Varun sai, and Mohana J. "Construction of CMOS Logic Double Tail Comparator for Lower Power Consumption Compared with Dynamic Comparator." ECS Transactions 107, no. 1 (2022): 13873–85. http://dx.doi.org/10.1149/10701.13873ecst.

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The aim of the study is to construct and analyze innovative CMOS based double tail comparators and compare them with a dynamic comparator using VLSI technology. Materials and methods: The comparator is designed by using the tanner tool for simulation and verification. By varying the length of a transistors the power values were obtained. There are two groups in the study. CMOS double tail comparator is the experimental group and dynamic tail comparator is the control group. This experiment is performed for 20 different values of length. Results: The power consumption of a CMOS logic double tai

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10

Wang, Sudong. "Review of Four Improving Designs of Dynamic Latch Comparator." Highlights in Science, Engineering and Technology 44 (April 13, 2023): 129–37. http://dx.doi.org/10.54097/hset.v44i.7287.

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In this paper, four disparate designs of dynamic latch comparators are discussed consecutively. By improving the design of the pre-amplifier stage, the double tail comparator provides a good power-speed trade-off. Further, Differential pair amplifiers are implemented in the second design, which has better comparison speed and energy dissipation. Next, a bulk-driven structure is employed on the comparator design to improve the comparison speed. Finally, a dynamic comparator utilizes a floating reservoir capacitor and a positive feedback bulk structure is introduced to achieve higher energy effi

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11

Chen, Zhenxiang, Yuheng Ni, and Zhenghao Xiong. "The Analysis of High-Speed Low-Power Dynamic Comparators." Journal of Physics: Conference Series 2187, no. 1 (2022): 012022. http://dx.doi.org/10.1088/1742-6596/2187/1/012022.

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Abstract This article reviews 5 different articles on optimizing comparators and focuses on their innovations. Many innovative methods are used to get a higher comparison speed, lower power consumption and degraded noise comparator. Many novel methods such as connecting the conventional two-stage dynamic comparator to a transconductance-enhanced latching stage, adding a charge pump to the Miyahara’s comparator, engendering two propagating edges in two inverter loops and measuring the distance between the two edges to compare different input voltage and using an inverter-based input pair which

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12

Zhang, Yuxin. "Design analyst of low energy, high gm/Id, and high sensitivity comparator." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 183–90. http://dx.doi.org/10.54097/hset.v27i.3745.

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This paper analyses three innovative designs of comparators and those structures have better performance than the traditional comparator. The dynamic floating inverter amplifier improves energy efficiency by preventing full discharging and charging. The Dynamic Bias Latch-Type Comparator used a double-tails latch to decrease energy consumption. The charge-injection compensations comparator has better sensitivity and less noise by utilizing the feedback loop. Those methods have greatly increased voltage gain, energy efficiency, and gm/Id

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13

Tang, Chengyun. "Performance analysis of comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 172–82. http://dx.doi.org/10.54097/hset.v27i.3742.

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This article reviews the innovative and improved structure of three comparators, and summarizes the optimization ideas to further optimize the design parameters of the comparators in the future. The Triple-Tail Dynamic Comparator proposes a multi-stage design to break connection between speed and noise. The Dynamic Bias Latch-Type (DB) Comparator takes an innovative approach to reducing energy consumption by stabilizing the source node voltage of the input pairs. The floating inverter amplififier (FIA)-based pre-amplififier further improves the energy efficiency based on the design of the low-

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14

Gupta, Anshu, Lalita Gupta, and R. K. Baghel. "Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator." International Journal of Engineering & Technology 7, no. 2.16 (2018): 38. http://dx.doi.org/10.14419/ijet.v7i2.16.11413.

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A second-order sigma delta modulator that uses an operational transconductance amplifier as integrator and latch comparator as quantizer. The proposed technique where a low power high gain OTA is used as integrator and another circuit called dynamic latch comparator with two tail transistors and two controlling switches are used to achieve high speed, low power and high resolution in second order delta sigma modulator. It enhances the power efficiency and compactness of the modulator by implementing these blocks as sub modules. A second order modulator has been designed to justify the effectiv

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15

Zhou, Yibo. "Analysis of the Improved Conventional Dynamic Comparator and the Edge-Pursuit Comparator." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 385–98. http://dx.doi.org/10.54097/hset.v27i.3782.

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In order to understand and learn the comparator in detail, three kinds of comparator are analyzed in this paper. An improvement of the traditional dynamic double-tailed comparator. So as to get fast operation and low power in low supply voltages, the circuit of the traditional double-tailed comparator is modulated. Another one is an improved low-power comparator. During evaluation, we can activate its latch delayed in order to avoid excess power consumption and get sufficient preamplification gain. The most innovative design is named edge-pursuit comparator (EPC) which is a new energy-efficien

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16

Zhu, Haomin. "Research on Four Different Designs of Comparator." Journal of Physics: Conference Series 2260, no. 1 (2022): 012003. http://dx.doi.org/10.1088/1742-6596/2260/1/012003.

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Abstract Comparators contribute a significant role to analogue to digital converters (ADC). This paper describes and evaluates four excellent comparator optimisation schemes in recent years and analyses their advantages and disadvantages, providing ideas for the following comparator research direction. In addition, this paper introduces the design steps of each comparator optimisation scheme. It shows how the designer completes the final optimisation scheme step by step from the practical problems, which provides a specific reference for the comparator designers in the future. A double-tail la

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17

G, Poornima. "Design of Low Power Double Tail Dynamic Comparator." International Journal for Research in Applied Science and Engineering Technology 12, no. 6 (2024): 426–35. http://dx.doi.org/10.22214/ijraset.2024.63031.

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Abstract: Dynamic regenerative comparators are being used more and more to enhance power and speed economy in analog-todigital converters. These converters must be extremely low-power, area-efficient, and high-speed. In this case, the DCs (DC) power is analyzed. A new DC is suggested, modifying the traditional double-tail comparator circuit for quick and low-power functioning even at low supply voltages, in accordance with the analysis that has been provided. Little transistors are added, and the construct is kept simple. Additionally, a new DC in line with on the suggested double-tail topolog

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18

Sathishkumar, Arumugam, and Siddhan Saravanan. "A Low-Noise Dynamic Comparator with Offset Calibration for CMOS Image Sensor Architecture." Journal of Circuits, Systems and Computers 28, no. 02 (2018): 1950022. http://dx.doi.org/10.1142/s0218126619500221.

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A low-noise, high-speed, low-input-capacitance switched dynamic comparator (SDC) CMOS image sensor architecture is presented in this paper. The comparator design occupying less area and consuming lesser power is suitable for bank of comparators in CMOS image readouts. The proposed dynamic comparator eliminates the stacking issue related to the conventional comparator and reduces the offset noise further. The need for low-noise, low-power, area-efficient and high-speed flash analog-to-digital converters (ADCs) in many applications today motivated us to design a comparator for ADC. The rail-to-r

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19

Cao, Menghua, and Weixun Tang. "The High-Speed Low-Power Dynamic Comparator." Journal of Physics: Conference Series 2113, no. 1 (2021): 012064. http://dx.doi.org/10.1088/1742-6596/2113/1/012064.

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Abstract This paper comments on four works for the optimization of comparator design. Today, with the development of integrated circuits, the requirements for comparators about low power, low delay, few offset voltage, and low noise are highly desirable. Specifically, these works made progress in the conventional comparator, which comprises a preamplifier and a latch. They also solved some problems, such as decreasing power and delay. Some works employ a positive feedback cross-coupled pares to provide a larger gain in the preamplifier, use PMOS switch transistors to accelerate the definition

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20

Panov, G., D. Manova, and A. Popov. "Comparator with dynamic hysteresis." Electronics Letters 35, no. 18 (1999): 1497. http://dx.doi.org/10.1049/el:19991075.

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21

Julie, Roslita Rusli, Shafie Suhaidi, Mohd Sidek Roslina, Abdul Majid Hasmayadi, Z. Wan Hassan W., and Mustafa M.A. "Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation." Indonesian Journal of Electrical Engineering and Computer Science (IJEECS) 17, no. 2 (2020): 783–92. https://doi.org/10.11591/ijeecs.v17.i2.pp783-792.

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Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V. The method used to verify the robustness of the comparator circuit across 45 PVT is presented. The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 1

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22

Kulothungan, Brindha, and Manjula Jothilingam. "A low power and high speed 45 nm CMOS dynamic comparator with low offset." A low power and high speed 45nm CMOS dynamic comparator with low offset 14, no. 4 (2023): 2293–300. https://doi.org/10.11591/ijpeds.v14.i4.pp2293-2300.

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The development of efficient data converters necessitates the design of low-power and high-speed comparators with low offset. Data converters, such as analog to digital converters (ADCs) and digital to analog converters (DACs), are critical components in applications like wireless communication, multimedia, and sensor interfaces. To enhance the performance of these data converters, improving the speed and power efficiency of comparators becomes crucial. Designing dynamic comparators with low power consumption and high-speed capabilities greatly enhances the sampling rate and accuracy of data c

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23

Brindha, Kulothungan, and Jothilingam Manjula. "A low power and high speed 45 nm CMOS dynamic comparator with low offset." International Journal of Power Electronics and Drive Systems (IJPEDS) 14, no. 4 (2023): 2293. http://dx.doi.org/10.11591/ijpeds.v14.i4.pp2293-2300.

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<p><span lang="EN-US">The development of efficient data converters necessitates the design of low-power and high-speed comparators with low offset. Data converters, such as analog to digital converters (ADCs) and digital to analog converters (DACs), are critical components in applications like wireless communication, multimedia, and sensor interfaces. To enhance the performance of these data converters, improving the speed and power efficiency of comparators becomes crucial. Designing dynamic comparators with low power consumption and high-speed capabilities greatly enhances the sa

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24

Chen, Yiming. "Innovative Techniques in Comparator Designs." Journal of Physics: Conference Series 2221, no. 1 (2022): 012022. http://dx.doi.org/10.1088/1742-6596/2221/1/012022.

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Abstract This paper presents four innovative designs of comparators proposed these years. A latch-type dynamic bias adds a tail capacitor to prevent fully discharging at the pre-amplifier output nodes to reduce energy consumption. The comparator is analysed and then compared with floating inverter amplifier (FIA) type. The pre-amplifier of the FIA type adopts an inverter-based input pair by a floating reservoir capacitor, greatly boosting gm/Id and improving the energy efficiency. The edge-pursuit comparator (EPC) provides a new perspective when designing comparators. According to the input di

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25

sharma*, D. Pavan kumar, and P. Sreehari Rao. "A Low Input Referred Noise Dynamic Comparator for High Speed Applications." International Journal of Recent Technology and Engineering (IJRTE) 8, no. 4 (2019): 4768–72. http://dx.doi.org/10.35940/ijrted6881.118419.

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Comparators play a pivotal role in design of analog and mixed signal circuits. Comparators employ regenerative feedback both in input pre-amplifier stage and output stage. The designed comparator resolves 5mV with resolution of 8 bits and dissipates 11mW of power using 1.2V supply in 130nm CMOS technology while operating at clock frequency of 1.25 GHz.

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26

Spinogatti, Valerio, Riccardo Della Sala, Cristian Bocciarelli, Francesco Centurelli, and Alessandro Trifiletti. "Body Biasing Techniques for Dynamic Comparators: A Systematic Survey." Electronics 13, no. 4 (2024): 711. http://dx.doi.org/10.3390/electronics13040711.

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Forward body biasing (FBB) has often been exploited in the literature for improving the performance of both analog and digital building blocks. Recent works have explored the application of FBB variants to mixed-signal electronics and in particular to dynamic comparators, where these techniques can help to relax the trade-off between speed and power consumption at medium and low supply voltages. However, the literature lacks a structured analysis of the solutions that have been developed and of the trade-offs that affect them. This work attempts to fill the gap by providing a survey of the app

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27

González-Cueto, José Antonio, Zaid García Sánchez, Gustavo Crespo Sánchez, Hernan Hernandez, Jorge Iván Silva Ortega, and Vicente Leonel Martínez Díaz. "A mho type phase comparator relay guideline using phase comparison technique for a power system." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (2021): 929. http://dx.doi.org/10.11591/ijece.v11i2.pp929-944.

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This paper presents a mho distance relay simulation based on the phase comparison technique using a typical electrical power systems analysis software for two cases: when the operation state is close to the static voltage limit and during a dynamic perturbation in the system. The paper evaluates the impedance variations caused by complex voltage values, the mho polarization, and the comparator operating region into the complex plane. In addition, the paper found the information for the dynamic perturbations from the outputs considering a mid-term stability program. The simulation of the mho-ph

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28

José, Antonio González-Cueto Cruz, García Sánchez Zaid, Crespo Sánchez Gustavo, Hernández Herrera Hernán, Iván Silva-Ortega Jorge, and Leonel Martínez Díaz Vicente. "A mho type phase comparator relay guideline using phase comparison technique for a power system." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (2021): 929–44. https://doi.org/10.11591/ijece.v11i2.pp929-944.

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This paper presents a mho distance relay simulation based on the phase comparison technique using a typical electrical power systems analysis software for two cases: when the operation state is close to the static voltage limit and during a dynamic perturbation in the system. The paper evaluates the impedance variations caused by complex voltage values, the mho polarization, and the comparator operating region into the complex plane. In addition, the paper found the information for the dynamic perturbations from the outputs considering a mid-term stability program. The simulation of the mho-ph

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29

Xi, Yinzheng, Nan Li, Jietao Diao, and Junqi Hong. "A full-scale complementary dynamic comparator." Journal of Physics: Conference Series 2807, no. 1 (2024): 012011. http://dx.doi.org/10.1088/1742-6596/2807/1/012011.

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Abstract This paper presents a dynamic comparator that achieves precise comparison across the entire full-scale range. The comparator, an essential component module in analog-to-digital converters (ADCs), is influenced by its input signal range, speed, and offset voltage, all of which impact the ADC’s performance. In the proposed comparator, a pre-amplification stage using PMOS as the input is incorporated alongside the comparator utilizing NMOS as the input, creating a complementary structure. This design ensures that at least one pre-amplification stage operates effectively, thereby maintain

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30

Dr., C. Arunabala, Ranjitha P.V.Sai, Likhitha Gunturu Sravya Bomminayuni, Navyasree Bonagiri, and Mounika Arumalla. "Design of Diversified Low Power and High-Speed Comparators using 45nm Cmos Technology." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 11, no. 5 (2022): 27–31. https://doi.org/10.35940/ijitee.E9849.0411522.

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<strong>Abstract:</strong> At Present, portable battery-operated devices are enhancing due to low power consumption and high-speed applications, The designed circuit with feedback are used to design novel circuits. If the comparator having feedback are without clock signal. The comparators are mainly designed to minimize the power consumption and with good accuracy because of clock signal, if the clock signal is there, it is used to drive the circuit with low current. But in the existed design the circuit is with high power and current. These drawbacks are overcome by using the projected desig

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31

N, Indu, Damodhar Rao M, and Prasad V. V. K. D. V. "High Speed Power Efficient Dynamic Comparator with Low Power Dissipation and Low Offset." Metallurgical and Materials Engineering 31, no. 3 (2025): 112–18. https://doi.org/10.63278/1332.

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When designing digital circuits with high speeds, dynamic comparators are necessary. In particular, central processing units (CPUs) in a wide variety of electronic devices rely on low-power, high-speed dynamic comparators. Numerous comparators, which are comparison circuits, make up these central processing units. This research article introduces a low-voltage, low-power Double Tail Dynamic Comparator (DTDC) that uses less power than previous designs. This journal article compares and contrasts the suggested design with several kinds of dynamic comparators. The suggested architecture is contra

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32

Gangadharan, Shaina, Ruqaiya Khanam, and Veeraiyah Thangasamy. "A Dynamic Supply Modulator in 18 nm FinFET Node Using Comparator Approach." International Journal of Experimental Research and Review 44 (October 30, 2024): 234–44. http://dx.doi.org/10.52756/ijerr.2024.v44spl.020.

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To keep up with the rapid development and to increase spectral efficiency, emerging communication systems like 5G will need to transfer data at speeds significantly faster than those of current systems. The subject of this study is radio frequency (RF) circuit systems, with an emphasis on efficiency enhancement for RF power amplifiers (PA). To cut costs and size, the majority of a smartphone's components are now integrated into a single chip. Regardless of the input signal's magnitude, the fundamental idea behind the envelope tracking (ET) approach is to operate the linear PA in its high-effic

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Hong, Jiyoon, and Jintae Kim. "Offset Cancellation Comparator with Dynamic amplifier." Journal of the Institute of Electronics and Information Engineers 56, no. 10 (2019): 32–37. http://dx.doi.org/10.5573/ieie.2019.56.10.32.

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34

Shrimali, Hitesh, and Valentino Liberali. "Parametric amplifier based dynamic clocked comparator." Solid-State Electronics 101 (November 2014): 85–89. http://dx.doi.org/10.1016/j.sse.2014.06.043.

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35

Zhang, H., T. Hirono, and I. Peric. "A high time resolution and high dynamic range ASIC for the micro-vertex detector in the PANDA experiment." Journal of Instrumentation 19, no. 02 (2024): P02036. http://dx.doi.org/10.1088/1748-0221/19/02/p02036.

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Abstract A monolithic pixel sensor test chip for the PANDA micro-vertex detector has been implemented in a 180 nm HVCMOS technology on a high resistivity substrate. The sensor should have very high time resolution (1 ns sigma) and high dynamic range (up to 1000). The pixel electronics contains a charge sensitive amplifier, a feedback circuit and two comparators. One comparator receives the fast signal and enables accurate time measurement. The other comparator receives the low pass filtered signal and is used for precise amplitude measurement. This publication presents several novel features o

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Nichols, M. J., and D. L. Sparks. "Independent feedback control of horizontal and vertical amplitude during oblique saccades evoked by electrical stimulation of the superior colliculus." Journal of Neurophysiology 76, no. 6 (1996): 4080–93. http://dx.doi.org/10.1152/jn.1996.76.6.4080.

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1. In early local feedback models for controlling horizontal saccade amplitude, a feedback signal of instantaneous eye position is continuously subtracted from a reference signal of desired eye position at a comparator. The output of the comparator is dynamic motor error, the remaining distance the eyes must rotate to reach the saccadic goal. When feedback reduces dynamic motor error to zero, the saccade stops on target. Two classes of local feedback model have been proposed for controlling oblique saccades (i.e., saccades with both horizontal and vertical components). In “independent comparat

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Deng, Ruichen. "Performance Analysis for Energy-Efficient Comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 94–105. http://dx.doi.org/10.54097/hset.v27i.3725.

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This work studies three different comparator proposed in recent years. Compared to the strnongARM latch as well as the Elzakker’s comparator, the dynamic comparator added cross-coupled devices that keeps the pre-amplifier’s integration nodes from fully discharge to the ground and thus improves energy performance. The dynamic bias latch-type comparator is an innovative design which added a tail capacitor to the pre-amplifier in order to block off the discharge route between the internal nodes and the ground. Though this design reduced the energy consumption significantly compared with the Elzak

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Zhang, Haoyue. "A Review of Innovative Comparator Designs." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 106–19. http://dx.doi.org/10.54097/hset.v27i.3726.

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Three papers on the optimal design of comparator circuits are further analyzed in this work. Each paper presents a method to improve the performance of comparators. Floating inverter amplifier applied an independent capacitor as the source of the preamplifier, which improves the overall performance of the circuit. In another design, a special local clock generator is proposed to control the input of both of the latch stage and the preampliﬁer, which makes it possible to adjust the speed and improve the energy efficiency. In dynamic bias circuit design, stabilized common-mode voltage is realize

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Sharath kumar, L Yeshwanth, Nallam Balaji Ram Ganesh, and Voruganti Saketh. "Design of Area efficient comparator architecture using 5T XOR GATE." international journal of engineering technology and management sciences 7, no. 3 (2023): 494–98. http://dx.doi.org/10.46647/ijetms.2023.v07i03.69.

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The use of comparators in computation-based designs is extensive, making optimization crucial. While some comparator designs use dynamic logic to achieve low-power consumption, the limitations of low-speed and poor-noise margin make this approach challenging. The proposed comparator design offers a new solution that is both area-efficient and has a high operating speed while consuming low-power. It was designed using 180nm technology in Tanner Tool, and its results were observed. Overall, this work presents a promising new solution for optimizing digital comparators and improving the efficienc

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Tang, Xiao-Bin, and Masayoshi Tachibana. "A BIST Scheme for Dynamic Comparators." Electronics 11, no. 24 (2022): 4169. http://dx.doi.org/10.3390/electronics11244169.

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This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in dynamic comparators. In this scheme, a feedback loop is designed using the characteristics of the comparator; monitoring the voltage in the feedback loop can determine the presence of a circuit fault. The proposed BIST scheme and the circuit under testing are realized at the transistor level. The proposed BIST scheme was simulated using HSPICE. The simulated fault coverage is approximately 87.8% with 90 test circuits. To further verify the effectiveness of the proposed BIST scheme, six faults were injec

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Khanfir, Leïla, and Jaouhar Mouïne. "Low-power latch comparator with accurate hysteresis control." Journal of Electrical Engineering 71, no. 6 (2020): 379–87. http://dx.doi.org/10.2478/jee-2020-0052.

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Abstract Recent research has focused on finding ways to control hysteresis of dynamic comparators. The current proposed techniques are based on either geometrical dimension adjustment or digital control. The first case does not allow for post fabrication control, while the second has limited accuracy. This paper presents a new dynamic comparator design with external hysteresis adjustment using an analog voltage. This is achieved by proposing an architecture including control devices with a specific sizing. This is performed with no significant increase of the design complexity, keeping the pow

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Rahman, Labonnah Farzana, Mamun Bin Ibne Reaz, Chia Chieu Yin, Mohammad Marufuzzaman, and Mohammad Anisur Rahman. "A High-Speed and Low-Offset Dynamic Latch Comparator." Scientific World Journal 2014 (2014): 1–8. http://dx.doi.org/10.1155/2014/258068.

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Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regen

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Prokopovič, Valdemar, Vytautas Makarskas, and Artūras Kilikevičius. "RESEARCH OF DYNAMICS OF MECHATRONICAL ANGLE MEASUREMENT SYSTEM / MECHATRONINIO KAMPO MATAVIMO KOMPARATORIAUS DINAMIKOS TYRIMAI." Mokslas – Lietuvos ateitis 7, no. 6 (2016): 637–41. http://dx.doi.org/10.3846/mla.2015.857.

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The article describes the dynamics researches of mechanical system of angle comparator. The goal of research is to determine the stability of mechanical system of angle comparator. Perfor-med the dynamic model of carriage of angle comparator which was conducted the theoretical research in Matlab environment. Straipsnyje aprašyti precizinės kampo komparatoriaus mechaninės sistemos dinamikos tyrimai. Tyrimo tikslas nustatyti precizinės kampo komparatoriaus mechaninės sistemos stabilumą. Sudarytas precizinės kampo komparatoriaus karietėlės dinaminis modelis, kuriuo pasitelkus buvo atliktas teorin

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Roslita Rusli, Julie, Suhaidi Shafie, Roslina Mohd Sidek, Hasmayadi Abdul Majid, W. Z. Wan Hassan, and M. A. Mustafa. "Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation." Indonesian Journal of Electrical Engineering and Computer Science 17, no. 2 (2020): 783. http://dx.doi.org/10.11591/ijeecs.v17.i2.pp783-792.

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Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V. The method used to verify the robustness of the comparator circuit across 45 PVT is presented. The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 100°C. The

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Parveen, Heena, and Vishal Moyal. "PARAMETRIC ANALYSIS OF DFAL BASED DYNAMIC COMPARATOR." ICTACT Journal on Microelectronics 3, no. 1 (2017): 354–58. http://dx.doi.org/10.21917/ijme.2017.0062.

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Kasparaitis, Albinas, Artūras Kilikevičius, Joris Vėžys, Valdemar Prokopovič, and Vytautas Makarskas. "Dynamic Research on Precision Angle Measurement Comparator." Solid State Phenomena 220-221 (January 2015): 554–57. http://dx.doi.org/10.4028/www.scientific.net/ssp.220-221.554.

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The aim of the research was to determine the mechanical stability of angle measurement comparator’s system. For that purpose, vibrations were measured at the significant points of the system and dynamic characteristics of the system were established.

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Yedukondalu, Udara, Vinod Arunachalam, Vasudha Vijayasri Bolisetty, and Ravikumar Guru Samy. "Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application." Indonesian Journal of Electrical Engineering and Computer Science 28, no. 2 (2022): 716. http://dx.doi.org/10.11591/ijeecs.v28.i2.pp716-723.

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The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm Complementary Metal-Oxide Semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when

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Yedukondalu, Udara, Vinod Arunachalam, Vasudha Vijayasri Bolisetty, and Ravikumar Guru Samy. "Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application." Indonesian Journal of Electrical Engineering and Computer Science 28, no. 2 (2022): 716–23. https://doi.org/10.11591/ijeecs.v28.i2.pp716-723.

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The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm complementary metal-oxide semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when

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Nguyen, Hoang Trong, and Trang Hoang. "A Novel Framework of Genetic Algorithm and Spectre to Optimize Delay and Power Consumption in Designing Dynamic Comparators." Electronics 12, no. 16 (2023): 3392. http://dx.doi.org/10.3390/electronics12163392.

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In integrated circuit (IC) design, analog circuits contribute significantly as the interface between real and digital world signals. Although they make up a relatively small portion of the overall circuit, their design process is often most time-consuming, mostly from the phase of manual iteration of circuit parameters to meet design specifications. Therefore, the design automation of analog circuits with the help of efficient optimization techniques arises as a promising candidate to address the issue. Among optimization algorithms, while the genetic algorithm (GA) has been shown to be effect

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Chen, Ziyan, and Zun Yang. "A Study on Design and Optimization methods in Latch Type Comparator." Journal of Physics: Conference Series 2221, no. 1 (2022): 012023. http://dx.doi.org/10.1088/1742-6596/2221/1/012023.

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Abstract The current state-of-the-art communication systems require analog-to-digital converters (ADCs) to sample the analog signals in digital representation at high speed and low power consumption with very high accuracy. Performance demand for ADCs directly promote the advancement of their basic component - the comparator. The traditional Strong-Arm dynamic comparator has been widely accepted for its fast decision, but it is limited by its significant voltage headroom and kickback noise. The double-tail latched dynamic comparator mitigates the aforementioned problems by allowing separate st

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