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Relevant bibliographies by topics / Dynamic element matching

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Academic literature on the topic 'Dynamic element matching'

Author: Grafiati

Published: 4 June 2021

Last updated: 12 June 2025

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Journal articles on the topic "Dynamic element matching"

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Galton, Ian. "Why Dynamic-Element-Matching DACs Work." IEEE Transactions on Circuits and Systems II: Express Briefs 57, no. 2 (2010): 69–74. http://dx.doi.org/10.1109/tcsii.2010.2042131.

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Weyten, L., and P. Rombouts. "A study of dynamic element-matching techniques for 3-level unit elements." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 47, no. 11 (2000): 1177–87. http://dx.doi.org/10.1109/82.885126.

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Yasuda, A., and H. Tanimoto. "Noise shaping dynamic element matching method using tree structure." Electronics Letters 33, no. 2 (1997): 130. http://dx.doi.org/10.1049/el:19970095.

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Chen, A. J., and Yong Ping Xu. "Multibit Delta-Sigma Modulator With Noise-Shaping Dynamic Element Matching." IEEE Transactions on Circuits and Systems I: Regular Papers 56, no. 6 (2009): 1125–33. http://dx.doi.org/10.1109/tcsi.2008.2008485.

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Jensen, H. T., and I. Galton. "An analysis of the partial randomization dynamic element matching technique." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 45, no. 12 (1998): 1538–49. http://dx.doi.org/10.1109/82.746665.

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Lindfors, Saska, Priit Ööpik та Kari Halonen. "N-path dynamic element matching for multibit bandpass ΣΔ modulators". International Journal of Circuit Theory and Applications 25, № 5 (1997): 335–46. http://dx.doi.org/10.1002/(sici)1097-007x(199709/10)25:5<335::aid-cta977>3.0.co;2-0.

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Wang, Jun, Toshimasa Matsuoka, and Kenji Taniguchi. "A switched-capacitor programmable gain amplifier using dynamic element matching." IEEJ Transactions on Electrical and Electronic Engineering 2, no. 6 (2007): 600–607. http://dx.doi.org/10.1002/tee.20215.

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Sanyal, Arindam, Long Chen, and Nan Sun. "Dynamic Element Matching With Signal-Independent Element Transition Rates for Multibit $\Delta\Sigma$ Modulators." IEEE Transactions on Circuits and Systems I: Regular Papers 62, no. 5 (2015): 1325–34. http://dx.doi.org/10.1109/tcsi.2015.2407434.

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Kok Lim Chan, N. Rakuljic, and I. Galton. "Segmented Dynamic Element Matching for High-Resolution Digital-to-Analog Conversion." IEEE Transactions on Circuits and Systems I: Regular Papers 55, no. 11 (2008): 3383–92. http://dx.doi.org/10.1109/tcsi.2008.2001757.

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Jensen, H. T., and I. Galton. "A low-complexity dynamic element matching DAC for direct digital synthesis." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 45, no. 1 (1998): 13–27. http://dx.doi.org/10.1109/82.659453.

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Dissertations / Theses on the topic "Dynamic element matching"

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Jensen, Henrik Tholstrup. "Analyses of dynamic element matching techniques for data conversion /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 1997. http://wwwlib.umi.com/cr/ucsd/fullcit?p9732715.

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Herbst, Steven (Steven G. ). "A low-noise bandgap voltage reference employing dynamic element matching." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/77071.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 109).<br>Bandgap voltages references are widely used in IC design, but are sensitive to low-frequency noise and component mismatch. This thesis describes the design and testing of a new IC voltage reference that targets these issues through three dynamic element matching (DEM) subsystems. The first is a chopper OTA, and the second two are component rotation schemes: one to exchange the positions of two critical resistors, and the second to cycle through all BJTs, periodically selecting each to participate as the "1" transistor of the N:1 bandgap ratio. Practical designs that address the various switching issues typically associated with DEM, such as glitch and clock drift, are described. Analytic expressions for the effects of noise and mismatch throughout the bandgap reference are derived, along with expressions for calculating the improvement that can be achieved by DEM. A test chip was implemented in a 0.25[mu]m BiCMOS process; with its three DEM subsystems enabled it is shown to achieve a 20x 1/f noise improvement and a 34x mismatch error improvement.<br>by Steven Herbst.<br>M.Eng.

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Nordick, Brent C. "Dynamic Element Matching Techniques For Delta-Sigma ADCs With Large Internal Quantizers." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd466.pdf.

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Gupta, Amit Kumar. "Design techniques for low noise and high speed A/D converters." [College Station, Tex. : Texas A&M University, 2006. http://hdl.handle.net/1969.1/ETD-TAMU-1666.

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Säll, Erik. "Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator Technology." Licentiate thesis, Linköping University, Linköping University, Electronics System, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5260.

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<p>High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers.</p><p>To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level. The models are simulated in MATLAB®. The results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase.</p><p>The first flash ADC has a conventional topology. It has a resistor net connected to a number of latched comparators, but its thermometer-tobinary encoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact encoder with a regular structure and short critical path. The main disadvantage is the code dependent timing difference between the encoder outputs introduced by this topology. The ADC was simulated on schematic level in Cadence® using the foundry provided transistor models. The design obtained a maximum sampling frequency of 1 GHz, an effective resolution bandwidth of 390 MHz, and a power consumption of 170 mW.</p><p>The purpose of the second ADC is to demonstrate the concept of introducing dynamic element matching (DEM) into the reference net of a flash ADC. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB when introducing DEM, but the settling time of the reference net with DEM will now limit the conversion speed of the converter. Further, the maximum input frequency is limited by the total resistance in the reference net, which gets increased in this topology. The total resistance is the total switch on-resistance plus the total resistance of the resistors. To increase the conversion speed and the maximum input frequency a new DEM topology is proposed in this work, which reduces the number of switches introduced into the reference net compared with earlier proposed DEM topologies. The transistor level simulations in Cadence® of the flash ADC with DEM indicates that the SFDR improves by 6 dB compared with when not using DEM, and is expected to improve more if more samples are used in the simulation. This was not possible in the current simulations due to the long simulation time. The improved SFDR is however traded for an increased chip area and a reduction of the maximum sampling frequency to 550 MHzfor this converter. The average power consumption is 92 mW.</p><p>A goal of this work is to evaluate a 130 nm partially depleted silicon-oninsulator (SOI) complementary metal oxide semiconductor (CMOS) technology with respect to analog circuit implementation. The converters are therefore implemented in this technology. When writing this the ADCs are still being manufactured. Since the technology evaluation will be based on the measurement results the final results of the evaluation are not included in this thesis. The conclusions regarding the SOI CMOS technology are therefore based on a literature study of published scientific papers in the SOI area, information extracted during the design phase of the ADCs, and from the transistor level circuit simulations. These inputs indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be exchanged for a fully depleted SOI CMOS technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved before the exchange can be done.</p><br>Report code: LiU-Tek-Lic-2005:68.

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Moine, Pascal. "Recalage de modèles éléments finis avec amortissement." Châtenay-Malabry, Ecole centrale de Paris, 1997. http://www.theses.fr/1997ECAP0537.

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Cette thèse est consacrée au recalage de modèles éléments finis avec amortissement visqueux non proportionnel sur les caractéristiques modales des structures modélisées. Le document est scindé en trois parties. - la première partie consiste en un rappel succinct des différents types d'amortissement couramment utilisés, un exposé de la problématique du recalage et une présentation des méthodes de recalage disponibles. - la seconde partie rassemble les nouveaux développements réalisés par l'auteur. Trois méthodes de recalage de modèles sur les caractéristiques modales des structures correspondantes sont présentées : la méthode de sensibilité inverse des valeurs et vecteurs propres, la méthode d'erreur en valeurs et vecteurs propres et la méthode d'erreur en loi de raideur. Deux méthodes de localisation des erreurs de modélisations sont proposées : la méthode d'erreur en loi de raideur et la méthode d'erreur en loi d'inertie. - la troisième et dernière partie est consacrée à l'utilisation des méthodes figurant dans la seconde partie du document pour le recalage de modèles industriels sur des données issues de mesures. Trois modèles sont recalés : le modèle de la maquette du bâtiment réacteur Hualien, le modèle d'une tuyauterie sur appuis en caoutchouc et le modèle d'une machine tournante.

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Wallin, Joakim. "Systematic planning and execution of ﬁnite element model updating". Licentiate thesis, KTH, Bro- och stålbyggnad, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-172295.

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In design of bridges and for estimation of dynamic properties and load carrying capacity Finite Element Method (FEM) is often used as a tool. The physical quantities used in the Finite Element (FE) model are often connected to varying degrees of uncertainty. To deal with these uncertainties conservative parameter estimates and safety factors are used. By calibrating the bridge FE model to better ﬁt with the response of the real structure, less conservative parameter values can be chosen. This method of comparing measured and response with estimates from a FE model and calibrating the model parameters is called Finite Element Model Updating (FEMU). In the present thesis diﬀerent aspects of FEMU are investigated. The ﬁrst part comprises a literature review covering all aspects of FEMU with special focus on the choice of updating parameters, objective functions for iterative updating procedures and the automatic pairing of modes. This part is concluded with a ﬂowchart suggesting a systematic approach to a FEMU project. In the second part of the text two bridge case studies are presented. In the ﬁrst case study a railway bridge in the north of Sweden is studied. A detailed FE bridge model from a previous project is used as a simulation model for extraction of modal data by eigenvalue analysis. Then simpliﬁed models are created and attempts to update these models are performed. The updating parameters are chosen based on a simple sensitivity analysis. Tests are performed to investigate the inﬂuence of chosen updating parameters and objective function on the computational cost and the quality of the updated model. Case study number two is more comprehensive and focuses on the sensitivity analysis for the choice of updating parameters and on the choice of objective function. A road bridge in the Stockholm area is used and as for case study one a detailed model from a previous project is used as simulation model. Also a new criteria for the automatic pairing of modes is presented and tested. In the end an attempt to verify two of the updated models is performed.<br><p>QC 20150825</p>

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Feuardent, Valérie. "Amélioration des modèles par recalage : application aux structures spatiales." Cachan, Ecole normale supérieure, 1997. http://www.theses.fr/1997DENS0019.

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Les modèles de calcul doivent permettre de prédire le comportement de structure complexe de façon précise. Il s'agit de minimiser la distance séparant les résultats de calcul (modèles éléments-finis) des données expérimentales (vibrations libres). Pour cela, la technique itérative de localisation-correction basée sur la notion de mesure d'erreur en relation de comportement (incluant une mesure d'erreur dynamique) est utilisée. Une base réduite de projection est proposée pour le recalage concernant les modélisations à grand nombre de degrés de liberté. Cette base construite à l'aide d'une méthode de sous-structuration a la particularité d'être associée aux tests expérimentaux. La robustesse au bruit de la méthode est considérée. Au niveau des résultats, l'étape de localisation des erreurs de modélisation est particulièrement performante et le problème inverse de détermination des paramètres dans le processus de correction ne rencontre pas de difficulté de résolution. Les erreurs faites lors de la modélisation des masses et des raideurs sont corrigées en quelques itérations.

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Lin, Yi-chg, and 林義哲. "A New Dynamic Element Matching techniques of TBDWA." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/25770985725903124651.

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碩士<br>逢甲大學<br>資訊電機工程碩士在職專班<br>94<br>Over-sampled Sigma-Delta D/A converters require discrete-time and switched-capacitor circuits. Hence over-sampled Sigma-Delta D/A converters in high-speed data transmission by accurate at sampling is not performance degradation. However must to improvement continuous-time circuits. Dynamic Element Matching (DEM) is proposed technique for reducing component mismatch. Dynamic Element Matching (DEM) is that good linearity of the multi-bit sigma-delta converter requires high component matching. A different approach to reduce the linearity of the DAC is offered by Dynamic Element Matching (DEM). The Data Weighted Averaging (DWA) is my research major for multi-bit Sigma-Delta D/A converters.

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Lee, Da-Huei, and 李大輝. "Dynamic Element Matching Approaches for Oversampling-Rate and Nyquist-Rate Data Converters." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/97751080152686237249.

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博士<br>國立成功大學<br>電機工程學系碩博士班<br>96<br>Data converters have become very important building blocks for integrated circuits (ICs) due to the fast growth of digital signal processing systems recently. Lower cost high-performance data converters are strongly demanded to satisfy the requirements of more complicated system-on-a-chip (SOC) systems. Element mismatch is one of the major impairments for low-cost high-resolution data converters. Dynamic element matching (DEM) approaches have been widely used to suppress the harmonic distortions caused by element mismatches. In this dissertation, several DEM approaches are proposed and analyzed. For oversampling-rate data converters, advancing data weighted averaging (ADWA) is proposed to remedy baseband tone problems of conventional DWA. For Nyquist-rate data converters, random multiple DWA (RMDWA), random incrementing DWA (RIDWA) and randomized thermometer-coding (RTC) are proposed to achieve high spurious-free dynamic range (SFDR) and small maximum output error. Furthermore, an ultra low-cost Nyquist-rate current-steering digital-to-analog converter (DAC) is implemented to experimentally verify the proposed RTC. For oversampling-rate data converters, multibit sigma–delta modulators usually employ the DWA to suppress the element mismatch effect but are plagued by baseband tone problems. The existing DWA-like approaches for solving these problems are categorized in this dissertation as tone-suppressing and tone-transferring approaches. Although tone-transferring approaches can achieve a better signal-to-noise-plus-distortion ratio than tone-suppressing approaches, they may behave unfavorably for input signals with dc components. A flexible DWA-like approach, ADWA, which can achieve both tone-suppressing and tone-transferring functions, is proposed. Moreover, ADWA can be a reconfigurable approach that uses input signal detection schemes to set its configuration. For Nyquist-rate data converters, three DEM approaches are proposed to be used with a proper layout switching scheme in a proposed new DAC structure. RMDWA and RIDWA have randomization and consecutive selection properties. Randomization effectively suppresses harmonic distortions to achieve good SFDR. Consecutive selection obtains small static output errors when it is used with the presented rotated walk switching scheme. The third DEM approach proposed for Nyquist-rate DACs is RTC, which provides randomization, consecutive selection, and low element switching activity properties. In addition to the benefits of the proposed RMDWA and RIDWA, low element switching activity can achieve small dynamic errors caused by element switching. To experimentally verify the proposed RTC, a 14-bit ultra low-cost current-steering DAC is implemented in a 1P6M 0.18-μm 1.8-V CMOS process. The measured SFDR is up to 80dB for single-tone tests at a 10MHz sampling frequency. The measurement results show that the RTC can improve the SFDR by 16dB. The 14-bit current-steering DAC has an active area of less than 0.28-mm2. The active area of the DAC is smaller than those of the state-of-the-art DACs with 14-bit resolution. The active area of the DAC is also smaller than those of other published 12-bit and 10-bit DACs.

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Book chapters on the topic "Dynamic element matching"

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Pertijs, Michiel A. P., Anton Bakker, and Johan H. Huijsing. "An Accurate CMOS Smart Temperature Sensor with Dynamic Element Matching and Second-Order Curvature Correction." In Transducers ’01 Eurosensors XV. Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/978-3-642-59497-7_18.

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Porto, Rodrigo Wolff, Lucas Murliky, Valner João Brusamarello, and Fernando Rangel de Sousa. "Multivariable Compensation for Wireless Power Transfer Systems in Dynamic Environments." In Emerging Capabilities and Applications of Wireless Power Transfer. IGI Global, 2019. http://dx.doi.org/10.4018/978-1-5225-5870-5.ch004.

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The growing number of publications concerning the dynamic compensation of inductive links has demonstrated the importance of the issue upon the WPT system design. There is not still a final and consolidated solution for the case when the coils are in relative movement with each other or misaligned. In this context, this chapter intends to give some contributions to that area, starting with the modeling of the inductive link in Section 2, where the authors show how the magnetic coupling coefficient and the load influence on the PDL. In addition, Section 2 also presents how the excitation frequency and the matching capacitances can improve the PDL. In Section 3, the variable excitation frequency method is explained as well as the hardware needed for the implementation. The voltage-controlled capacitance as a variable element in the matching network is shown in Section 4. Finally, in Section 5, optimization techniques are presented by using both frequency and capacitance to maximize the PDL.

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BOURSIER, I., D. TROMEURDERVOUT, and Y. VASSILEVSKY. "Aitken-Schwarz methods with non matching finite elements and spectral elements grids for the parallel simulation of an underground waste disposal site modelized by upscaling." In Parallel Computational Fluid Dynamics 1995. Elsevier, 1996. http://dx.doi.org/10.1016/b978-044482322-9/50009-8.

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Boursier, I., D. Tromeur-Dervout, and Y. Vassilevsky. "Aitken-Schwarz methods with non matching finite elements and spectral elements grids for the parallel simulation of an underground waste disposal site modelized by upscaling." In Parallel Computational Fluid Dynamics 2004. Elsevier, 1996. http://dx.doi.org/10.1016/b978-044452024-1/50009-9.

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Ahtisham Aslam, Muhammad, Sören Auer, and Klaus-Peter Fähnrich. "Towards Semantic Business Processes." In Semantic Web for Business. IGI Global, 2009. http://dx.doi.org/10.4018/978-1-60566-066-0.ch012.

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The business process execution language for Web services (BPEL4WS, shortly BPEL) is one of the most popular languages and de facto standard for modelling business processes as Web services compositions. However, it only allows using hard-coded syntactical interfaces for partners and the process itself, i.e. semantic descriptions of services cannot be used within a process model. The lacks of an ontological description of the process elements cause limitations in the ways services are used within a process. A service providing the same functionality as the one referenced in the process model, but via a different syntactical interface, cannot be used instead. As a result, a process model cannot find an alternate service that performs the same functionality but exposes a different interface and can crash. Also, another drawback of such business processes is that they expose syntactical interfaces and cannot be discovered and composed dynamically by other semantic enabled systems slowing down the process of interaction between business partners. OWL-S on the other hand is suite of OWL ontologies and can be used to describe the compositions of Web services on the basis of matching semantics as well as to expose semantically enriched interfaces of business processes. Consequently, translating BPEL process descriptions to OWL-S suite of ontologies can overcome syntactical limitations of BPEL processes enabling them to 1) edit and model the composition of Web services on the basis of matching semantics 2) provide semantically enriched information of business processes. This semantically enriched information helps for dynamic and automated discovery, invocation and composition of business processes as Semantic Web services. Describing an approach and its implementation that can be used to enable business processes for semantic based dynamic discovery, invocation and composition by translating BPEL process descriptions to OWL-S suite of ontologies is the aim of this chapter.

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Conference papers on the topic "Dynamic element matching"

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Nguyen, Khiem. "Practical dynamic element matching techniques for 3-level unit elements." In 2017 IEEE Custom Integrated Circuits Conference (CICC). IEEE, 2017. http://dx.doi.org/10.1109/cicc.2017.7993717.

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Noeske, Carsten, Maurits Ortmanns, and Yiannos Manoli. "A dynamic-Element-Matching architecture using individual element error shaping." In 2008 51st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2008. http://dx.doi.org/10.1109/mwscas.2008.4616836.

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Sall, Erik, and Mark Vesterbacka. "6-bit Flash ADC with Dynamic Element Matching." In 2006 NORCHIP. IEEE, 2006. http://dx.doi.org/10.1109/norchp.2006.329268.

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Keppler, Marc, and Donald Thelen. "An Idle-Tone Free Dynamic Element Matching Algorithm." In 2007 IEEE Custom Integrated Circuits Conference. IEEE, 2007. http://dx.doi.org/10.1109/cicc.2007.4405713.

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Kokolanski, Zivko, Cvetan Gavrovski, and Vladimir Dimcev. "Dynamic element matching in direct sensor — Microcontroller interface." In 2010 14th International Power Electronics and Motion Control Conference (EPE/PEMC 2010). IEEE, 2010. http://dx.doi.org/10.1109/epepemc.2010.5606678.

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Su, Wei, Yuan Wang, Junlei Zhao, Song Jia, and Xing Zhang. "A novel dynamic element matching technique in current-steering DAC." In 2011 International Conference of Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2011. http://dx.doi.org/10.1109/edssc.2011.6117746.

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Jafari, Hamed Mazhab, and Roman Genov. "Bidirectional current conveyer with chopper stabilization and dynamic element matching." In 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012. IEEE, 2012. http://dx.doi.org/10.1109/iscas.2012.6271416.

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Maurino, R. "A dynamic element matching scheme for quadrature sigma-delta modulators." In 5th IEE International Conference on ADDA 2005. Advanced A/D and D/A Conversion Techniques and their Applications. IEE, 2005. http://dx.doi.org/10.1049/cp:20050153.

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Jensen, H. T. "Dynamic element matching for highly linear digital-to-analog conversion." In Third International Conference on Advanced A/D and D/A Conversion Techniques and their Applications. IEE, 1999. http://dx.doi.org/10.1049/cp:19990463.

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Kok Lim Chan and I. Galton. "A 14b 100MS/s DAC with Fully Segmented Dynamic Element Matching." In 2006 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. IEEE, 2006. http://dx.doi.org/10.1109/isscc.2006.1696302.

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