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Rountree, Barry. "Theory and Practice of Dynamic Voltage/Frequency Scaling in the High Performance Computing Environment." Diss., The University of Arizona, 2009. http://hdl.handle.net/10150/305368.
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This dissertation provides a comprehensive overview of the theory and practice of Dynamic Voltage/Frequency Scaling (DVFS) in the High Performance Computing (HPC) environment. We summarize the overall problem as follows: how can the same level of computational performance be achieved using less electrical power? Equivalently, how can computational performance be increased using the same amount of electrical power? In this dissertation we present performance and architecture models of DVFS as well as the Adagio runtime system. The performance model recasts the question as an optimization problem that we solve using linear programming, thus establishing a bound on potential energy savings. The architectural model provides a low-level explanation of how memory bus and CPU clock frequencies interact to determine execution time. Using insights provided from these models, we have designed and implemented the Adagio runtime system. This system realizes near-optimal energy savings on real-world scientific applications without the use of training runs or source code modification, and under the constraint that only negligible delay will be tolerated by the user. This work has opened up several new avenues of research, and we conclude by enumerating these.
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Saha, Sonal. "An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms." Thesis, Virginia Tech, 2011. http://hdl.handle.net/10919/35035.
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Dynamic voltage and frequency scaling (DVFS) is an extensively studied energy manage-
ment technique, which aims to reduce the energy consumption of computing platforms by
dynamically scaling the CPU frequency. Real-Time DVFS (RT-DVFS) is a branch of DVFS,
which reduces CPU energy consumption through DVFS, while at the same time ensures that
task time constraints are satisfied by constructing appropriate real-time task schedules. The
literature presents numerous RT-DVFS scheduling algorithms, which employ different tech-
niques to utilize the CPU idle time to scale the frequency. Many of these algorithms have
been experimentally studied through simulations, but have not been implemented on real
hardware platforms. Though simulation-based experimental studies can provide a first-order
understanding, implementation-based studies can reveal actual timeliness and energy con-
sumption behaviours. This is particularly important, when it is difficult to devise accurate
simulation models of hardware, which is increasingly the case with modern systems.
In this thesis, we study the timeliness and energy consumption behaviours of fourteen state-
of-the-art RT-DVFS schedulers by implementing and evaluating them on two hardware plat-
forms. The schedulers include CC-EDF, LA-EDF, REUA, DRA andd AGR1 among others,
and the hardware platforms include ASUS laptop with the Intel I5 processor and a mother-
board with the AMD Zacate processor. We implemented these schedulers in the ChronOS
real-time Linux kernel and measured their actual timeliness and energy behaviours under
a range of workloads including CPU-intensive, memory-intensive, mutual exclusion lock-
intensive, and processor-underloaded and overloaded workloads.
Our studies reveal that measuring the CPU power consumption as the cube of CPU fre-
quency can lead to incorrect conclusions. In particular, it ignores the idle state CPU power
consumption, which is orders of magnitude smaller than the active power consumption.
Consequently, power savings obtained by exclusively optimizing active power consumption
(i.e., RT-DVFS) may be offset by completing tasks sooner by running them at the highest
frequency and transitioning to the idle state earlier (i.e., no DVFS). Thus, the active power
consumption savings of the RT-DVFS techniquesâ that we report are orders of magnitude
smaller than their simulation-based savings reported in the literature.Master of Science
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Clark, Mark A. "Dynamic Voltage/Frequency Scaling and Power-Gating of Network-on-Chip with Machine Learning." Ohio University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1544105215810566.
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Li, Juan. "Application-Directed DVFS using Multiple Clock Domains on Graphics Hardware." Digital WPI, 2009. https://digitalcommons.wpi.edu/etd-theses/85.
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As handheld devices have become increasingly popular, powerful programmable graphics hardware for mobile and handheld devices has been deployed. While many resources on mobile devices are limited, the predominant problem for mobile devices is their limited battery power. Several techniques have been proposed to increase the energy efficiency of mobile applications and improve battery life. In this thesis, we propose a new dynamic voltage and frequency scaling (DVFS) on Graphics Processing Units (GPU). In most cases, cues within the graphics appli- cation can be used to predict portions of a GPU that will be used or unused when the application is run. We partition the GPU into six clock domains that can be clocked at different rates. Specifically, each domain it has its own voltage and frequency set- ting based on its predicted workload to save energy without reducing applications frame rates. In addition, we propose an signature-based algorithm for predicting the workload offered to our six clock domains by a given application to decide voltage and frequency settings. We conduct experiments and compare the results of our new signature based workload prediction algorithm with some other traditional interval based workload prediction algorithms. Our results show that our signature-based prediction can save 30-50% energy without afecting application frame rates.
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Muhammad, F. "Ordonnancement de tâches efficace et à complexité maîtrisée pour des systèmes temps-réel." Phd thesis, Université de Nice Sophia-Antipolis, 2009. http://tel.archives-ouvertes.fr/tel-00454616.
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Les performances des algorithmes d'ordonnancement ont un impact direct sur les performances du système complet. Les algorithmes d'ordonnancement temps réel possèdent des bornes théoriques d'ordonnançabilité optimales mais cette optimalité est souvent atteinte au prix d'un nombre élevé d'événements d'ordonnancement à considérer (préemptions et migrations de tâches) et d'une complexité algorithmique importante. Notre opinion est qu'en exploitant plus efficacement les paramètres des tâches il est possible de rendre ces algorithmes plus efficaces et à coût maitrisé, et ce dans le but d'améliorer la Qualité de Service (QoS) des applications. Nous proposons dans un premier temps des algorithmes d'ordonnancement monoprocesseur qui augmentent la qualité de service d'applications hybrides c'est-à-dire qu'en situation de surcharge, les tâches à contraintes souples ont leur exécution maximisée et les échéances des tâches à contraintes strictes sont garanties. Le coût d'ordonnancement de ces algorithmes est aussi réduit (nombre de préemptions) par une meilleure exploitation des paramètres implicites et explicites des tâches. Cette réduction est bénéfique non seulement pour les performances du système mais elle agit aussi positivement sur la consommation d'énergie. Aussi nous proposons une technique associée à celle de DVFS (dynamic voltage and frequency scaling) afin de minimiser le nombre de changements de points de fonctionnement du fait qu'un changement de fréquence implique un temps d'inactivité du processeur et une consommation d'énergie. Les algorithmes d'ordonnancement multiprocesseur basés sur le modèle d'ordonnancement fluide (notion d'équité) atteignent des bornes d'ordonnançabilité optimales. Cependant cette équité n'est garantie qu'au prix d'hypothèses irréalistes en pratique du fait des nombres très élevés de préemptions et de migrations de tâches qu'ils induisent. Dans cette thèse un algorithme est proposé (ASEDZL) qui n'est pas basé sur le modèle d'ordonnancement fluide. Il permet non seulement de réduire les préemptions et les migrations de tâches mais aussi de relâcher les hypothèses imposées par ce modèle d'ordonnancement. Enfin, nous proposons d'utiliser ASEDZL dans une approche d'ordonnancement hiérarchique ce qui permet d'obtenir de meilleurs résultats que les techniques classiques.
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Shiomi, Jun. "Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits." Kyoto University, 2017. http://hdl.handle.net/2433/228252.
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Bhatti, K. "Energy-aware Scheduling for Multiprocessor Real-time Systems." Phd thesis, Université de Nice Sophia-Antipolis, 2011. http://tel.archives-ouvertes.fr/tel-00599980.
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Les applications temps réel modernes deviennent plus exigeantes en termes de ressources et de débit amenant la conception d'architectures multiprocesseurs. Ces systèmes, des équipements embarqués au calculateur haute performance, sont, pour des raisons d'autonomie et de fiabilité, confrontés des problèmes cruciaux de consommation d'énergie. Pour ces raisons, cette thèse propose de nouvelles techniques d'optimisation de la consommation d'énergie dans l'ordonnancement de systèmes multiprocesseur. La premiére contribution est un algorithme d'ordonnancement hiérarchique á deux niveaux qui autorise la migration restreinte des tâches. Cet algorithme vise á réduire la sous-optimalité de l'algorithme global EDF. La deuxiéme contribution de cette thèse est une technique de gestion dynamique de la consommation nommée Assertive Dynamic Power Management (AsDPM). Cette technique, qui régit le contrôle d'admission des tâches, vise á exploiter de manière optimale les modes repos des processeurs dans le but de réduire le nombre de processeurs actifs. La troisiéme contribution propose une nouvelle technique, nommée Deterministic Stretch-to-Fit (DSF), permettant d'exploiter le DVFS des processeurs. Les gains énergétiques observés s'approchent des solutions déjà existantes tout en offrant une complexité plus réduite. Ces techniques ont une efficacité variable selon les applications, amenant á définir une approche plus générique de gestion de la consommation appelée Hybrid Power Management (HyPowMan). Cette approche sélectionne, en cours d'exécution, la technique qui répond le mieux aux exigences énergie/performance.
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Mallangi, Siva Sai Reddy. "Low-Power Policies Based on DVFS for the MUSEIC v2 System-on-Chip." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-229443.
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Multi functional health monitoring wearable devices are quite prominent these days. Usually these devices are battery-operated and consequently are limited by their battery life (from few hours to a few weeks depending on the application). Of late, it was realized that these devices, which are currently being operated at fixed voltage and frequency, are capable of operating at multiple voltages and frequencies. By switching these voltages and frequencies to lower values based upon power requirements, these devices can achieve tremendous benefits in the form of energy savings. Dynamic Voltage and Frequency Scaling (DVFS) techniques have proven to be handy in this situation for an efficient trade-off between energy and timely behavior. Within imec, wearable devices make use of the indigenously developed MUSEIC v2 (Multi Sensor Integrated circuit version 2.0). This system is optimized for efficient and accurate collection, processing, and transfer of data from multiple (health) sensors. MUSEIC v2 has limited means in controlling the voltage and frequency dynamically. In this thesis we explore how traditional DVFS techniques can be applied to the MUSEIC v2. Experiments were conducted to find out the optimum power modes to efficiently operate and also to scale up-down the supply voltage and frequency. Considering the overhead caused when switching voltage and frequency, transition analysis was also done. Real-time and non real-time benchmarks were implemented based on these techniques and their performance results were obtained and analyzed. In this process, several state of the art scheduling algorithms and scaling techniques were reviewed in identifying a suitable technique. Using our proposed scaling technique implementation, we have achieved 86.95% power reduction in average, in contrast to the conventional way of the MUSEIC v2 chip’s processor operating at a fixed voltage and frequency. Techniques that include light sleep and deep sleep mode were also studied and implemented, which tested the system’s capability in accommodating Dynamic Power Management (DPM) techniques that can achieve greater benefits. A novel approach for implementing the deep sleep mechanism was also proposed and found that it can obtain up to 71.54% power savings, when compared to a traditional way of executing deep sleep mode.Nuförtiden så har multifunktionella bärbara hälsoenheter fått en betydande roll. Dessa enheter drivs vanligtvis av batterier och är därför begränsade av batteritiden (från ett par timmar till ett par veckor beroende på tillämpningen). På senaste tiden har det framkommit att dessa enheter som används vid en fast spänning och frekvens kan användas vid flera spänningar och frekvenser. Genom att byta till lägre spänning och frekvens på grund av effektbehov så kan enheterna få enorma fördelar när det kommer till energibesparing. Dynamisk skalning av spänning och frekvens-tekniker (såkallad Dynamic Voltage and Frequency Scaling, DVFS) har visat sig vara användbara i detta sammanhang för en effektiv avvägning mellan energi och beteende. Hos Imec så använder sig bärbara enheter av den internt utvecklade MUSEIC v2 (Multi Sensor Integrated circuit version 2.0). Systemet är optimerat för effektiv och korrekt insamling, bearbetning och överföring av data från flera (hälso) sensorer. MUSEIC v2 har begränsad möjlighet att styra spänningen och frekvensen dynamiskt. I detta examensarbete undersöker vi hur traditionella DVFS-tekniker kan appliceras på MUSEIC v2. Experiment utfördes för att ta reda på de optimala effektlägena och för att effektivt kunna styra och även skala upp matningsspänningen och frekvensen. Eftersom att ”overhead” skapades vid växling av spänning och frekvens gjordes också en övergångsanalys. Realtidsoch icke-realtidskalkyler genomfördes baserat på dessa tekniker och resultaten sammanställdes och analyserades. I denna process granskades flera toppmoderna schemaläggningsalgoritmer och skalningstekniker för att hitta en lämplig teknik. Genom att använda vår föreslagna skalningsteknikimplementering har vi uppnått 86,95% effektreduktion i jämförelse med det konventionella sättet att MUSEIC v2-chipets processor arbetar med en fast spänning och frekvens. Tekniker som inkluderar lätt sömn och djupt sömnläge studerades och implementerades, vilket testade systemets förmåga att tillgodose DPM-tekniker (Dynamic Power Management) som kan uppnå ännu större fördelar. En ny metod för att genomföra den djupa sömnmekanismen föreslogs också och enligt erhållna resultat så kan den ge upp till 71,54% lägre energiförbrukning jämfört med det traditionella sättet att implementera djupt sömnläge.
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Akgul, Yeter. "Gestion de la consommation basée sur l’adaptation dynamique de la tension, fréquence et body bias sur les systèmes sur puce en technologie FD-SOI." Thesis, Montpellier 2, 2014. http://www.theses.fr/2014MON20132/document.
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Au-delà du nœud technologique CMOS BULK 28nm, certaines limites ont été atteintes dans l'amélioration des performances en raison notamment d'une consommation énergétique devenant trop importante. C'est une des raisons pour lesquelles de nouvelles technologies ont été développées, notamment celles basées sur Silicium sur Isolant (SOI). Par ailleurs, la généralisation des architectures complexes de type multi-cœurs, accentue le problème de gestion de la consommation à grain-fin. Les technologies CMOS FD-SOI offrent de nouvelles opportunités pour la gestion de la consommation en permettant d'ajuster, outre les paramètres usuels que sont la tension d'alimentation et la fréquence d'horloge, la tension de body bias. C'est dans ce contexte que ce travail étudie les nouvelles possibilités offertes et explore des solutions innovantes de gestion dynamique de la tension d'alimentation, fréquence d'horloge et tension de body bias afin d'optimiser la consommation énergétique des systèmes sur puce. L'ensemble des paramètres tensions/fréquence permettent une multitude de points de fonctionnement, qui doivent satisfaire des contraintes de fonctionnalité et de performance. Ce travail s'intéresse donc dans un premier temps à une problématique de conception, en proposant une méthode d'optimisation du placement de ces points de fonctionnement. Une solution analytique permettant de maximiser le gain en consommation apporté par l'utilisation de plusieurs points de fonctionnement est proposée. La deuxième contribution importante de cette thèse concerne la gestion dynamique de la tension d'alimentation, de la fréquence et de la tension de body bias, permettant d'optimiser l'efficacité énergétique en se basant sur le concept de convexité. La validation expérimentale des méthodes proposées s'appuie sur des échantillons de circuits réels, et montre des gains en consommation moyens allant jusqu'à 35%Beyond 28nm CMOS BULK technology node, some limits have been reached in terms of performance improvements. This is mainly due to the increasing power consumption. This is one of the reasons why new technologies have been developed, including those based on Silicon-On-Insulator (SOI). Moreover, the standardization of complex architectures such as multi-core architectures emphasizes the problem of power management at fine-grain. FD-SOI technologies offer new power management opportunities by adjusting, in addition to the usual parameters such as supply voltage and clock frequency, the body bias voltage. In this context, this work explores new opportunities and searches novel solutions for dynamically manage supply voltage, clock frequency and body bias voltage in order to optimize the power consumption of System on Chip.Adjusting supply voltage, frequency and body bias parameters allows multiple operating points, which must satisfy the constraints of functionality and performance. This work focuses initially at design time, proposing a method to optimize the placement of these operating points. An analytical solution to maximize power savings achieved through the use of several operating points is provided. The second important contribution of this work is a method based on convexity concept to dynamically manage the supply voltage, the frequency and the body bias voltage so as to optimize the energy efficiency. The experimental results based on real circuits show average power savings reaching 35%
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Zorello, Ligia Maria Moreira. "Dynamic CPU frequency scaling using machine learning for NFV applications." Universidade de São Paulo, 2018. http://www.teses.usp.br/teses/disponiveis/3/3141/tde-30012019-100044/.
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Growth in the Information and Communication Technology sector is increasing the need to improve the quality of service and energy efficiency, as this industry has already surpassed 12% of global energy consumption in 2017. Data centers correspond to a large part of this consumption, accounting for about 15% of energy expenditure on the Information and Communication Technology domain; moreover, the subsystem that generates the most costs for data center operators is that of servers and storage. Many solutions have been proposed to reduce server consumption, such as the use of dynamic voltage and frequency scaling, a technology that enables the adaptation of energy consumption to the workload by modifying the operating voltage and frequency, although they are not optimized for network traffic. In this thesis, a control method was developed using a prediction engine based on the analysis of the ongoing traffic. Machine learning algorithms based on Neural Networks and Support Vector Machines have been used, and it was verified that it is possible to reduce power consumption by up to 12% on servers with Intel Sandy Bridge processor and up to 21 % in servers with Intel Haswell processor when compared to the maximum frequency, which is currently the most used solution in the industry.O crescimento do setor de Tecnologia da Informação e Comunicação está aumentando a necessidade de melhorar a qualidade de serviço e a eficiência energética, pois o setor já ultrapassou a marca de 12% do consumo energético global em 2017. Data centers correspondem a grande parte desse consumo, representando cerca de 15% dos gastos com energia do setor Tecnologia Informação e Comunicação; além disso, o subsistema que gera mais custos para operadores de data centers é o de servidores e armazenamento. Muitas soluções foram propostas a fim de reduzir o consumo de energia com servidores, como o uso de escalonamento dinâmico de tensão e frequência, uma tecnologia que permite adaptar o consumo de energia à carga de trabalho, embora atualmente não sejam otimizadas para o processamento do tráfego de rede. Nessa dissertação, foi desenvolvido um método de controle usando um mecanismo de previsão baseado na análise do tráfego que chega aos servidores. Os algoritmos de aprendizado de máquina baseados em Redes Neurais e em Máquinas de Vetores de Suporte foram utilizados, e foi verificado que é possível reduzir o consumo de energia em até 12% em servidores com processador Intel Sandy Bridge e em até 21% em servidores com processador Intel Haswell quando comparado com a frequência máxima, que é atualmente a solução mais utilizada na indústria.
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Wang, Qiang. "Performance and power modeling of GPU systems with dynamic voltage and frequency scaling." HKBU Institutional Repository, 2020. https://repository.hkbu.edu.hk/etd_oa/814.
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To address the ever-increasing demand for computing capacities, more and more heterogeneous systems have been designed to use both general-purpose and special-purpose processors. The huge energy consumption of them raises new environmental concerns and challenges. Besides performance, energy efficiency is another key factor to be considered by system designers and consumers. In particular, contemporary graphics processing units (GPUs) support dynamic voltage and frequency scaling (DVFS) to balance computational performance and energy consumption. However, accurate and straightforward performance and power estimation for a given GPU kernel under different frequency settings is still lacking for real hardware, which is essential to determine the best frequency configuration for energy saving. In this thesis, we investigate how to improve the energy efficiency of GPU systems by accurately modeling the effects of GPU DVFS on the target GPU kernel. We also propose efficient algorithms to solve the communication contention problem in scheduling multiple distributed deep learning (DDL) jobs on GPU clusters. We introduce our studies as follows. First, we present a benchmark suite EPPMiner for evaluating the performance, power, and energy of different heterogeneous systems. EPPMiner consists of 16 benchmark programs that cover a broad range of application domains, and it shows a great variety in the intensity of utilizing the processors. We have implemented a prototype of EPPMiner that supports OpenMP, CUDA, and OpenCL, and demonstrated its usage by three showcases. The showcases justify that GPUs provide much better energy efficiency than other types of computing systems, and especially illustrate the effectiveness of GPU Dynamic Voltage and Frequency Scaling (DVFS) on the energy efficiency of GPU applications. Second, we reveal a fine-grained analytical model to estimate the execution time of GPU kernels with both core and memory frequency scaling. Compared to the cycle-level simulators, which are too slow to apply on real hardware, our model only needs one-off micro-benchmarks to extract a set of hardware parameters and kernel performance counters without any source code analysis. Our experimental results show that the proposed performance model can capture the kernel performance scaling behaviors under different frequency settings and achieve decent accuracy. Third, we design a cross-benchmarking suite, which simulates kernels with a wide range of instruction distributions. The synthetic kernels generated by this suite can be used for model pre- training or as supplementary training samples. We then build machine learning models to predict the execution time and runtime power of a GPU kernel under different voltage and frequency settings. Validated on three modern GPUs with a wide frequency scaling range, by using a collection of 24 real application kernels, the model trained only with our cross-benchmarking suite is able to achieve considerably accurate results. At last, we establish a new DDL job scheduling framework which organizes DDL jobs as Directed Acyclic Graphs (DAGs) and considers communication contention between nodes. We then propose an efficient job placement algorithm, Least-Workload-First- (LWF-), to balance the GPU utilization and consolidate the allocated GPUs for each job. When scheduling the communication tasks, we propose Ada-SRSF for the DDL job scheduling problem to address the communication contention issue. Our simulation results show that LWF- achieves up to 1.59x improvement over the classical first-fit algorithms. More importantly, Ada-SRSF reduces the average job completion time by up to 36.7%, as compared to the solutions of either avoiding all the communication contention or accepting all of it
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Michael, Michael Nasri. "Dynamic voltage and frequency scaling with multi-clock distribution systems on SPARC core /." Online version of thesis, 2009. http://hdl.handle.net/1850/10750.
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Aldhahri, Eiman Ali. "Dynamic Voltage and Frequency Scaling Enhanced Task Scheduling Technologies Toward Greener Cloud Computing." OpenSIUC, 2014. https://opensiuc.lib.siu.edu/theses/1382.
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The skyrocketing amount of electricity consumed by many data centers around the globe has become a serious issue for the cloud computing and entire IT industry. The demand for data centers is rapidly increasing due to widespread usage of cloud services. It also leads to huge carbon emissions contributing to the global greenhouse effect. The US Environmental Protection Agency has declared that data centers represent a substantial portion of the energy consumption in the US and the whole world. Some of this energy consumption is caused by idle servers or servers running at higher-than-necessary frequencies. Due to the Dynamic Voltage and Frequency Scaling (DVFS) technology enabled in many CPUs, strategically reducing CPU frequency without affecting the Quality of Service (QoS) is desired. Our goal in this paper is to calculate and tune to the best CPU frequency for each running task combined with two commonly-used scheduling approaches, namely round robin and first fit algorithms, given the CPU configuration and the execution deadline. The effectiveness of our algorithms is evaluated under a CloudSim/CloudReport simulation environment as well as real hypervisor computer system with power gauge. The open source CloudReport, based on the CloudSim simulator, has been used to integrate our DVFS algorithm with the two scheduling algorithms to illustrate the efficiency of power saving in different scenarios. Furthermore, electricity consumption is measured and compared using power gauge of Watts Up meter.
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Benhani, El mehdi. "Sécurité des systèmes sur puce complexes hétérogènes." Thesis, Lyon, 2020. http://www.theses.fr/2020LYSES016.
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La thèse étudie la sécurité de la technologie ARM TrustZone dans le cadre des SoCs complexes hétérogènes. La thèse présente des attaques matérielles qui touchent des éléments de l’architecture des SoCs et elle présente aussi des stratégies de contremesureThe thesis studies the security of the ARM TrustZone technology in the context of complex heterogeneous SoCs. The thesis presents hardware attacks that affect elements of the SoCs architecture and it also presents countermeasure strategies
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Wang, Weihuang. "Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling." [College Station, Tex. : Texas A&M University, 2007. http://hdl.handle.net/1969.1/ETD-TAMU-2504.
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Datta, Srabosti. "POWER REDUCTION BY DYNAMICALLY VARYING SAMPLING RATE." UKnowledge, 2006. http://uknowledge.uky.edu/gradschool_theses/275.
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In modern digital audio applications, a continuous audio signal stream is sampled at a fixed sampling rate, which is always greater than twice the highest frequency of the input signal, to prevent aliasing. A more energy efficient approach is to dynamically change the sampling rate based on the input signal. In the dynamic sampling rate technique, fewer samples are processed when there is little frequency content in the samples. The perceived quality of the signal is unchanged in this technique. Processing fewer samples involves less computation work; therefore processor speed and voltage can be reduced. This reduction in processor speed and voltage has been shown to reduce power consumption by up to 40% less than if the audio stream had been run at a fixed sampling rate.
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Tapou, Monaf Sabri. "High efficiency smart voltage regulating module for green mobile computing." Thesis, Brunel University, 2014. http://bura.brunel.ac.uk/handle/2438/8285.
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In this thesis a design for a smart high efficiency voltage regulating module capable of supplying the core of modern microprocessors incorporating dynamic voltage and frequency scaling (DVS) capability is accomplished using a RISC based microcontroller to facilitate all the functions required to control, protect, and supply the core with the required variable operating voltage as set by the DVS management system. Normally voltage regulating modules provide maximum power efficiency at designed peak load, and the efficiency falls off as the load moves towards lesser values. A mathematical model has been derived for the main converter and small signal analysis has been performed in order to determine system operation stability and select a control scheme that would improve converter operation response to transients and not requiring intense computational power to realize. A Simulation model was built using Matlab/Simulink and after experimenting with tuned PID controller and fuzzy logic controllers, a simple fuzzy logic control scheme was selected to control the pulse width modulated converter and several methods were devised to reduce the requirements for computational power making the whole system operation realizable using a low power RISC based microcontroller. The same microcontroller provides circuit adaptations operation in addition to providing protection to load in terms of over voltage and over current protection. A novel circuit technique and operation control scheme enables the designed module to selectively change some of the circuit elements in the main pulse width modulated buck converter so as to improve efficiency over a wider range of loads. In case of very light loads as the case when the device goes into standby, sleep or hibernation mode, a secondary converter starts operating and the main converter stops. The secondary converter adapts a different operation scheme using switched capacitor technique which provides high efficiency at low load currents. A fuzzy logic control scheme was chosen for the main converter for its lighter computational power requirement promoting implementation using ultra low power embedded controllers. Passive and active components were carefully selected to augment operational efficiency. These aspects enabled the designed voltage regulating module to operate with efficiency improvement in off peak load region in the range of 3% to 5%. At low loads as the case when the computer system goes to standby or sleep mode, the efficiency improvent is better than 13% which will have noticeable contribution in extending battery run time thus contributing to lowering the carbon footprint of human consumption.
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Wamhoff, Jons-Tobias, Stephan Diestelhorst, Christof Fetzer, Patrick Marlier, Pascal Felber, and Dave Dice. "Selective Core Boosting: The Return of the Turbo Button." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2013. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-127748.
Full textAbstract:
Several modern multi-core architectures support the dynamic control of the CPU's clock rate, allowing processor cores to temporarily operate at speeds exceeding the operational base frequency. Conversely, cores can operate at a lower speed or be disabled altogether to save power. Such facilities are notably provided by Intel's Turbo Boost and AMD's Turbo CORE technologies. Frequency control is typically driven by the operating system which requests changes to the performance state of the processor based on the current load of the system.
In this paper, we investigate the use of dynamic frequency scaling from user space to speed up multi-threaded applications that must occasionally execute time-critical tasks or to solve problems that have heterogeneous computing requirements. We propose a general-purpose library that allows selective control of the frequency of the cores - subject to the limitations of the target architecture. We analyze the performance trade-offs and illustrate its benefits using several benchmarks and real-world workloads when temporarily boosting selected cores executing time-critical operations. While our study primarily focuses on AMD's architecture, we also provide a comparative evaluation of the features, limitations, and runtime overheads of both Turbo Boost and Turbo CORE technologies. Our results show that we can successful exploit these new hardware facilities to
accelerate the execution of key sections of code (critical paths) improving overall performance of some multi-threaded applications. Unlike prior research, we focus on performance instead of power conservation. Our results further can give guidelines for the design of hardware power management facilities and the operating system interfaces to those facilities.
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Li, Bo. "Modeling and Runtime Systems for Coordinated Power-Performance Management." Diss., Virginia Tech, 2019. http://hdl.handle.net/10919/87064.
Full textAbstract:
Emergent systems in high-performance computing (HPC) expect maximal
efficiency to achieve the goal of power budget under 20-40
megawatts for 1 exaflop set by the Department of Energy.
To optimize efficiency, emergent systems
provide multiple power-performance control techniques to
throttle different system components and scale of concurrency.
In this dissertation, we focus on three throttling techniques:
CPU dynamic voltage and frequency scaling (DVFS), dynamic memory
throttling (DMT), and dynamic concurrency throttling (DCT). We first conduct an
empirical analysis of the performance and energy trade-offs of
different architectures under the throttling techniques. We
show the impact on performance and energy consumption on Intel
x86 systems with accelerators of Intel Xeon Phi and a Nvidia
general-purpose graphics processing unit (GPGPU).
We show the trade-offs and potentials for improving efficiency.
Furthermore, we propose a parallel performance model for coordinating
DVFS, DMT, and DCT simultaneously. We present a multivariate
linear regression-based approach to approximate the impact of
DVFS, DMT, and DCT on performance for performance prediction.
Validation using 19 HPC applications/kernels on
two architectures (i.e., Intel x86 and IBM BG/Q)
shows up to 7% and 17% prediction
error correspondingly. Thereafter, we develop the metrics for
capturing the performance impact of DVFS, DMT, and DCT.
We apply the artificial neural network model to approximate
the nonlinear effects on performance impact and present
a runtime control strategy accordingly for power capping.
Our validation using
37 HPC applications/kernels shows up to a 20% performance
improvement under a given power budget compared with the Intel
RAPL-based method.Ph. D.
System efficiency on high-performance computing (HPC) systems is the key to achieving the goal of power budget for exascale supercomputers. Techniques for adjusting the performance of different system components can help accomplish this goal by dynamically controlling system performance according to application behaviors. In this dissertation, we focus on three techniques: adjusting CPU performance, memory performance, and the number of threads for running parallel applications. First, we profile the performance and energy consumption of different HPC applications on both Intel systems with accelerators and IBM BG/Q systems. We explore the trade-offs of performance and energy under these techniques and provide optimization insights. Furthermore, we propose a parallel performance model that can accurately capture the impact of these techniques on performance in terms of job completion time. We present an approximation approach for performance prediction. The approximation has up to 7% and 17% prediction error on Intel x86 and IBM BG/Q systems respectively under 19 HPC applications. Thereafter, we apply the performance model in a runtime system design for improving performance under a given power budget. Our runtime strategy achieves up to 20% performance improvement to the baseline method.
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Fanfakh, Ahmed Badri Muslim. "Energy consumption optimization of parallel applications with Iterations using CPU frequency scaling." Thesis, Besançon, 2016. http://www.theses.fr/2016BESA2021/document.
Full textAbstract:
Au cours des dernières années, l'informatique “green” est devenue un sujet important dans le calcul intensif. Cependant, les plates-formes informatiques continuent de consommer de plus en plus d'énergie en raison de l'augmentation du nombre de noeuds qui les composent. Afin de minimiser les coûts d'exploitation de ces plates-formes de nombreuses techniques ont été étudiées, parmi celles-ci, il y a le changement de la fréquence dynamique des processeurs (DVFS en anglais). Il permet de réduire la consommation d'énergie d'un CPU, en abaissant sa fréquence. Cependant, cela augmente le temps d'exécution de l'application. Par conséquent, il faut trouver un seuil qui donne le meilleur compromis entre la consommation d'énergie et la performance d'une application. Cette thèse présente des algorithmes développés pour optimiser la consommation d'énergie et les performances des applications parallèles avec des itérations synchrones et asynchrones sur des clusters ou des grilles. Les modèles de consommation d'énergie et de performance proposés pour chaque type d'application parallèle permettent de prédire le temps d'exécution et la consommation d'énergie d'une application pour toutes les fréquences disponibles.La contribution de cette thèse peut être divisé en trois parties. Tout d'abord, il s'agit d'optimiser le compromis entre la consommation d'énergie et les performances des applications parallèles avec des itérations synchrones sur des clusters homogènes. Deuxièmement, nous avons adapté les modèles de performance énergétique aux plates-formes hétérogènes dans lesquelles chaque noeud peut avoir des spécifications différentes telles que la puissance de calcul, la consommation d'énergie, différentes fréquences de fonctionnement ou encore des latences et des bandes passantes réseaux différentes. L'algorithme d'optimisation de la fréquence CPU a également été modifié en fonction de l'hétérogénéité de la plate-forme. Troisièmement, les modèles et l'algorithme d'optimisation de la fréquence CPU ont été complètement repensés pour prendre en considération les spécificités des algorithmes itératifs asynchrones.Tous ces modèles et algorithmes ont été appliqués sur des applications parallèles utilisant la bibliothèque MPI et ont été exécutés avec le simulateur Simgrid ou sur la plate-forme Grid'5000. Les expériences ont montré que les algorithmes proposés sont plus efficaces que les méthodes existantes. Ils n’introduisent qu’un faible surcoût et ne nécessitent pas de profilage au préalable car ils sont exécutés au cours du déroulement de l’applicationIn recent years, green computing has become an important topic in the supercomputing research domain. However, the computing platforms are still consuming more and more energy due to the increase in the number of nodes composing them. To minimize the operating costs of these platforms many techniques have been used. Dynamic voltage and frequency scaling (DVFS) is one of them. It can be used to reduce the power consumption of the CPU while computing, by lowering its frequency. However, lowering the frequency of a CPU may increase the execution time of the application running on that processor. Therefore, the frequency that gives the best trade-off between the energy consumption and the performance of an application must be selected.This thesis, presents the algorithms developed to optimize the energy consumption and theperformance of synchronous and asynchronous message passing applications with iterations runningover clusters or grids. The energy consumption and performance models for each type of parallelapplication predicts its execution time and energy consumption for any selected frequency accordingto the characteristics of both the application and the architecture executing this application.The contribution of this thesis can be divided into three parts: Firstly, optimizing the trade-offbetween the energy consumption and the performance of the message passing applications withsynchronous iterations running over homogeneous clusters. Secondly, adapting the energy andperformance models to heterogeneous platforms where each node can have different specificationssuch as computing power, energy consumption, available frequency gears or network’s latency andbandwidth. The frequency scaling algorithm was also modified to suit the heterogeneity of theplatform. Thirdly, the models and the frequency scaling algorithm were completely rethought to takeinto considerations the asynchronism in the communication and computation. All these models andalgorithms were applied to message passing applications with iterations and evaluated over eitherSimGrid simulator or Grid’5000 platform. The experiments showed that the proposed algorithms areefficient and outperform existing methods such as the energy and delay product. They also introducea small runtime overhead and work online without any training or profiling
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Zeng, Gang, Tetsuo Yokoyama, Hiroyuki Tomiyama, and Hiroaki Takada. "A Generalized Framework for Energy Savings in Real-Time Multiprocessor Systems." IEEE, 2008. http://hdl.handle.net/2237/12101.
Full text
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Schöne, Robert, Thomas Ilsche, Mario Bielert, Daniel Molka, and Daniel Hackenberg. "Software Controlled Clock Modulation for Energy Efficiency Optimization on Intel Processors." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-224966.
Full textAbstract:
Current Intel processors implement a variety of power saving features like frequency scaling and idle states. These mechanisms limit the power draw and thereby decrease the thermal dissipation of the processors. However, they also have an impact on the achievable performance. The various mechanisms significantly differ regarding the amount of power savings, the latency of mode changes, and the associated overhead. In this paper, we describe and closely examine the so-called software controlled clock modulation mechanism for different processor generations. We present results that imply that the available documentation is not always correct and describe when this feature can be used to improve energy efficiency. We additionally compare it against the more popular feature of dynamic voltage and frequency scaling and develop a model to decide which feature should be used to optimize inter-process synchronizations on Intel Haswell-EP processors.
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Rathnala, Prasanthi. "Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation." Thesis, University of Derby, 2017. http://hdl.handle.net/10545/621716.
Full textAbstract:
Growing usage of smart and portable electronic devices demands embedded system designers to provide solutions with better performance and reduced power consumption. Due to the new development of IoT and embedded systems usage, not only power and performance of these devices but also security of them is becoming an important design constraint. In this work, a novel aggressive scaling based on timing speculation is proposed to overcome the drawbacks of traditional DVFS and provide security from power analysis attacks at the same time. Dynamic voltage and frequency scaling (DVFS) is proven to be the most suitable technique for power efficiency in processor designs. Due to its promising benefits, the technique is still getting researchers attention to trade off power and performance of modern processor designs. The issues of traditional DVFS are: 1) Due to its pre-calculated operating points, the system is not able to suit to modern process variations. 2) Since Process Voltage and Temperature (PVT) variations are not considered, large timing margins are added to guarantee a safe operation in the presence of variations. The research work presented here addresses these issues by employing aggressive scaling mechanisms to achieve more power savings with increased performance. This approach uses in-situ timing error monitoring and recovering mechanisms to reduce extra timing margins and to account for process variations. A novel timing error detection and correction mechanism, to achieve more power savings or high performance, is presented. This novel technique has also been shown to improve security of processors against differential power analysis attacks technique. Differential power analysis attacks can extract secret information from embedded systems without knowing much details about the internal architecture of the device. Simulated and experimental data show that the novel technique can provide a performance improvement of 24% or power savings of 44% while occupying less area and power overhead. Overall, the proposed aggressive scaling technique provides an improvement in power consumption and performance while increasing the security of processors from power analysis attacks.
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Wamhoff, Jons-Tobias. "Exploiting Speculative and Asymmetric Execution on Multicore Architectures." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2015. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-163250.
Full textAbstract:
The design of microprocessors is undergoing radical changes that affect the performance and reliability of hardware and will have a high impact on software development. Future systems will depend on a deep collaboration between software and hardware to cope with the current and predicted system design challenges. Instead of higher frequencies, the number of processor cores per chip is growing. Eventually, processors will be composed of cores that run at different speeds or support specialized features to accelerate critical portions of an application. Performance improvements of software will only result from increasing parallelism and introducing asymmetric processing. At the same time, substantial enhancements in the energy efficiency of hardware are required to make use of the increasing transistor density. Unfortunately, the downscaling of transistor size and power will degrade the reliability of the hardware, which must be compensated by software.
In this thesis, we present new algorithms and tools that exploit speculative and asymmetric execution to address the performance and reliability challenges of multicore architectures. Our solutions facilitate both the assimilation of software to the changing hardware properties as well as the adjustment of hardware to the software it executes. We use speculation based on transactional memory to improve the synchronization of multi-threaded applications. We show that shared memory synchronization must not only be scalable to large numbers of cores but also robust such that it can guarantee progress in the presence of hardware faults. Therefore, we streamline transactional memory for a better throughput and add fault tolerance mechanisms with a reduced overhead by speculating optimistically on an error-free execution. If hardware faults are present, they can manifest either in a single event upset or crashes and misbehavior of threads. We address the former by applying transactions to checkpoint and replicate the state such that threads can correct and continue their execution.
The latter is tackled by extending the synchronization such that it can tolerate crashes and misbehavior of other threads. We improve the efficiency of transactional memory by enabling a lightweight thread that always wins conflicts and significantly reduces the overheads. Further performance gains are possible by exploiting the asymmetric properties of applications. We introduce an asymmetric instrumentation of transactional code paths to enable applications to adapt to the underlying hardware. With explicit frequency control of individual cores, we show how applications can expose their possibly asymmetric computing demand and dynamically adjust the hardware to make a more efficient usage of the available resources.
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Miftakhutdinov, Rustam Raisovich. "Performance prediction for dynamic voltage and frequency scaling." Thesis, 2014. http://hdl.handle.net/2152/26939.
Full textAbstract:
This dissertation proves the feasibility of accurate runtime prediction of processor performance under frequency scaling. The performance predictors developed in this dissertation allow processors capable of dynamic voltage and frequency scaling (DVFS) to improve their performance or energy efficiency by dynamically adapting chip or core voltages and frequencies to workload characteristics. The dissertation considers three processor configurations: the uniprocessor capable of chip-level DVFS, the private cache chip multiprocessor capable of per-core DVFS, and the shared cache chip multiprocessor capable of per-core DVFS. Depending on processor configuration, the presented performance predictors help the processor realize 72–85% of average oracle performance or energy efficiency gains.text
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Arun, R. "Petri Net Model Based Energy Optimization Of Programs Using Dynamic Voltage And Frequency Scaling." Thesis, 2011. https://etd.iisc.ac.in/handle/2005/2013.
Full textAbstract:
High power dissipation and on-chip temperature limit performance and affect reliability in modern microprocessors. For servers and data centers, they determine the cooling cost, whereas for handheld and mobile systems, they limit the continuous usage of these systems. For mobile systems, energy consumption affects the battery life. It can not be ignored for desktop and server systems as well, as the contribution of energy continues to go up in organizations’ budgets, influencing strategic decisions, and its implications on the environment are getting appreciated. Intelligent trade-offs involving these quantities are critical to meet the performance demands of many modern applications.
Dynamic Voltage and Frequency Scaling (DVFS) offers a huge potential for designing
trade-offs involving energy, power, temperature and performance of computing systems. In our work, we propose and evaluate DVFS schemes that aim at minimizing energy consumption while meeting a performance constraint, for both sequential and parallel applications.
We propose a Petri net based program performance model, parameterized by application properties, microarchitectural settings and system resource configuration, and use this model to find energy efficient DVFS settings. We first propose a DVFS scheme
using this model for sequential programs running on single core multiple clock domain
(MCD) processors, and evaluate this on a MCD processor simulator. We then extend
this scheme for data parallel (Single Program Multiple Data style) applications, and then generalize it for stream applications as well, and evaluate these two schemes on a full system CMP simulator. Our experimental evaluation shows that the proposed schemes achieve significant energy savings for a small performance degradation.
27
Arun, R. "Petri Net Model Based Energy Optimization Of Programs Using Dynamic Voltage And Frequency Scaling." Thesis, 2011. http://etd.iisc.ernet.in/handle/2005/2013.
Full textAbstract:
High power dissipation and on-chip temperature limit performance and affect reliability in modern microprocessors. For servers and data centers, they determine the cooling cost, whereas for handheld and mobile systems, they limit the continuous usage of these systems. For mobile systems, energy consumption affects the battery life. It can not be ignored for desktop and server systems as well, as the contribution of energy continues to go up in organizations’ budgets, influencing strategic decisions, and its implications on the environment are getting appreciated. Intelligent trade-offs involving these quantities are critical to meet the performance demands of many modern applications.
Dynamic Voltage and Frequency Scaling (DVFS) offers a huge potential for designing
trade-offs involving energy, power, temperature and performance of computing systems. In our work, we propose and evaluate DVFS schemes that aim at minimizing energy consumption while meeting a performance constraint, for both sequential and parallel applications.
We propose a Petri net based program performance model, parameterized by application properties, microarchitectural settings and system resource configuration, and use this model to find energy efficient DVFS settings. We first propose a DVFS scheme
using this model for sequential programs running on single core multiple clock domain
(MCD) processors, and evaluate this on a MCD processor simulator. We then extend
this scheme for data parallel (Single Program Multiple Data style) applications, and then generalize it for stream applications as well, and evaluate these two schemes on a full system CMP simulator. Our experimental evaluation shows that the proposed schemes achieve significant energy savings for a small performance degradation.
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Prabhu, Subodh. "Ocin_tsim - A DVFS Aware Simulator for NoC Design Space Exploration and Optimization." 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7798.
Full textAbstract:
Networks-on-Chip (NoCs) are a general purpose, scalable replacement for shared
medium wired interconnects offering many practical applications in industry. Dynamic
Voltage Frequency Scaling (DVFS) is a technique whereby a chip?s voltage-frequency
levels are varied at run time, often used to conserve dynamic power. Various DVFSbased
NoC optimization techniques have been proposed. However, due to the resources
required to validate architectural decisions through prototyping, few are implemented.
As a result, designers are faced with a lack of insight into potential power savings or
performance gains at early architecture stages.
This thesis proposes a DVFS aware NoC simulator with support for per node
power-frequency modeling to allow fine-tuning of such optimization techniques early on
in the design cycle. The proposed simulator also provides a framework for
benchmarking various candidate strategies to allow selective prototyping and
optimization.
As part of the research, DVFS extensions were built for an existing NoC
performance simulator and released for public use. This thesis presents some of the preliminary results from our simulator that show the average power consumed per node
for all the benchmarks in SPLASH 2 benchmark suite [74] to be quite similar to each
other. This thesis also serves as a technical manual for the simulator extensions.
Important links for downloading and using the simulator are provided at the end of this
document in Appendix C.
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Govindan, Madhu Sarava. "E³ : energy-efficient EDGE architectures." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-08-1934.
Full textAbstract:
Increasing power dissipation is one of the most serious challenges facing designers in the microprocessor industry. Power dissipation, increasing wire delays, and increasing design complexity have forced industry to embrace multi-core architectures or chip multiprocessors (CMPs). While CMPs mitigate wire delays and design complexity, they do not directly address single-threaded performance. Additionally, programs must be parallelized, either manually or automatically, to fully exploit the performance of CMPs. Researchers have recently proposed an architecture called Explicit Data Graph Execution (EDGE) as an alternative to conventional CMPs. EDGE architectures are designed to be technology-scalable and to provide good single-threaded performance as well as exploit other types of parallelism including data-level and thread-level parallelism. In this dissertation, we examine the energy efficiency of a specific EDGE architecture called TRIPS Instruction Set Architecture (ISA) and two microarchitectures called TRIPS and TFlex that implement the TRIPS ISA. TRIPS microarchitecture is a first-generation design that proves the feasibility of the TRIPS ISA and distributed tiled microarchitectures. The second-generation TFlex microarchitecture addresses key inefficiencies of the TRIPS microarchitecture by matching the resource needs of applications to a composable hardware substrate. First, we perform a thorough power analysis of the TRIPS microarchitecture. We describe how we develop architectural power models for TRIPS. We then improve power-modeling accuracy using hardware power measurements on the TRIPS prototype combined with detailed Register Transfer Level (RTL) power models from the TRIPS design. Using these refined architectural power models and normalized power modeling methodologies, we perform a detailed performance and power comparison of the TRIPS microarchitecture with two different processors: 1) a low-end processor designed for power efficiency (ARM/XScale) and 2) a high-end superscalar processor designed for high performance (a variant of Power4). This detailed power analysis provides key insights into the advantages and disadvantages of the TRIPS ISA and microarchitecture compared to processors on either end of the performance-power spectrum. Our results indicate that the TRIPS microarchitecture achieves 11.7 times better energy efficiency compared to ARM, and approximately 12% better energy efficiency than Power4, in terms of the Energy-Delay-Squared (ED²) metric. Second, we evaluate the energy efficiency of the TFlex microarchitecture in comparison to TRIPS, ARM, and Power4. TFlex belongs to a class of microarchitectures called Composable Lightweight Processors (CLPs). CLPs are distributed microarchitectures designed with simple cores and are highly configurable at runtime to adapt to resource needs of applications. We develop power models for the TFlex microarchitecture based on the validated TRIPS power models. Our quantitative results indicate that by better matching execution resources to the needs of applications, the composable TFlex system can operate in both regimes of low power (similar to ARM) and high performance (similar to Power4). We also show that the composability feature of TFlex achieves a signification improvement (2 times) in the ED² metric compared to TRIPS. Third, using TFlex as our experimental platform, we examine the efficacy of processor composability as a potential performance-power trade-off mechanism. Most modern processors support a form of dynamic voltage and frequency scaling (DVFS) as a performance-power trade-off mechanism. Since the rate of voltage scaling has slowed significantly in recent process technologies, processor designers are in dire need of alternatives to DVFS. In this dissertation, we explore processor composability as an architectural alternative to DVFS. Through experimental results we show that processor composability achieves almost as good performance-power trade-offs as pure frequency scaling (no changes in supply voltages), and a much better performance-power trade-off compared to voltage and frequency scaling (both supply voltage and frequency change). Next, we explore the effects of additional performance-improving techniques for the TFlex system on its energy efficiency. Researchers have proposed a variety of techniques for improving the performance of the TFlex system. These include: (1) block mapping techniques to trade off intra-block concurrency with communication across the operand network; (2) predicate prediction and (3) operand multi-cast/broadcast mechanism. We examine each of these mechanisms in terms of its effect on the energy efficiency of TFlex, and our experimental results demonstrate the effects of operand communication, and speculation on the energy efficiency of TFlex. Finally, this dissertation evaluates a set of fine-grained power management (FGPM) policies for TFlex: instruction criticality and controlled speculation. These policies rely on a temporally and spatially fine-grained dynamic voltage and frequency scaling (DVFS) mechanism for improving power efficiency. The instruction criticality policy seeks to improve power efficiency by mapping critical computation in a program to higher performance-power levels, and by mapping non-critical computation to lower performance-power levels. Controlled speculation policy, on the other hand, maps blocks that are highly likely to be on correct execution path in a program to higher performance levels, and the other blocks to lower performance levels. Our experimental results indicate that idealized instruction criticality and controlled speculation policies improve the operating range and flexibility of the TFlex system. However, when the actual overheads of fine-grained DVFS, especially energy conversion losses of voltage regulator modules (VRMs), are considered the power efficiency advantages of these idealized policies quickly diminish. Our results also indicate that the current conversion efficiencies of on-chip VRMs need to improve to as high as 95% for the realistic policies to be feasible.text
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Σπηλιόπουλος, Βασίλειος. "Προσαρμογή συχνότητας και τάσης λειτουργίας για τη βελτιστοποίηση κατανάλωσης ενέργειας επεξεργαστών." Thesis, 2009. http://nemertes.lis.upatras.gr/jspui/handle/10889/2909.
Full textAbstract:
Η σύγχρονη αρχιτεκτονική στρέφεται σε λύσεις που έχουν ως στόχο την εξοικονόμηση ενέργειας, χωρίς όμως να επιβαρύνεται σε μεγάλο βαθμό η απόδοση του επεξεργαστή. Ιδιαίτερα οι υπερβαθμωτοί (superscalar) επεξεργαστές που επιτρέπουν εκτέλεση εκτός σειράς (out-of-order execution) διακρίνονται από υψηλή κατανάλωση ενέργειας, εξαιτίας των πολύπλοκων δομών που χρησιμοποιούν για την αύξηση της απόδοσης.
Η δυναμική ρύθμιση τάσης – συχνότητας (DVFS) αποτελεί μία ευρέως χρησιμοποιούμενη τεχνική για την επίτευξη εξοικονόμησης ενέργειας. Μειώνοντας τη συχνότητα λειτουργίας ενός κυκλώματος, είναι δυνατόν να μειωθεί και η τάση τροφοδοσίας του κυκλώματος. Με τον τρόπο αυτό ελαττώνεται και η ενέργεια που καταναλώνει το κύκλωμα.
Σκοπός της εργασίας είναι η ανάπτυξη ενός μηχανισμού πραγματικού χρόνου που θα ρυθμίζει τη συχνότητα και την τάση λειτουργίας ενός superscalar, out-of-order επεξεργαστή ώστε να επιτυγχάνεται εξοικονόμηση ενέργειας χωρίς μεγάλη μείωση της απόδοσης του επεξεργαστή. Αυτό μπορεί να επιτευχθεί ελαττώνοντας τη συχνότητα και την τάση κατά τις περιόδους που ο επεξεργαστής εκτελεί πολλές λειτουργίες μνήμης.
Η εξομοίωση του μηχανισμού μας για μία σειρά από μετροπρογράμματα δείχνει ότι μπορούμε να επιτύχουμε μεγάλη εξοικονόμηση ενέργειας χωρίς σημαντική αύξηση του χρόνου εκτέλεσης των προγραμμάτων.Modern research in computer architecture focuses on techniques whose purpose is to save energy, without much loss in processor's performance. Especially superscalar processors that allow out of order execution are characterized by high energy consumption, because of the complex structures the use in order to increase performance. Dynamic Voltage - Frequency Scaling (DVFS) is a widely used technique for energy saving. Reducing the frequency of the processor's clock, it is possible to reduce the supply voltage. In this way the consumed energy is also reduced. The purpose of this diploma thesis is to create a real time mechanism that will scale the frequency and the voltage of a superscalar, out of order processor so that the processor saves energy without much loss in processor's performance. This can be made by reducing the frequency and the voltage during the periods that the processor executes many memory functions. The simulation of our mechanism for a variety of benchmarks proved that we can save much energy without much increase in the benchmark's execution time.
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"Enabling dynamic voltage and frequency scaling in multicore architectures." UNIVERSITY OF COLORADO AT BOULDER, 2010. http://pqdtopen.proquest.com/#viewpdf?dispub=1473683.
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Hsu, An-Jia, and 許安嘉. "iVisual: An Intelligent Vision Processor With Dynamic Voltage and Frequency Scaling." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/65444071204522740913.
Full textAbstract:
碩士臺灣大學
電子工程學研究所
98
An high frame rate vision processor with Dynamic voltage and frequency scaling is presented in this thesis. The peak performance of this processor is 240 GOPS which consumes 185 mW at 156 MHz. The chip is implemented on a 3.95mmx3.95mm die in a UMC 90nm Logic&Mixed-Mode 1P9M Low-K Process. In recent years, applications of intelligent vision processor can be seen everywhere. Systems applying intelligent vision processors can work 24 hours a day and 7 days a week, waiting for the signals of interest and response immediately once some situation happens. This nature can be widely used in surveillance system, intelligent vehicles, home-care system and human-machine interface. To fulfill the needs for various applications, vision processors are usually required to have the ability of robust and rapid object detection and very high throughput. In this thesis we represent a vision processor which can achieve more than 100 frames per second computation for 128x128 8-bit gray level images. We’ll show that this vision processor can be widely used in surveillance system and intelligent vehicle. However, the demanded throughput of vision processor is not invariable. Under different working environment the vision processor does not always works at peak performance. Under such situation, DVFS is believed to be the most efficient way to achieve a low-power design. Here we introduce DVFS engines into the vision processor. According the demanded throughput DVFS engines can dynamically adjust working frequency and supply voltage. In our design, the DVFS engine can reduce 70% of the power consumption.
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Chen, Ya Ting, and 陳雅婷. "A Bus Circuit Design with Dynamic Voltage/Frequency Scaling and Repeater Insertion." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/99647596644232328251.
Full textAbstract:
碩士國立交通大學
電機與控制工程系所
97
This thesis proposes a bus circuit using repeater insertion to reduce its power consumption and area. Moreover, we use a timing measurement circuit to estimate eye opening and jitter. According to the eye opening, we can determine if the supply voltage or the frequency is adequate for the task. If the supply voltage or the frequency disagrees with the task, we can dynamically change the supply voltage or the frequency to make the signal correctly transferred. For the data generation, a pseudorandom binary sequence generator has been used to generate eight parallel outputs and a divider to generate a clock signal. The clock’s trigger location is at the middle of pseudorandom data. The data and the clock have been transferred to the bus circuit which is 10mm in length. Finally, we use a timing measurement circuit to estimate the jitter. This chip is implemented in TSMC 0.13um RF CMOS process. On a 1.2V power supply, the PRBS generator consumes 1.36mW, the global interconnects consume 22.18mW (each interconnect consumes 2.77mW), and the timing measurement circuit consumes 9.75mW.
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Hsu, Chun-Po, and 許竣博. "A CPU Utilization-oriented Memory-aware Dynamic Voltage and Frequency Scaling Algorithm." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/ktd9y6.
Full textAbstract:
碩士國立臺北科技大學
資訊工程系研究所
99
Saving energy is an important target for portable devices which are powered by batteries. Among low power mechanisms, DVFS is an efficient method which can reduce energy consumption while tasks are running. In our previous studies, we found a relationship between the memory access rate and the frequency which minimizes the energy consumption. We have proposed an equation named MAR-CSE which represents this relationship and is used to perform dynamic frequency selection. However, the MAR-CSE equation cannot handle all the cases. It may cause the energy consumption to be increased inversely. For example, if both of the memory access rate and the number of instruction executed are low, the system will scale up the frequency according to the MAR-CSE equation. This may not be correct, because the system could be in an I/O state. A low frequency will be more suitable for this case. In this thesis, we improve our MAR-CSE-based DVFS algorithm. The CPU utilization is considered in the algorithm. We use the MiBench benchmarks and some utility programs in Linux to find the thresholds which can distinguish among I/O bound, memory bound, and CPU bound according to the memory access rate and the CPU utilization information. We have implemented the algorithm in the Linux kernel based on the CPUfreq subsystem, a processor power management architecture for Linux. The EDP metric is used to prove our algorithm is good at energy saving and low performance loss.
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Tang, Yi Lun, and 唐翊倫. "A Cache-Utilization Based Dynamic Voltage Frequency Scaling Mechanism for Reliability Enhancements." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/05665302847329800767.
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碩士國立清華大學
資訊工程學系
104
Dynamic Voltage-Frequency Scaling (DVFS) has been proposed for a good balance between power and performance in processor design. Various DVFS methods are now applied to modern processor designs. These techniques sometimes make processors and cache operate at lower supplying voltage for energy saving. But the scaled-down supplying voltage greatly decreases the reliability of cache at the same time. To address this issue, we propose a cache-utilization based DVFS mechanism utilizing 7T/14T cache architecture [1] for reliability enhancements. In our method, under ultra-low voltage, the cache system can still operate in a reliable state. Different from conventional DVFS, in order to combine perfectly with 7T/14T cache architecture, we consider not only CPI behaviors but also a new metric -- cache utilization, which we use to estimate the effectiveness of cache capacity. A set of experiments to examine our method are conducted in three degrees: reliability, power, and performance. The results show that compared to the online learning DVFS method [2] using safe supply voltage, reliability by our method improves in average from 0.246 ECC errors per day to 0.113, with 2.2% energy reduction and 5.5% speed-up in performance. Moreover, compared to the online learning DVFS method using ultra-low voltage, reliability by our method improves in average from 522.85 ECC errors per day to 0.113, and 1.5% reduction in energy and 5.5% speed-up in performance.
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Chen, Shih-Chang, and 陳世昌. "Energy Aware Dual-Speed Dynamic Voltage and Frequency Scaling on Portable Devices." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/rva5me.
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碩士國立臺北科技大學
資訊工程系研究所
96
In recent years, the use of mobile devices has become highly integrated into people’s daily lives. The study of power consumption has become an important system design issue on portable devices. Many mobile systems such as PDAs, smart phones, and laptops have currently supported dynamic voltage and frequency scaling (DVFS) during the system operating, and DVFS is considered as one of most efficient techniques to decrease energy consumption. This paper demonstrates an adaptive hardware and software systems architecture on mobile devices. We modify software power management framework, which is based on Intel® XScaleTM platforms, and take advantage of monitoring the performance monitoring unit (PMU) for the usage of processor to adjust voltage and frequency dynamically in order to reduce power consumption on system, meanwhile, extend the lifetime of battery. This paper is experimented on Creator PXA270 development board, and measure relative energy consumption with several benchmarks. According to the characters of different programs, we calculate the critical speed of minimal energy consumption, and present a runtime algorithm (Energy Aware - Dynamic Voltage and Frequency Scaling, EA-DVFS), and then we implement in Linux kernel. Results of the experiments showed the energy consumption of system, which used EA-DVFS algorithm, is lower 20 percent at least than the one without the algorithm. This study mainly investigates the dynamic relationship between processor utilization and energy consumption, as well as providing a better understanding of how characters of programs related to the strategy use.
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陳則翔, Tse-Hsiang Chen, and 陳則翔. "Design and Implementation of an EDP-based Dynamic Voltage and Frequency Scaling Mechanism." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/y97n82.
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碩士國立臺北科技大學
資訊工程系研究所
100
Energy saving is an important issue, especially for the handheld devices. The dynamic voltage and frequency scaling (DVFS) is one of the mechanisms in the energy saving research area. DVFS can be used to reduce energy consumption of a processor while tasks are running. However, reducing the frequency for a processor might not induce minimized energy consumption, since the execution time will be extended due to the frequency being decreased and the program will consume extra energy during this extended period. As a result, the induced extra energy could be higher than what has been saved. Experiment results indicated that the execution time is an important factor for the energy consumption. The EDP (energy and delay product) metric[1] has been used to evaluate the trade-off between energy consumption and execution time. In this thesis, an approximation equation based on the correlation of the memory access rate and the critical speed for the minimum EDP metric is conducted for frequency and voltage prediction. The correlation equation can thus be deduced from the relationship and used at task execution time to find a frequency. According to the correlation equation, an appropriate frequency (called CSEDP) can be found to minimize the EDP. The energy saving DVFS algorithm based on the correlation equation is presented in this thesis. The algorithm has been implemented on Linux as a kernel-space power manager. The experiment result shows that our algorithm performed better than the commonly used Linux Ondemand Governor[2]. It indicates that the EDP values are lower than that of Ondemand from 0.429% to 14.596% with 5.27% in average.
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Chen, Yusheng, and 陳裕生. "Design and Implementation of Dynamic Voltage and Frequency Scaling for Embedded Java Virtual Machine." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/whh657.
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碩士國立交通大學
資訊工程系所
94
Dynamic voltage and frequency Scaling (DVFS) is recognized as one of the most effective power reduction techniques. JAVA is getting popular in mobile embedded systems in recent year. Thus we propose a low-power research platform on an embedded JVM and implement DVFS on it. We refer to an accurate DVFS algorithm which calculates proper frequency of a program according to the ratio of on-chip computation time to off-chip access time. Proposed methodology for estimating the ratio of on-chip computation time to off-chip access time can be applied on defacement platforms. On our experiment platform, average error of estimations is less than 8%. Implemented design contains two schemes. Proposed interval-based design reduces 12.04%~28.68% energy consumption of the CPU with 15.89%~ 41.16% performance losses. We also experiment the potential of method-based design. And we conclude that method-based design is not suitable for embedded JVMs.
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Wang, Chi Tsung, and 王啟宗. "On the Design of Battery-aware Dynamic Voltage and Frequency Scaling for Sensor Node." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/11702203168721062445.
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碩士輔仁大學
資訊工程學系
100
Sensors are often distributed in rather adverse and even dangerous environments in wireless sensor network (WSN). It is difficult to change batteries of sensor nodes manually. Therefore, maximizing the battery life and effective power consumption have become hot research fields of WSN. Generally speaking, sensors in active mode are idle most of the time. Since most available sensors are operating on a single frequency, which indicating that same CPU frequency is used whether in working or in idle mode. It will result in unnecessary waste of energy if CPU were operated in high operating frequency during idle mode. In this thesis, we integrate DVFS (Dynamic voltage frequency scaling) mechanism into sensor node, and use the battery remaining energy as a criterion by adjusting CPU frequency to achieve energy-efficiency. According to the experimental results, the battery’s lifetime can be prolonged approximately 86% compared to single-frequency sensor and 27% compared to DVFS mechanism.
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Su, Wei-Siang, and 蘇煒翔. "A 0.5V/1.0V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/87345556199303855073.
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碩士國立中正大學
資訊工程研究所
101
In recent years, biomedical electronic applications, such as biological signal monitoring devices, implantable medical devices, and wireless body sensors become more and more popular now. In these battery-powered systems, low energy is a primary concern to increase the system operating time. Therefore, power management is an important issue for designing these devices. Dynamic voltage and frequency scaling (DVFS) serves an effective means to reduce the dynamic power consumption of the system. Moreover, the duty-cycle control of the power switch can further reduce the standby power consumption of the system. However, since reducing the supply voltage, circuit will be slowed down, and become sensitive to the PVT Variations. Thus, the ultra-low voltage is usually adopted in the low frequency applications. There are many PLLs / DLLs provide the clock of I/O interface. Traditionally, PLL / DLL usually has long lock-in time. Thus, they can’t be turned off for reducing the standby power consumption. When the system is switched to the sleeping mode, the continuous operating PLLs often dominate the standby power consumption of the system. Therefore, in this thesis, we propose a fast lock-in ADPLL with low power consumption for supporting DVFS scheme. In addition, the test chip is implemented and verified in 90nm CMOS process with standard cells.
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Trescases, Olivier. "A high-frequency, soft-switching DC-DC converter for dynamic voltage scaling in VLSI loads." 2004. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=95046&T=F.
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Chang, Ming-Feng, and 張銘峰. "Design of Dynamic Voltage and Frequency Scaling Algorithms for Energy Efficiency Applications on Embedded System." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/ek8a9z.
Full textAbstract:
博士國立臺北科技大學
資訊工程系研究所
104
Energy efficiency becomes a critical consideration in computer engineering due to the rise of mobile, battery-powered devices. Nowadays, the modern hardware provides many features for reducing power and energy that require effective software control. Dynamic voltage and frequency scaling (DVFS) is a well-known and efficient technique for reducing power. The central idea of DVFS technique on general-purpose applications is to supply a minimal voltage and frequency when the CPU is in the idle mode. This dissertation proposes different types of DVFS approaches, including: lowest energy regression, decoding video DVFS and scheduling based DVFS, for different type of applications to predict the computing complexity and supply a just-enough voltage and frequency setting. This dissertation can be divided into three parts: First, the existence of a critical speed and the memory access rate-critical speed equation (MAR-CSE) is proved theoretically and practically. A lowest energy DVFS boundary for Dynamic Voltage and Frequency Scaling is defined. Secondly, a table-based DVFS mechanism for frame decoding is proposed that can effectively reduce the power consumption of a processor by exploiting the frame-decoding complexity features. Finally, a novel scheduling based DVFS approach is proposed that schedules applications to cores in a multi-core system with homogeneous cores. Taking advantage of all energy-saving opportunities requires the detailed platform, implementation and environmental information. From the experiment results, we reach the exciting conclusion that near-optimal power management is possible on real operating systems, with certain platforms.
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Tsung-YuHsieh and 謝宗諭. "An Effective Dynamic Thermal Management Using Proactive Task Scheduler with Dynamic Voltage and Frequency Scaling for Three Dimensional Multi-Processor Systems." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/uzwzf7.
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Mochocki, Bren Christopher. "The impact of dynamic voltage and frequency scaling on the energy consumption, schedulability and predictability of real-time embedded systems." 2006. http://etd.nd.edu/ETD-db/theses/available/etd-12052006-163806/.
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Thesis (Ph. D.)--University of Notre Dame, 2006.Thesis directed by Xiaobo (Sharon) Hu for the Department of Computer Science and Engineering. "December 2006." Includes bibliographical references (leaves 174-183).
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"System Level Power and Thermal Management on Embedded Processors." Doctoral diss., 2012. http://hdl.handle.net/2286/R.I.14683.
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abstract: Semiconductor scaling technology has led to a sharp growth in transistor counts. This has resulted in an exponential increase on both power dissipation and heat flux (or power density) in modern microprocessors. These microprocessors are integrated as the major components in many modern embedded devices, which offer richer features and attain higher performance than ever before. Therefore, power and thermal management have become the significant design considerations for modern embedded devices. Dynamic voltage/frequency scaling (DVFS) and dynamic power management (DPM) are two well-known hardware capabilities offered by modern embedded processors. However, the power or thermal aware performance optimization is not fully explored for the mainstream embedded processors with discrete DVFS and DPM capabilities. Many key problems have not been answered yet. What is the maximum performance that an embedded processor can achieve under power or thermal constraint for a periodic application? Does there exist an efficient algorithm for the power or thermal management problems with guaranteed quality bound? These questions are hard to be answered because the discrete settings of DVFS and DPM enhance the complexity of many power and thermal management problems, which are generally NP-hard. The dissertation presents a comprehensive study on these NP-hard power and thermal management problems for embedded processors with discrete DVFS and DPM capabilities. In the domain of power management, the dissertation addresses the power minimization problem for real-time schedules, the energy-constrained make-span minimization problem on homogeneous and heterogeneous chip multiprocessors (CMP) architectures, and the battery aware energy management problem with nonlinear battery discharging model. In the domain of thermal management, the work addresses several thermal-constrained performance maximization problems for periodic embedded applications. All the addressed problems are proved to be NP-hard or strongly NP-hard in the study. Then the work focuses on the design of the off-line optimal or polynomial time approximation algorithms as solutions in the problem design space. Several addressed NP-hard problems are tackled by dynamic programming with optimal solutions and pseudo-polynomial run time complexity. Because the optimal algorithms are not efficient in worst case, the fully polynomial time approximation algorithms are provided as more efficient solutions. Some efficient heuristic algorithms are also presented as solutions to several addressed problems. The comprehensive study answers the key questions in order to fully explore the power and thermal management potentials on embedded processors with discrete DVFS and DPM capabilities. The provided solutions enable the theoretical analysis of the maximum performance for periodic embedded applications under power or thermal constraints.Dissertation/Thesis
Ph.D. Computer Science 2012
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Wamhoff, Jons-Tobias. "Exploiting Speculative and Asymmetric Execution on Multicore Architectures." Doctoral thesis, 2014. https://tud.qucosa.de/id/qucosa%3A28598.
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The design of microprocessors is undergoing radical changes that affect the performance and reliability of hardware and will have a high impact on software development. Future systems will depend on a deep collaboration between software and hardware to cope with the current and predicted system design challenges. Instead of higher frequencies, the number of processor cores per chip is growing. Eventually, processors will be composed of cores that run at different speeds or support specialized features to accelerate critical portions of an application. Performance improvements of software will only result from increasing parallelism and introducing asymmetric processing. At the same time, substantial enhancements in the energy efficiency of hardware are required to make use of the increasing transistor density. Unfortunately, the downscaling of transistor size and power will degrade the reliability of the hardware, which must be compensated by software.
In this thesis, we present new algorithms and tools that exploit speculative and asymmetric execution to address the performance and reliability challenges of multicore architectures. Our solutions facilitate both the assimilation of software to the changing hardware properties as well as the adjustment of hardware to the software it executes. We use speculation based on transactional memory to improve the synchronization of multi-threaded applications. We show that shared memory synchronization must not only be scalable to large numbers of cores but also robust such that it can guarantee progress in the presence of hardware faults. Therefore, we streamline transactional memory for a better throughput and add fault tolerance mechanisms with a reduced overhead by speculating optimistically on an error-free execution. If hardware faults are present, they can manifest either in a single event upset or crashes and misbehavior of threads. We address the former by applying transactions to checkpoint and replicate the state such that threads can correct and continue their execution.
The latter is tackled by extending the synchronization such that it can tolerate crashes and misbehavior of other threads. We improve the efficiency of transactional memory by enabling a lightweight thread that always wins conflicts and significantly reduces the overheads. Further performance gains are possible by exploiting the asymmetric properties of applications. We introduce an asymmetric instrumentation of transactional code paths to enable applications to adapt to the underlying hardware. With explicit frequency control of individual cores, we show how applications can expose their possibly asymmetric computing demand and dynamically adjust the hardware to make a more efficient usage of the available resources.