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Dissertations / Theses on the topic 'Dynamic Voltage and Frequency Scaling (DVFS)'

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Published: 4 June 2021

Last updated: 25 July 2025

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1

Rountree, Barry. "Theory and Practice of Dynamic Voltage/Frequency Scaling in the High Performance Computing Environment." Diss., The University of Arizona, 2009. http://hdl.handle.net/10150/305368.

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This dissertation provides a comprehensive overview of the theory and practice of Dynamic Voltage/Frequency Scaling (DVFS) in the High Performance Computing (HPC) environment. We summarize the overall problem as follows: how can the same level of computational performance be achieved using less electrical power? Equivalently, how can computational performance be increased using the same amount of electrical power? In this dissertation we present performance and architecture models of DVFS as well as the Adagio runtime system. The performance model recasts the question as an optimization proble

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2

Saha, Sonal. "An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms." Thesis, Virginia Tech, 2011. http://hdl.handle.net/10919/35035.

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Dynamic voltage and frequency scaling (DVFS) is an extensively studied energy manage- ment technique, which aims to reduce the energy consumption of computing platforms by dynamically scaling the CPU frequency. Real-Time DVFS (RT-DVFS) is a branch of DVFS, which reduces CPU energy consumption through DVFS, while at the same time ensures that task time constraints are satisfied by constructing appropriate real-time task schedules. The literature presents numerous RT-DVFS scheduling algorithms, which employ different tech- niques to utilize the CPU idle time to scale the frequency. Many of these

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Clark, Mark A. "Dynamic Voltage/Frequency Scaling and Power-Gating of Network-on-Chip with Machine Learning." Ohio University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1544105215810566.

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4

Li, Juan. "Application-Directed DVFS using Multiple Clock Domains on Graphics Hardware." Digital WPI, 2009. https://digitalcommons.wpi.edu/etd-theses/85.

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As handheld devices have become increasingly popular, powerful programmable graphics hardware for mobile and handheld devices has been deployed. While many resources on mobile devices are limited, the predominant problem for mobile devices is their limited battery power. Several techniques have been proposed to increase the energy efficiency of mobile applications and improve battery life. In this thesis, we propose a new dynamic voltage and frequency scaling (DVFS) on Graphics Processing Units (GPU). In most cases, cues within the graphics appli- cation can be used to predict portions of a GP

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Muhammad, F. "Ordonnancement de tâches efficace et à complexité maîtrisée pour des systèmes temps-réel." Phd thesis, Université de Nice Sophia-Antipolis, 2009. http://tel.archives-ouvertes.fr/tel-00454616.

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Les performances des algorithmes d'ordonnancement ont un impact direct sur les performances du système complet. Les algorithmes d'ordonnancement temps réel possèdent des bornes théoriques d'ordonnançabilité optimales mais cette optimalité est souvent atteinte au prix d'un nombre élevé d'événements d'ordonnancement à considérer (préemptions et migrations de tâches) et d'une complexité algorithmique importante. Notre opinion est qu'en exploitant plus efficacement les paramètres des tâches il est possible de rendre ces algorithmes plus efficaces et à coût maitrisé, et ce dans le but d'améliorer l

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6

Shiomi, Jun. "Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits." Kyoto University, 2017. http://hdl.handle.net/2433/228252.

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Bhatti, K. "Energy-aware Scheduling for Multiprocessor Real-time Systems." Phd thesis, Université de Nice Sophia-Antipolis, 2011. http://tel.archives-ouvertes.fr/tel-00599980.

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Les applications temps réel modernes deviennent plus exigeantes en termes de ressources et de débit amenant la conception d'architectures multiprocesseurs. Ces systèmes, des équipements embarqués au calculateur haute performance, sont, pour des raisons d'autonomie et de fiabilité, confrontés des problèmes cruciaux de consommation d'énergie. Pour ces raisons, cette thèse propose de nouvelles techniques d'optimisation de la consommation d'énergie dans l'ordonnancement de systèmes multiprocesseur. La premiére contribution est un algorithme d'ordonnancement hiérarchique á deux niveaux qui autorise

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Mallangi, Siva Sai Reddy. "Low-Power Policies Based on DVFS for the MUSEIC v2 System-on-Chip." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-229443.

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Multi functional health monitoring wearable devices are quite prominent these days. Usually these devices are battery-operated and consequently are limited by their battery life (from few hours to a few weeks depending on the application). Of late, it was realized that these devices, which are currently being operated at fixed voltage and frequency, are capable of operating at multiple voltages and frequencies. By switching these voltages and frequencies to lower values based upon power requirements, these devices can achieve tremendous benefits in the form of energy savings. Dynamic Voltage a

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9

Akgul, Yeter. "Gestion de la consommation basée sur l’adaptation dynamique de la tension, fréquence et body bias sur les systèmes sur puce en technologie FD-SOI." Thesis, Montpellier 2, 2014. http://www.theses.fr/2014MON20132/document.

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Au-delà du nœud technologique CMOS BULK 28nm, certaines limites ont été atteintes dans l'amélioration des performances en raison notamment d'une consommation énergétique devenant trop importante. C'est une des raisons pour lesquelles de nouvelles technologies ont été développées, notamment celles basées sur Silicium sur Isolant (SOI). Par ailleurs, la généralisation des architectures complexes de type multi-cœurs, accentue le problème de gestion de la consommation à grain-fin. Les technologies CMOS FD-SOI offrent de nouvelles opportunités pour la gestion de la consommation en permettant d'ajus

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Zorello, Ligia Maria Moreira. "Dynamic CPU frequency scaling using machine learning for NFV applications." Universidade de São Paulo, 2018. http://www.teses.usp.br/teses/disponiveis/3/3141/tde-30012019-100044/.

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Growth in the Information and Communication Technology sector is increasing the need to improve the quality of service and energy efficiency, as this industry has already surpassed 12% of global energy consumption in 2017. Data centers correspond to a large part of this consumption, accounting for about 15% of energy expenditure on the Information and Communication Technology domain; moreover, the subsystem that generates the most costs for data center operators is that of servers and storage. Many solutions have been proposed to reduce server consumption, such as the use of dynamic voltage an

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11

Wang, Qiang. "Performance and power modeling of GPU systems with dynamic voltage and frequency scaling." HKBU Institutional Repository, 2020. https://repository.hkbu.edu.hk/etd_oa/814.

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To address the ever-increasing demand for computing capacities, more and more heterogeneous systems have been designed to use both general-purpose and special-purpose processors. The huge energy consumption of them raises new environmental concerns and challenges. Besides performance, energy efficiency is another key factor to be considered by system designers and consumers. In particular, contemporary graphics processing units (GPUs) support dynamic voltage and frequency scaling (DVFS) to balance computational performance and energy consumption. However, accurate and straightforward performan

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12

Michael, Michael Nasri. "Dynamic voltage and frequency scaling with multi-clock distribution systems on SPARC core /." Online version of thesis, 2009. http://hdl.handle.net/1850/10750.

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13

Aldhahri, Eiman Ali. "Dynamic Voltage and Frequency Scaling Enhanced Task Scheduling Technologies Toward Greener Cloud Computing." OpenSIUC, 2014. https://opensiuc.lib.siu.edu/theses/1382.

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The skyrocketing amount of electricity consumed by many data centers around the globe has become a serious issue for the cloud computing and entire IT industry. The demand for data centers is rapidly increasing due to widespread usage of cloud services. It also leads to huge carbon emissions contributing to the global greenhouse effect. The US Environmental Protection Agency has declared that data centers represent a substantial portion of the energy consumption in the US and the whole world. Some of this energy consumption is caused by idle servers or servers running at higher-than-necessar

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Benhani, El mehdi. "Sécurité des systèmes sur puce complexes hétérogènes." Thesis, Lyon, 2020. http://www.theses.fr/2020LYSES016.

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La thèse étudie la sécurité de la technologie ARM TrustZone dans le cadre des SoCs complexes hétérogènes. La thèse présente des attaques matérielles qui touchent des éléments de l’architecture des SoCs et elle présente aussi des stratégies de contremesure<br>The thesis studies the security of the ARM TrustZone technology in the context of complex heterogeneous SoCs. The thesis presents hardware attacks that affect elements of the SoCs architecture and it also presents countermeasure strategies

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Wang, Weihuang. "Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling." [College Station, Tex. : Texas A&M University, 2007. http://hdl.handle.net/1969.1/ETD-TAMU-2504.

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Datta, Srabosti. "POWER REDUCTION BY DYNAMICALLY VARYING SAMPLING RATE." UKnowledge, 2006. http://uknowledge.uky.edu/gradschool_theses/275.

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In modern digital audio applications, a continuous audio signal stream is sampled at a fixed sampling rate, which is always greater than twice the highest frequency of the input signal, to prevent aliasing. A more energy efficient approach is to dynamically change the sampling rate based on the input signal. In the dynamic sampling rate technique, fewer samples are processed when there is little frequency content in the samples. The perceived quality of the signal is unchanged in this technique. Processing fewer samples involves less computation work; therefore processor speed and voltage can

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Tapou, Monaf Sabri. "High efficiency smart voltage regulating module for green mobile computing." Thesis, Brunel University, 2014. http://bura.brunel.ac.uk/handle/2438/8285.

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In this thesis a design for a smart high efficiency voltage regulating module capable of supplying the core of modern microprocessors incorporating dynamic voltage and frequency scaling (DVS) capability is accomplished using a RISC based microcontroller to facilitate all the functions required to control, protect, and supply the core with the required variable operating voltage as set by the DVS management system. Normally voltage regulating modules provide maximum power efficiency at designed peak load, and the efficiency falls off as the load moves towards lesser values. A mathematical model

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Wamhoff, Jons-Tobias, Stephan Diestelhorst, Christof Fetzer, Patrick Marlier, Pascal Felber, and Dave Dice. "Selective Core Boosting: The Return of the Turbo Button." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2013. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-127748.

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Several modern multi-core architectures support the dynamic control of the CPU's clock rate, allowing processor cores to temporarily operate at speeds exceeding the operational base frequency. Conversely, cores can operate at a lower speed or be disabled altogether to save power. Such facilities are notably provided by Intel's Turbo Boost and AMD's Turbo CORE technologies. Frequency control is typically driven by the operating system which requests changes to the performance state of the processor based on the current load of the system. In this paper, we investigate the use of dynamic frequen

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Li, Bo. "Modeling and Runtime Systems for Coordinated Power-Performance Management." Diss., Virginia Tech, 2019. http://hdl.handle.net/10919/87064.

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Emergent systems in high-performance computing (HPC) expect maximal efficiency to achieve the goal of power budget under 20-40 megawatts for 1 exaflop set by the Department of Energy. To optimize efficiency, emergent systems provide multiple power-performance control techniques to throttle different system components and scale of concurrency. In this dissertation, we focus on three throttling techniques: CPU dynamic voltage and frequency scaling (DVFS), dynamic memory throttling (DMT), and dynamic concurrency throttling (DCT). We first conduct an empirical analysis of the performance and energ

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Fanfakh, Ahmed Badri Muslim. "Energy consumption optimization of parallel applications with Iterations using CPU frequency scaling." Thesis, Besançon, 2016. http://www.theses.fr/2016BESA2021/document.

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Au cours des dernières années, l'informatique “green” est devenue un sujet important dans le calcul intensif. Cependant, les plates-formes informatiques continuent de consommer de plus en plus d'énergie en raison de l'augmentation du nombre de noeuds qui les composent. Afin de minimiser les coûts d'exploitation de ces plates-formes de nombreuses techniques ont été étudiées, parmi celles-ci, il y a le changement de la fréquence dynamique des processeurs (DVFS en anglais). Il permet de réduire la consommation d'énergie d'un CPU, en abaissant sa fréquence. Cependant, cela augmente le temps d'exéc

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Zeng, Gang, Tetsuo Yokoyama, Hiroyuki Tomiyama, and Hiroaki Takada. "A Generalized Framework for Energy Savings in Real-Time Multiprocessor Systems." IEEE, 2008. http://hdl.handle.net/2237/12101.

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Schöne, Robert, Thomas Ilsche, Mario Bielert, Daniel Molka, and Daniel Hackenberg. "Software Controlled Clock Modulation for Energy Efficiency Optimization on Intel Processors." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-224966.

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Current Intel processors implement a variety of power saving features like frequency scaling and idle states. These mechanisms limit the power draw and thereby decrease the thermal dissipation of the processors. However, they also have an impact on the achievable performance. The various mechanisms significantly differ regarding the amount of power savings, the latency of mode changes, and the associated overhead. In this paper, we describe and closely examine the so-called software controlled clock modulation mechanism for different processor generations. We present results that imply that th

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Rathnala, Prasanthi. "Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation." Thesis, University of Derby, 2017. http://hdl.handle.net/10545/621716.

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Growing usage of smart and portable electronic devices demands embedded system designers to provide solutions with better performance and reduced power consumption. Due to the new development of IoT and embedded systems usage, not only power and performance of these devices but also security of them is becoming an important design constraint. In this work, a novel aggressive scaling based on timing speculation is proposed to overcome the drawbacks of traditional DVFS and provide security from power analysis attacks at the same time. Dynamic voltage and frequency scaling (DVFS) is proven to be

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Wamhoff, Jons-Tobias. "Exploiting Speculative and Asymmetric Execution on Multicore Architectures." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2015. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-163250.

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The design of microprocessors is undergoing radical changes that affect the performance and reliability of hardware and will have a high impact on software development. Future systems will depend on a deep collaboration between software and hardware to cope with the current and predicted system design challenges. Instead of higher frequencies, the number of processor cores per chip is growing. Eventually, processors will be composed of cores that run at different speeds or support specialized features to accelerate critical portions of an application. Performance improvements of software will

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Miftakhutdinov, Rustam Raisovich. "Performance prediction for dynamic voltage and frequency scaling." Thesis, 2014. http://hdl.handle.net/2152/26939.

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This dissertation proves the feasibility of accurate runtime prediction of processor performance under frequency scaling. The performance predictors developed in this dissertation allow processors capable of dynamic voltage and frequency scaling (DVFS) to improve their performance or energy efficiency by dynamically adapting chip or core voltages and frequencies to workload characteristics. The dissertation considers three processor configurations: the uniprocessor capable of chip-level DVFS, the private cache chip multiprocessor capable of per-core DVFS, and the shared cache chip multiprocess

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Arun, R. "Petri Net Model Based Energy Optimization Of Programs Using Dynamic Voltage And Frequency Scaling." Thesis, 2011. https://etd.iisc.ac.in/handle/2005/2013.

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High power dissipation and on-chip temperature limit performance and affect reliability in modern microprocessors. For servers and data centers, they determine the cooling cost, whereas for handheld and mobile systems, they limit the continuous usage of these systems. For mobile systems, energy consumption affects the battery life. It can not be ignored for desktop and server systems as well, as the contribution of energy continues to go up in organizations’ budgets, influencing strategic decisions, and its implications on the environment are getting appreciated. Intelligent trade-offs involvi

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Arun, R. "Petri Net Model Based Energy Optimization Of Programs Using Dynamic Voltage And Frequency Scaling." Thesis, 2011. http://etd.iisc.ernet.in/handle/2005/2013.

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High power dissipation and on-chip temperature limit performance and affect reliability in modern microprocessors. For servers and data centers, they determine the cooling cost, whereas for handheld and mobile systems, they limit the continuous usage of these systems. For mobile systems, energy consumption affects the battery life. It can not be ignored for desktop and server systems as well, as the contribution of energy continues to go up in organizations’ budgets, influencing strategic decisions, and its implications on the environment are getting appreciated. Intelligent trade-offs involvi

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Prabhu, Subodh. "Ocin_tsim - A DVFS Aware Simulator for NoC Design Space Exploration and Optimization." 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7798.

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Networks-on-Chip (NoCs) are a general purpose, scalable replacement for shared medium wired interconnects offering many practical applications in industry. Dynamic Voltage Frequency Scaling (DVFS) is a technique whereby a chip?s voltage-frequency levels are varied at run time, often used to conserve dynamic power. Various DVFSbased NoC optimization techniques have been proposed. However, due to the resources required to validate architectural decisions through prototyping, few are implemented. As a result, designers are faced with a lack of insight into potential power savings or performance g

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Govindan, Madhu Sarava. "E³ : energy-efficient EDGE architectures." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-08-1934.

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Increasing power dissipation is one of the most serious challenges facing designers in the microprocessor industry. Power dissipation, increasing wire delays, and increasing design complexity have forced industry to embrace multi-core architectures or chip multiprocessors (CMPs). While CMPs mitigate wire delays and design complexity, they do not directly address single-threaded performance. Additionally, programs must be parallelized, either manually or automatically, to fully exploit the performance of CMPs. Researchers have recently proposed an architecture called Explicit Data Graph Executi

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Σπηλιόπουλος, Βασίλειος. "Προσαρμογή συχνότητας και τάσης λειτουργίας για τη βελτιστοποίηση κατανάλωσης ενέργειας επεξεργαστών". Thesis, 2009. http://nemertes.lis.upatras.gr/jspui/handle/10889/2909.

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Η σύγχρονη αρχιτεκτονική στρέφεται σε λύσεις που έχουν ως στόχο την εξοικονόμηση ενέργειας, χωρίς όμως να επιβαρύνεται σε μεγάλο βαθμό η απόδοση του επεξεργαστή. Ιδιαίτερα οι υπερβαθμωτοί (superscalar) επεξεργαστές που επιτρέπουν εκτέλεση εκτός σειράς (out-of-order execution) διακρίνονται από υψηλή κατανάλωση ενέργειας, εξαιτίας των πολύπλοκων δομών που χρησιμοποιούν για την αύξηση της απόδοσης. Η δυναμική ρύθμιση τάσης – συχνότητας (DVFS) αποτελεί μία ευρέως χρησιμοποιούμενη τεχνική για την επίτευξη εξοικονόμησης ενέργειας. Μειώνοντας τη συχνότητα λειτουργίας ενός κυκλώματος, είναι δυνατόν ν

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"Enabling dynamic voltage and frequency scaling in multicore architectures." UNIVERSITY OF COLORADO AT BOULDER, 2010. http://pqdtopen.proquest.com/#viewpdf?dispub=1473683.

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Hsu, An-Jia, and 許安嘉. "iVisual: An Intelligent Vision Processor With Dynamic Voltage and Frequency Scaling." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/65444071204522740913.

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碩士<br>臺灣大學<br>電子工程學研究所<br>98<br>An high frame rate vision processor with Dynamic voltage and frequency scaling is presented in this thesis. The peak performance of this processor is 240 GOPS which consumes 185 mW at 156 MHz. The chip is implemented on a 3.95mmx3.95mm die in a UMC 90nm Logic&Mixed-Mode 1P9M Low-K Process. In recent years, applications of intelligent vision processor can be seen everywhere. Systems applying intelligent vision processors can work 24 hours a day and 7 days a week, waiting for the signals of interest and response immediately once some situation happens. This na

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Chen, Ya Ting, and 陳雅婷. "A Bus Circuit Design with Dynamic Voltage/Frequency Scaling and Repeater Insertion." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/99647596644232328251.

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碩士<br>國立交通大學<br>電機與控制工程系所<br>97<br>This thesis proposes a bus circuit using repeater insertion to reduce its power consumption and area. Moreover, we use a timing measurement circuit to estimate eye opening and jitter. According to the eye opening, we can determine if the supply voltage or the frequency is adequate for the task. If the supply voltage or the frequency disagrees with the task, we can dynamically change the supply voltage or the frequency to make the signal correctly transferred. For the data generation, a pseudorandom binary sequence generator has been used to generate eigh

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Hsu, Chun-Po, and 許竣博. "A CPU Utilization-oriented Memory-aware Dynamic Voltage and Frequency Scaling Algorithm." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/ktd9y6.

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碩士<br>國立臺北科技大學<br>資訊工程系研究所<br>99<br>Saving energy is an important target for portable devices which are powered by batteries. Among low power mechanisms, DVFS is an efficient method which can reduce energy consumption while tasks are running. In our previous studies, we found a relationship between the memory access rate and the frequency which minimizes the energy consumption. We have proposed an equation named MAR-CSE which represents this relationship and is used to perform dynamic frequency selection. However, the MAR-CSE equation cannot handle all the cases. It may cause the energy consum

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Tang, Yi Lun, and 唐翊倫. "A Cache-Utilization Based Dynamic Voltage Frequency Scaling Mechanism for Reliability Enhancements." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/05665302847329800767.

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碩士<br>國立清華大學<br>資訊工程學系<br>104<br>Dynamic Voltage-Frequency Scaling (DVFS) has been proposed for a good balance between power and performance in processor design. Various DVFS methods are now applied to modern processor designs. These techniques sometimes make processors and cache operate at lower supplying voltage for energy saving. But the scaled-down supplying voltage greatly decreases the reliability of cache at the same time. To address this issue, we propose a cache-utilization based DVFS mechanism utilizing 7T/14T cache architecture [1] for reliability enhancements. In our method, under

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Chen, Shih-Chang, and 陳世昌. "Energy Aware Dual-Speed Dynamic Voltage and Frequency Scaling on Portable Devices." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/rva5me.

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碩士<br>國立臺北科技大學<br>資訊工程系研究所<br>96<br>In recent years, the use of mobile devices has become highly integrated into people’s daily lives. The study of power consumption has become an important system design issue on portable devices. Many mobile systems such as PDAs, smart phones, and laptops have currently supported dynamic voltage and frequency scaling (DVFS) during the system operating, and DVFS is considered as one of most efficient techniques to decrease energy consumption. This paper demonstrates an adaptive hardware and software systems architecture on mobile devices. We modify software po

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陳則翔, Tse-Hsiang Chen, and 陳則翔. "Design and Implementation of an EDP-based Dynamic Voltage and Frequency Scaling Mechanism." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/y97n82.

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碩士<br>國立臺北科技大學<br>資訊工程系研究所<br>100<br>Energy saving is an important issue, especially for the handheld devices. The dynamic voltage and frequency scaling (DVFS) is one of the mechanisms in the energy saving research area. DVFS can be used to reduce energy consumption of a processor while tasks are running. However, reducing the frequency for a processor might not induce minimized energy consumption, since the execution time will be extended due to the frequency being decreased and the program will consume extra energy during this extended period. As a result, the induced extra energy could be h

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Chen, Yusheng, and 陳裕生. "Design and Implementation of Dynamic Voltage and Frequency Scaling for Embedded Java Virtual Machine." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/whh657.

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碩士<br>國立交通大學<br>資訊工程系所<br>94<br>Dynamic voltage and frequency Scaling (DVFS) is recognized as one of the most effective power reduction techniques. JAVA is getting popular in mobile embedded systems in recent year. Thus we propose a low-power research platform on an embedded JVM and implement DVFS on it. We refer to an accurate DVFS algorithm which calculates proper frequency of a program according to the ratio of on-chip computation time to off-chip access time. Proposed methodology for estimating the ratio of on-chip computation time to off-chip access time can be applied on defacement platf

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Wang, Chi Tsung, and 王啟宗. "On the Design of Battery-aware Dynamic Voltage and Frequency Scaling for Sensor Node." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/11702203168721062445.

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碩士<br>輔仁大學<br>資訊工程學系<br>100<br>Sensors are often distributed in rather adverse and even dangerous environments in wireless sensor network (WSN). It is difficult to change batteries of sensor nodes manually. Therefore, maximizing the battery life and effective power consumption have become hot research fields of WSN. Generally speaking, sensors in active mode are idle most of the time. Since most available sensors are operating on a single frequency, which indicating that same CPU frequency is used whether in working or in idle mode. It will result in unnecessary waste of energy if CPU were ope

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Su, Wei-Siang, and 蘇煒翔. "A 0.5V/1.0V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/87345556199303855073.

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碩士<br>國立中正大學<br>資訊工程研究所<br>101<br>In recent years, biomedical electronic applications, such as biological signal monitoring devices, implantable medical devices, and wireless body sensors become more and more popular now. In these battery-powered systems, low energy is a primary concern to increase the system operating time. Therefore, power management is an important issue for designing these devices. Dynamic voltage and frequency scaling (DVFS) serves an effective means to reduce the dynamic power consumption of the system. Moreover, the duty-cycle control of the power switch can further red

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Trescases, Olivier. "A high-frequency, soft-switching DC-DC converter for dynamic voltage scaling in VLSI loads." 2004. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=95046&T=F.

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Chang, Ming-Feng, and 張銘峰. "Design of Dynamic Voltage and Frequency Scaling Algorithms for Energy Efficiency Applications on Embedded System." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/ek8a9z.

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博士<br>國立臺北科技大學<br>資訊工程系研究所<br>104<br>Energy efficiency becomes a critical consideration in computer engineering due to the rise of mobile, battery-powered devices. Nowadays, the modern hardware provides many features for reducing power and energy that require effective software control. Dynamic voltage and frequency scaling (DVFS) is a well-known and efficient technique for reducing power. The central idea of DVFS technique on general-purpose applications is to supply a minimal voltage and frequency when the CPU is in the idle mode. This dissertation proposes different types of DVFS approaches

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Tsung-YuHsieh and 謝宗諭. "An Effective Dynamic Thermal Management Using Proactive Task Scheduler with Dynamic Voltage and Frequency Scaling for Three Dimensional Multi-Processor Systems." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/uzwzf7.

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Mochocki, Bren Christopher. "The impact of dynamic voltage and frequency scaling on the energy consumption, schedulability and predictability of real-time embedded systems." 2006. http://etd.nd.edu/ETD-db/theses/available/etd-12052006-163806/.

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Thesis (Ph. D.)--University of Notre Dame, 2006.<br>Thesis directed by Xiaobo (Sharon) Hu for the Department of Computer Science and Engineering. "December 2006." Includes bibliographical references (leaves 174-183).

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"System Level Power and Thermal Management on Embedded Processors." Doctoral diss., 2012. http://hdl.handle.net/2286/R.I.14683.

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abstract: Semiconductor scaling technology has led to a sharp growth in transistor counts. This has resulted in an exponential increase on both power dissipation and heat flux (or power density) in modern microprocessors. These microprocessors are integrated as the major components in many modern embedded devices, which offer richer features and attain higher performance than ever before. Therefore, power and thermal management have become the significant design considerations for modern embedded devices. Dynamic voltage/frequency scaling (DVFS) and dynamic power management (DPM) are two well-

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Wamhoff, Jons-Tobias. "Exploiting Speculative and Asymmetric Execution on Multicore Architectures." Doctoral thesis, 2014. https://tud.qucosa.de/id/qucosa%3A28598.

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The design of microprocessors is undergoing radical changes that affect the performance and reliability of hardware and will have a high impact on software development. Future systems will depend on a deep collaboration between software and hardware to cope with the current and predicted system design challenges. Instead of higher frequencies, the number of processor cores per chip is growing. Eventually, processors will be composed of cores that run at different speeds or support specialized features to accelerate critical portions of an application. Performance improvements of software will

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