Academic literature on the topic 'Early/Late Gate Synchronizer (ELGS)'

Les circuits de récupération d'horloge et de données sont nécessaires au bon fonctionnement de plusieurs systèmes de communication sans fil. Les travaux effectués dans le cadre de cette thèse concernent le développement de ces circuits avec d'une part la réalisation, en technologie HCMOS9 0,13 μm de STMICROELECTRONICS, de circuits CDR analogiques à 1 et 54 Mbit/s, et d'autre part, la mise en œuvre de fonctions CDR numériques programmables à bas débit. Un circuit CDR fonctionnant à plus bas débit (1 Mbit/s) a été conçu dans le cadre de la gestion d'énergie d'un récepteur ULB impulsionnel non cohérent. Ces deux structures ont été réalisées à l'aide de PLL analogiques du 3ème ordre. Un comparateur de phase adapté aux impulsions issues du détecteur d'énergie a été proposé dans cette étude. Les circuits ont ensuite été dimensionnés dans le but d'obtenir de très bonnes performances en termes de jitter et de consommation. En particulier, les performances mesurées (sous pointes) du circuit CDR à 1 Mbit/s permettent d'envisager une gestion d'énergie efficace (réduction de plus de 97% de la consommation du récepteur). Dans le cadre d'une chaîne de télémesure avion vers sol, deux circuits CDR numériques ont également été réalisés durant cette thèse. Une PLL numérique du second degré a été implémentée en vue de fournir des données et une horloge synchrone de celles-ci afin de piloter une chaîne SOQPSK entièrement numérique. Un circuit ELGS a également mis au point pour fonctionner au sein d'un récepteur PCM/FM
Clock and data recovery circuits are required in many wireless communication systems. This thesis is about development of such circuits with: firstly, the realization, in HCMOS9 0.13 μm of STMICROELECTRONICS technology, of 1 and 54 Mb/s analog CDR circuits, and secondly, the implementation of programmable digital circuits at low rates. In the aim of an impulse UWB transceiver dealing with video transmission, a CDR circuit at 54 Mb/s rate has been realized to provide clock signal synchronously with narrow pulses (their duration is about a few nanoseconds) from the energy detector. Another CDR circuit has been built at 1 Mb/s rate in a non-coherent IR- UWB receiver power management context. Both circuits have been implemented as 3rd order analog PLL. In this work, a phase comparator suitable for “RZ low duty cycle” data from the energy detector has been proposed. Circuits have been sized to obtain very good performances in terms of jitter and power consumption. Particularly, measured performances of the 1 Mb/s CDR circuit allow to plan an efficient power management (a decrease of more than 97% of the receiver total power consumption). In the context of a telemetry system from aircraft to ground, two digital CDR circuits have also been implemented. A second order digital PLL has been adopted in order to provide synchronous clock and data to an SOQPSK digital transmitter. Also, a digital ELGS circuit has been proposed to work in a PCM/FM receiver. For both CDR structures, the input signal rate is programmable and varies globally from 1 to 30 Mb/s

碩士
國立中正大學
電機工程學系
84
ABSTRACT Timing is the important operation. It distinguishes a digital communication system from an analog system. Before a receiver can even begin to decide which of the various symbols it is receiving ,it must establish symbol timing. That is, everyone of the digital receivers need to have their demodulators synchronized to the incoming digital symbol transitions in order to achieve optimum demodulation. Personal Communication Service ( PCS ) is a new mode of telephone communication in which the phone subscriber is assigned a phone number which he carriers with his person and he can dial from this number from wherever travels to just as if he were calling from home. A full-fledged PCS will probably not be in operation for another ten years hence, but an area-restricted version of it is at user-testing stage in various parts of the world and will be deployed within the next few years. We studied the demodulator design to a set specification code-named PACS ( Personal Access Communication Service ) proposed by Bellcore in the United States. But Bellcore has proposed a method of implementing the PACS demodulator which has been patented. There are two key elements in the design of a demodulator, they are symbol epoch synchronization and offset frequency synchronization. We investigate an alternative method of implementation which will perform as well as the Bellcore method. In this thesis, we present the algorithm for the process needed for the acquisition and tracking of timing. There are several methods available for symbol synchronization. We discuss a method of symbol epoch synchronization which is based on a modified Early-Late Gate type of estimating time error for a signal with raised-cosine shaping with a rolloff factor of 0.5. We simulate this early-late gate algorithm by FORTRAN 77.