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Relevant bibliographies by topics / EDVAC

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Academic literature on the topic 'EDVAC'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 February 2022

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Journal articles on the topic "EDVAC"

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Wang, Daniel C. "From the EDVAC to WEBVACs." Queue 13, no. 4 (April 2015): 10–28. http://dx.doi.org/10.1145/2756506.2756508.

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Wang, Daniel C. "From the EDVAC to WEBVACs." Communications of the ACM 58, no. 8 (July 23, 2015): 44–51. http://dx.doi.org/10.1145/2714079.

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Reitwiesner, G. W. "The first operating system for the EDVAC." IEEE Annals of the History of Computing 19, no. 1 (1997): 55–59. http://dx.doi.org/10.1109/85.560738.

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Williams, M. R. "The origins, uses, and fate of the EDVAC." IEEE Annals of the History of Computing 15, no. 1 (1993): 22–38. http://dx.doi.org/10.1109/85.194089.

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von Neumann, J. "First draft of a report on the EDVAC." IEEE Annals of the History of Computing 15, no. 4 (1993): 27–75. http://dx.doi.org/10.1109/85.238389.

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Miranda, Pablo. "Computer utterances: Sequence and event in digital architecture." International Journal of Architectural Computing 15, no. 4 (October 13, 2017): 268–84. http://dx.doi.org/10.1177/1478077117734661.

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Barely a month before the end of World War II, a technical report begun circulating among allied scientists: the ‘First Draft of a Report on the EDVAC’, attributed to John von Neumann, described for the first time the design and implementation of the earliest stored-program computer. The ‘First Draft’ became the template followed by subsequent British and American computers, establishing the standard characteristics of most computing machines to date. This article looks at how the material and design choices described in this report influenced architecture, as it set up the technological matrix onto which a discipline relying on a tradition of drawn geometry would be eventually completely remediated. It consists of two parts: first, a theoretical section, analysing the repercussions for architecture of the type of computer laid out in the ‘First Draft’. Second, a description of a design experiment, a sort of information furniture, that tests and exemplifies some of the observations from the first section. This experiment examines the possibilities of an architecture that, moving beyond geometric representations, uses instead the programming of events as its rationale. The structure of this article reflects a methodology in which theoretical formulation and design experiments proceed in parallel. The theoretical investigation proposes concepts that can be tested and refined through design and conversely design work determines and encourages technical, critical and historical research. This relation is dialogical: theoretical investigation is not simply a rationalisation and explanation of earlier design work; inversely, the role of design is not just to illustrate previously formulated concepts. Both design and theorisation are interdependent but autonomous in their parallel development.

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Lee, J. H. M., and K. L. Leung. "Consistency Techniques for Flow-Based Projection-Safe Global Cost Functions in Weighted Constraint Satisfaction." Journal of Artificial Intelligence Research 43 (February 28, 2012): 257–92. http://dx.doi.org/10.1613/jair.3476.

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Many combinatorial problems deal with preferences and violations, the goal of which is to find solutions with the minimum cost. Weighted constraint satisfaction is a framework for modeling such problems, which consists of a set of cost functions to measure the degree of violation or preferences of different combinations of variable assignments. Typical solution methods for weighted constraint satisfaction problems (WCSPs) are based on branch-and-bound search, which are made practical through the use of powerful consistency techniques such as AC*, FDAC*, EDAC* to deduce hidden cost information and value pruning during search. These techniques, however, are designed to be efficient only on binary and ternary cost functions which are represented in table form. In tackling many real-life problems, high arity (or global) cost functions are required. We investigate efficient representation scheme and algorithms to bring the benefits of the consistency techniques to also high arity cost functions, which are often derived from hard global constraints from classical constraint satisfaction. The literature suggests some global cost functions can be represented as flow networks, and the minimum cost flow algorithm can be used to compute the minimum costs of such networks in polynomial time. We show that naive adoption of this flow-based algorithmic method for global cost functions can result in a stronger form of null-inverse consistency. We further show how the method can be modified to handle cost projections and extensions to maintain generalized versions of AC* and FDAC* for cost functions with more than two variables. Similar generalization for the stronger EDAC* is less straightforward. We reveal the oscillation problem when enforcing EDAC* on cost functions sharing more than one variable. To avoid oscillation, we propose a weak version of EDAC* and generalize it to weak EDGAC* for non-binary cost functions. Using various benchmarks involving the soft variants of hard global constraints ALLDIFFERENT, GCC, SAME, and REGULAR, empirical results demonstrate that our proposal gives improvements of up to an order of magnitude when compared with the traditional constraint optimization approach, both in terms of time and pruning.

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Wilkes, M. V. "EDSAC 2." IEEE Annals of the History of Computing 14, no. 4 (1992): 49–56. http://dx.doi.org/10.1109/85.194055.

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Fielding, David I., Justin Travers, Phan Nguyen, Michael G. Brown, Gunter Hartel, and Stephen Morrison. "Expiratory reactance abnormalities in patients with expiratory dynamic airway collapse: a new application of impulse oscillometry." ERJ Open Research 4, no. 4 (October 2018): 00080–2018. http://dx.doi.org/10.1183/23120541.00080-2018.

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Expiratory dynamic airways collapse (EDAC) is a condition that affects the central airways; it is not well characterised physiologically, with relatively few studies. We sought to characterise impulse oscillometry (IOS) features of EDAC in patients with normal spirometry. Expiratory data were hypothesised to be the most revealing. In addition, we compared IOS findings in chronic obstructive pulmonary disease (COPD) patients with and without EDAC.EDAC was identified at bronchoscopy as 75–100% expiratory closure at the carina or bilateral main bronchi. Four patient groups were compared: controls with no EDAC and normal lung function; lone EDAC with normal lung function; COPD-only patients; and COPD patients with EDAC.38 patients were studied. Mean IOS data z-scores for EDAC compared to controls showed significantly higher reactance (X) values including X at 5 Hz, resonance frequency and area under the reactance curve (AX). EDAC showed significantly greater expiratory/inspiratory differences in all IOS data compared to controls. Stepwise logistic regression showed that resonant frequency best discriminated between EDAC and normal control, whereas classification and regression tree analysis found AX ≥3.523 to be highly predictive for EDAC in cases with normal lung function (14 out of 15 cases, and none out of eight controls).These data show a new utility of IOS: detecting EDAC in patients with normal lung function.

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Parkes, Hugh. "EDPAC '95: New Horizons." Computer Audit Update 1995, no. 7 (July 1995): 14–17. http://dx.doi.org/10.1016/s0960-2593(00)80045-2.

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Dissertations / Theses on the topic "EDVAC"

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Bulfone, Lorenzo. "Von Neumann: non solo architetto." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2014. http://amslaurea.unibo.it/7909/.

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Álvarez, Peña Roberto Ignacio. "Evaluación de la Implementación de EDAC por Señal Específica como Complemento al Criterio N-1." Tesis, Universidad de Chile, 2011. http://www.repositorio.uchile.cl/handle/2250/104043.

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No autorizado por el autor para ser publicada a texto completo
Los esquemas de desconexión automáticos de carga (EDAC) por señal específica se definen como recursos generales o especiales de control de contingencias, que operan al detectar un cambio de estado predefinido en el Sistema Interconectado (SI). Estos automatismos se definen en la Norma Técnica de Seguridad y Calidad de Servicio (NT) y son de gran importancia para preservar la seguridad del SI. El presente trabajo busca contribuir en el desarrollo de estos esquemas, evaluando distintas aplicaciones en un modelo reducido del Sistema Interconectado Central (SIC). Adicionalmente, se propone una metodología para valorizar el Servicio Complementario que se provee al sistema. En esta memoria se consideran cuatro casos: EDAC por colapso de tensión, por límite térmico, por salida en cascada y por colapso en isla. Se simulan contingencias simples en todos los elementos donde son aplicables, y a partir de los estándares de recuperación dinámica, definidos en la NT, se procede a determinar los puntos críticos del modelo reducido del SIC, a los cuales se aplica una evaluación técnico-económica para determinar la conveniencia de implementar un EDAC por señal específica. Desde el punto de vista económico, se busca establecer si la operación del SI con uno de estos esquemas minimiza los costos de operar la red con un criterio N-1, el cual se refiere a una metodología de planificación y operación del SI, donde la ocurrencia de una contingencia simple no afecta a las restantes instalaciones del mismo. Los resultados obtenidos muestran que los EDAC por señal específica son un complemento válido al criterio N-1, ya que permiten utilizar el sistema de transmisión por sobre la limitación técnica establecida, lo que hace posible aumentar las transferencias hasta las cercanías del límite por colapso de tensión o el límite térmico. Por otro lado, estos automatismos permiten operar líneas de transmisión con elevados niveles de carga en sectores caracterizados por tener una topología enmallada, ya que evitan una salida en cascada al presentarse una contingencia simple en este lugar del SIC. Por consiguiente, centrales ubicadas en lugares remotos, y con menores costos variables, pueden aumentar sus inyecciones al SI, disminuyendo el costo de operación sistémico, con lo cual el Centro de Despacho Económico de Carga (CDEC) cumple con el mandato legal de operar el sistema con una confiabilidad prefijada y a mínimo costo. Finalmente se evalúa numéricamente la propuesta de valorización para los distintos escenarios desarrollados. Se consideran las siguientes componentes de la valorización: la anualidad por inversión, el costo de falla, el valor de restablecer los consumos desconectados, reducción en las pérdidas del sistema y los costos de operación y mantenimiento. Se concluye que el valor del Servicio Complementario está fuertemente influenciado por la topología del sector, ya que las componentes fundamentales son la anualidad por inversión, costo de falla y valor de la energía no suministrada luego de que el sistema restablece el máximo de clientes posibles. Como trabajo futuro, se propone la implementación de múltiples escenarios utilizando el método de Monte Carlo, con lo cual se puede realizar una valorización más precisa de los EDAC por señal específica.

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Oechsel, Craig R. "Implementation of error detection and correction (EDAC) in the Static Random Access Memory (SRAM) aboard Petite Amateur Navy Satellite (PANSAT)." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1995. http://handle.dtic.mil/100.2/ADA297723.

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Sepúlveda, Martínez Francisco Javier. "Aumento de la capacidad de transmisión del sistema de transmisión troncal del SIC a través de un sistema EDAG y EDAC." Tesis, Universidad de Chile, 2013. http://www.repositorio.uchile.cl/handle/2250/114721.

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Ingeniero Civil Electricista
En el marco de los altos precios de la energía eléctrica en Chile, en particular en el Sistema Interconectado Central (SIC), realizar un estudio sobre las capacidades máximas de transmisión resulta de vital importancia para poder descongestionar las líneas de transporte de energía eléctrica, haciendo la operación del sistema eléctrico más económica. Dado que el CDEC SIC tiene como obligación operar el sistema eléctrico a mínimo costo, la Dirección de Operaciones (DO) tiene la facultad de aumentar la capacidad de transmisión a través de esquemas de desconexión automático de carga (EDAC) y de generación (EDAG) haciendo uso de la capacidad de sobrecarga de los elementos serie del sistema de transmisión, cuando las líneas ya se encuentran operativas. Esta memoria de título se centra en el aumento de capacidad del sistema de transmisión troncal del SIC con esquemas de desconexión automático de carga (EDAC) y de generación (EDAG). Primero se hace un análisis del estado actual del sistema de transmisión troncal para encontrar las líneas que presentan congestión. Luego se procede a justificar económicamente que la solución con sistemas EDAG/EDAC es la adecuada. Se comprueba que los niveles de seguridad, usando dichos sistemas, se mantienen considerando cuatro escenarios que consisten en distintos niveles de transferencia de energía eléctrica proveniente del sur de subestación Charrúa (octava región) hacia el centro de consumo. Para cada escenario el sistema se somete a dos contingencias ocurridas en la línea de doble circuito Charrúa Ancoa 500 [kV] (línea que manifiesta congestión) que consisten en la desconexión intempestiva de uno de los circuitos y en un cortocircuito bifásico a tierra sin impedancia de falla ocurrida en la mitad de uno de los circuitos. La modelación de estas dos contingencias para los cuatro escenarios se realiza en DigSilent. Los resultados que se obtienen permiten concluir que sí es posible aumentar la capacidad de transmisión de la línea Charrúa Ancoa 500 [kV] sin comprometer la seguridad del sistema ante la ocurrencia de las contingencias descritas anteriormente. Sin embargo los márgenes admitidos en la Norma Técnica para la tensión en barras de 500 [kV] se ven violados y además presentan oscilaciones (estas últimas pueden ser superadas sintonizando los P.S.S. del sistema eléctrico) en el último escenario, cuando la línea está más sobrecargada. Luego, un aumento en la capacidad de transmisión con esquemas EDAG/EDAC es posible, pero se debe realizar en conjunto con una adecuada sintonización de los P.S.S. del sistema eléctrico.

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Ellis, Robert H. "Long haul communications in the HF spectrum utilizing high speed modems." Thesis, Monterey, California. Naval Postgraduate School, 1988. http://hdl.handle.net/10945/23289.

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Approved for public release; distribution is unlimited
In the past ten years reliable high-speed satellite systems have pushed slower less reliable communication systems to the bottom of the list for development programs. Concern over reduced budgets, vulnerability of expensive satellite systems, and recent advances in HF technology are creating new interest in upgrading existing HF communication systems. Nondevelopment Items (NDI) are defined as the use of off-the-shelf commercial items instead of costly, time-consuming conventional research and development programs. The Navy Department's current policies are designed to insure the maximum use of NDI to fulfill Navy requirements. The speed of HF systems can be improved using current signaling and modulation techniques, and reliability can be increased by error-correcting codes or error detection used in conjunction with automatic repeat request (ARQ) schemes. Improved HF systems not only provide survivable back-up capability, but increased capacity for present communication needs.
http://archive.org/details/longhaulcommunic00elli
Lieutenant, United States Navy

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Tapfuh, Mouafo Joseph. "Etude d'amplificateurs faible niveau à haute linéarité en technologies intégrées HEMT AsGa pour applications spatiales." Limoges, 2008. https://aurore.unilim.fr/theses/nxfile/default/82c545c3-edac-49d5-a891-3f4fbc7ceba0/blobholder:0/2008LIMO4056.pdf.

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Dans ce mémoire, nous examinons en détail les différentes méthodes d'évaluation de la linéarité dans les amplificateurs. Une analyse mathématique par séries de Volterra, basée sur le schéma équivalent d'un transistor HEMT nous a permis de dégager les différents paramètres qui influencent la linéarité d'un amplificateur faible niveau, notamment, son point de polarisation et ses impédances de charge. Ainsi, l'optimisation de la linéarité ne passe plus par l'optimisation du P1dB comme dans le cas des amplificateurs de puissance, mais sur l'optimisation de la charge des transistors du dernier étage à partir des données issues d'une mesure load-pull bi-porteuse visant à maximiser directement le C/I3 pour une puissance de fonctionnement nominale. Cette approche permet de palier à l'absence de modèle non-linéaire fiable pour prédire l'intermodulation à bas niveau de puissance de fonctionnement et d'optimiser la linéarité à partir d'une simple simulation linéaire robuste, fiable et rapide
This work presents an analysis of low-level and high linearity amplifier circuits, and proposes solutions in order to optimise the ratio between high linearity and low consumption (IP3/Pdc). Different methods to evaluate linearity in amplifier has been studied. Mathematical analysis with Volterra series based on equivalent circuit of HEMT transistor allows us to highlight different parameters influencing linearity in low amplifier, in particular, bias point and load impedances. Hence, linearity optimisation does not involve optimisation of output power at 1 dB gain compression, as for high power amplifier, but optimisation of load of transistor for the last stage, using data from 2 tones load-pull measurement, in order to maximise the C/I3 ratio for a given output power. This approach allow us to bypass the lack of reliable non-linear model of transistor for an accurate IM3 prediction, and help to optimise the linearity using a simple, fast and robust linear simulation

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Huang, Yi-Wei, and 黃奕維. "A Parity Check Matrix Generator for Low Power Memory with EDAC." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/46038539563532695234.

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碩士
國立清華大學
電機工程學系
96
With the feature size of semiconductor technology continues to reduce, how to keep a high level of reliability for memory products has become an important issue. Specifically, Error Detection and Correction (EDAC) techniques are commonly used in this scheme. It protects against soft errors and thereby enhances system reliability and data integrity. However, the conventional EDAC techniques would not be satisfied with memories with long codewords. Moreover, power reduction in memories like cells can be always done by keeping refreshing the frequency, but the data integrity should be considered with carefully. On account of the above issues, we propose an EDAC scheme for designing the parity check matrices which can be used on memories with different sizes of long codewords. The parity check matrix generator proposed in the paper can apply memories to reduce refreshing power consumption in single-error correcting, double error-detecting codes (SEC-DED). Power is minimized with little or no impact on area and delay, using degree freedom in selecting the parity check matrix of the error correcting code. It presents codes that use a smaller number of circuits and requires a shorter gate delay time than known codes. The overall construction methods are useful for systematic constructing the parity check matrices.

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Books on the topic "EDVAC"

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... edva i︠a︡ zadŭrzham: Poezii︠a︡. Sofii︠a︡: Stigmati, 2008.

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Bin yılın mirası: Makamı var eden döngü : Edvar geleneği. Beşiktaş, İstanbul: Pan Yayıncılık, 2012.

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Chubakha, Igorʹ. Taĭna Chernogo mori͡a︡: Semʹ dneĭ, kotorye edva ne potri͡a︡sli mir. 3rd ed. Sankt-Peterburg: Neva, 2002.

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European Design and Test Conference (1994 Paris, France). The European Design and Test Conference: Proceedings : EDAC, The European Conference on Design Automation : ETC, European Test Conference : EUROASIC, The European Event in ASIC Design : February 28-March 3, 1994, Paris, France. Los Alamitos, Calif: IEEE Computer Society Press, 1994.

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5

Anderson, James A. The Brain Works by Logic. Oxford University Press, 2018. http://dx.doi.org/10.1093/acprof:oso/9780199357789.003.0007.

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Brains and computers were twins separated at birth. In 1943, it was known that action potentials were all or none, approximating TRUE or FALSE. In that year, Walter Pitts and Warren McCulloch wrote a paper suggesting that neurons were computing logic functions and that networks of such neurons could compute any finite logic function. This was a bold and exciting large-scale theory of brain function. Around the same time, the first digital computer, the ENIAC, was being built. The McCulloch-Pitts work was well known to the scientists building ENIAC. The connection between them appeared explicitly in a report by John von Neumann on the successor to the ENIAC, the EDVAC. It soon became clear that biological brain computation was not based on logic functions. However, this idea was believed by many scientists for decades. A brilliant wrong theory can sometimes cause trouble.

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Accenti, Eva, and Ettore Accenti. Computer : 6. 000 Anni: COLOR - Abaco, Astrolabio, Pascalina, Eniac, Motore Analitico, Comtometer, Tabulatrici, Enigma, Z3, Colossus, Model 3, Eniac, Mark 1, Edvac, PDP8, Cray 1, IBM360, PC, D-Wave. Independently Published, 2020.

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Accenti, Eva, and Ettore Accenti. Computer : 6. 000 Anni: B/N - Abaco, Astrolabio, Pascalina, Eniac, Motore Analitico, Comtometer, Tabulatrici, Enigma, Z3, Colossus, Model 3, Eniac, Mark 1, Edvac, PDP8, Cray 1, IBM360, PC, D-Wave. Independently Published, 2020.

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Erhardt, Rhoda Priest. Erhardt developmental vision assessment (EDVA). Communication Skill Builders, 1989.

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Erhardt, Rhoda P. Erhardt Developmental Visual Assessment (EDVA). Psychological Corp, 1989.

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European Conf. on Design Automation. European Conference on Design Automation (Edac 91). Ieee Computer Society, 1991.

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Book chapters on the topic "EDVAC"

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Priestley, Mark. "EDVAC and Its Codes." In SpringerBriefs in History of Computing, 21–37. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-91671-2_3.

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O’Regan, Gerard. "EDVAC and ENIAC Computers." In The Innovation in Computing Companion, 113–17. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-02619-6_23.

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Herbert, Andrew, and David Hartley. "EDSAC Replica Project." In Making the History of Computing Relevant, 297–308. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-41650-7_27.

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Raab, Horst H. "Wirtschaftlichkeitsvergleich mittels EDVA." In Handbuch Industrieroboter, 262–86. Wiesbaden: Vieweg+Teubner Verlag, 1986. http://dx.doi.org/10.1007/978-3-322-83600-7_7.

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Caliskan, Tayfun, Gaurav Kumar, and Septimiu Murgu. "Tracheobronchomalacia (TBM) and Excessive Dynamic Airway Collapse (EDAC)." In Advances in Interventional Pulmonology, 142–75. UAE: Bentham Science Publishers Ltd., 2017. http://dx.doi.org/10.2174/9781681085913117010012.

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Yasiran, S. S., A. Ibrahim, W. E. Z. W. A. Rahman, and R. Mahmud. "Efficiency of Enhanced Distance Active Contour (EDAC) for Microcalcifications Segmentation." In IFMBE Proceedings, 650–54. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-21729-6_159.

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Colodro-Conde, Carlos, and Rafael Toledo-Moreo. "Improving the Implementation of EDAC Functions in Radiation-Hardened FPGAs." In FPGAs and Parallel Architectures for Aerospace Applications, 189–200. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-14352-1_13.

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Campbell-Kelly, Martin. "The Evolution of Digital Computing Practice on the Cambridge University EDSAC, 1949–1951." In History of Computing, 117–34. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-02152-8_7.

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"EDVAC and the First Draft." In ENIAC in Action. The MIT Press, 2016. http://dx.doi.org/10.7551/mitpress/10131.003.0010.

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Haigh, Thomas, Mark Priestley, and Crispin Rope. "EDVAC and the First Draft." In Eniac in Action. The MIT Press, 2016. http://dx.doi.org/10.7551/mitpress/9780262033985.003.0007.

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This chapter charts the rapid evolution of thinking about programming and computer architecture among members of the ENIAC team from 1944 onward, as what is usually called the “stored program concept” was formulated with John von Neumann and presented in the “First Draft of a Report on the EDVAC.” Use of archival sources makes this more specific and rigorous in documenting this process than any previous published account, presenting the new approach as an evolution of, and response to, the original ENIAC programming method. The ideas present in the “First Draft” are clearly explained and separated into three distinct clusters: the “EDVAC hardware paradigm,” the “von Neumann architecture paradigm,” and the “modern code paradigm.” The chapter finishes with an exploration of initial understanding and reception of these ideas, reconstructing the late-1940s consensus on what was important about the new approach and why.

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Conference papers on the topic "EDVAC"

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Wilkes, Maurice V. "Arithmetic on the EDSAC." In the 1996 ACM 24th annual conference. New York, New York, USA: ACM Press, 1996. http://dx.doi.org/10.1145/228329.228343.

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Eason, Ernest D., Edward E. Nelson, and Graham B. Heys. "Fatigue Crack Growth Rate of Medium and Low Sulfur Ferritic Steels in Pressurized Water Reactor Primary Water Environments." In ASME 2003 Pressure Vessels and Piping Conference. ASMEDC, 2003. http://dx.doi.org/10.1115/pvp2003-1776.

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Models of fatigue crack growth rates for medium and low sulfur ferritic pressure vessel steels in pressurized water reactor (PWR) primary environments are developed based on a recent collection of UK data and the EPRI Database for Environmentally Assisted Cracking (EDEAC). The combined UK and EDEAC database contains a broader range of experimental conditions specific to PWRs than either database by itself. Both probabilistic and conventional crack growth rate models are developed that reduce unnecessary conservatism for medium and low sulfur PWR primary water applications and eliminate the explicit dependence on rise time that caused difficulties applying prior models.

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Roure-Pujol, Carme, Pi: Paola Galbany-Estragués, Aija Ahokas, Joan Carles Casas-Baroy, D. Cavani, C. Gradellini, K. Grendova, et al. "EDUCATING VACCINATION COMPETENCE PROJECT (EDUVAC)." In 11th International Conference on Education and New Learning Technologies. IATED, 2019. http://dx.doi.org/10.21125/edulearn.2019.2197.

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Limes, Greg, Scott Christa, Craig Pires, and Karen Gundy-Burlet. "EDAC events during the LADEE mission." In 2015 IEEE Aerospace Conference. IEEE, 2015. http://dx.doi.org/10.1109/aero.2015.7119107.

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Hao, Li, and Lixin Yu. "A Study on the Hardware Implementation Of EDAC." In 2008 Third International Conference on Convergence and Hybrid Information Technology (ICCIT). IEEE, 2008. http://dx.doi.org/10.1109/iccit.2008.14.

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Chen, Po-yuan, Yi-ting Yeh, Chao-hsun Chen, Jen-chieh Yeh, Cheng-wen Wu, Jeng-shen Lee, and Yu-chang Lin. "An Enhanced EDAC Methodology for Low Power PSRAM." In 2006 IEEE International Test Conference. IEEE, 2006. http://dx.doi.org/10.1109/test.2006.297689.

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"EDAC. Proceedings of the European Design Automation Conference." In Proceedings of the European Design Automation Conference. IEEE, 1990. http://dx.doi.org/10.1109/edac.1990.136609.

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"EDAC. Proceedings of the European Conference on Design Automation." In Proceedings of the European Conference on Design Automation. IEEE, 1991. http://dx.doi.org/10.1109/edac.1991.206333.

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Ching-Yi Chen and Cheng-Wen Wu. "An adaptive code rate EDAC scheme for random access memory." In 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010). IEEE, 2010. http://dx.doi.org/10.1109/date.2010.5456955.

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Ahmad, Sadia, Minahil Zahra, Salma Zainab Farooq, and Adnan Zafar. "Comparison of EDAC schemes for DDR memory in space applications." In 2013 International Conference on Aerospace Science & Engineering (ICASE). IEEE, 2013. http://dx.doi.org/10.1109/icase.2013.6785556.

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