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Journal articles on the topic 'Electrical and Computer Engineering. Metal oxide semiconductors'

Author: Grafiati

Published: 4 June 2021

Last updated: 16 February 2022

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1

Saha, H., and C. Chaudhuri. "Complementary Metal Oxide Semiconductors Microelectromechanical Systems Integration." Defence Science Journal 59, no. 6 (2009): 557–67. http://dx.doi.org/10.14429/dsj.59.1560.

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2

Chavan, YV, and DK Mishra. "Improved Complementary Metal Oxide Semiconductor Digital Pixel Sensor." IETE Journal of Research 55, no. 5 (2009): 222. http://dx.doi.org/10.4103/0377-2063.57600.

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3

Fadavi Roudsari, Anita, Iman Khodadad, Simarjeet Singh Saini, and M. P. Anantram. "Photon-Induced Negative Capacitance in Metal Oxide Semiconductor Structures." IEEE Transactions on Nanotechnology 15, no. 5 (2016): 715–19. http://dx.doi.org/10.1109/tnano.2016.2519897.

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4

Zhou, Huimei, Bei Li, Zheng Yang, et al. "$\hbox{TiSi}_{2}$ Nanocrystal Metal Oxide Semiconductor Field Effect Transistor Memory." IEEE Transactions on Nanotechnology 10, no. 3 (2011): 499–505. http://dx.doi.org/10.1109/tnano.2010.2049271.

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5

McDonough, Colin, Doug La Tulipe, Dan Pascual, et al. "Heterogeneous Integration of a 300-mm Silicon Photonics-CMOS Wafer Stack by Direct Oxide Bonding and Via-Last 3-D Interconnection." Journal of Microelectronics and Electronic Packaging 13, no. 2 (2016): 71–76. http://dx.doi.org/10.4071/imaps.494.

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A fully functional Si photonics and 65-nm complementary metal-oxide semiconductor (CMOS) heterogeneous three-dimensional (3-D) integration is demonstrated for the first time in a 300-mm production environment. Direct oxide wafer bonding was developed to eliminate voids between silicon on insulator photonics and bulk Si CMOS wafers. A via-last, Cu through-oxide via 3-D integration was developed for low capacitance electrical connections with no impact on the CMOS performance. The 3-D yield approaching 100% was demonstrated on &gt;20,000 via chains.

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6

Yoshikawa, Masahito, Takeshi Ohshima, Hisayoshi Itoh, et al. "Effects of gamma-ray irradiation on the electrical characteristics of SiC metal-oxide-semiconductor structures." Electronics and Communications in Japan (Part II: Electronics) 81, no. 10 (1998): 37–47. http://dx.doi.org/10.1002/(sici)1520-6432(199810)81:10<37::aid-ecjb5>3.0.co;2-h.

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7

Ghosh, Sumalya, Bishnu Prasad De, Rajib Kar, Durbadal Mandal, and Ashis Kumar Mal. "Optimal design of complementary metal-oxide-semiconductor analogue circuits: An evolutionary approach." Computers & Electrical Engineering 80 (December 2019): 106485. http://dx.doi.org/10.1016/j.compeleceng.2019.106485.

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8

Krik, Soufiane, Andrea Gaiardo, Matteo Valt, et al. "First-Principles Study of Electronic Conductivity, Structural and Electronic Properties of Oxygen-Vacancy-Defected SnO2." Journal of Nanoscience and Nanotechnology 21, no. 4 (2021): 2633–40. http://dx.doi.org/10.1166/jnn.2021.19116.

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The use of computer simulations has become almost essential for prediction and interpretation of device's performance. In gas sensing field, the simulation of specific conditions, which determine the physical-chemical properties of widely used metal oxide semiconductors, can be used to investigate the performance of gas sensors based on these kinds of materials. The aim of this work was to evaluate the physical-chemical properties of tin dioxide employed for environmental and health gas sensing application and to investigate the influence of oxygen vacancies on its properties by means of densi

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9

Wang, Chen, Xiuli Zhao, Hao Liu, Xin Chao, Hao Zhu, and Qingqing Sun. "A High-Density Memory Design Based on Self-Aligned Tunneling Window for Large-Capacity Memory Application." Electronics 10, no. 16 (2021): 1954. http://dx.doi.org/10.3390/electronics10161954.

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Despite the continuous downscaling of complementary metal–oxide–semiconductor (CMOS) devices, various scenarios of technology have also been proposed toward the shrinking of semiconductor memory. In this paper, a high-density memory (HDM) has been proposed on the basis of band-to-band tunneling (BTBT) for low-power, high density, and high-speed memory applications. The geometric structure and electrical properties have been demonstrated by using TCAD tools. Typical memory operations including read, program, and erase have been designed and performed. High operation speed, lower power consumpti

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10

Saraniti, M., G. Zandler, G. Formicone, and S. Goodnick. "Cellular Automata Studies of Vertical Silicon Devices." VLSI Design 8, no. 1-4 (1998): 111–15. http://dx.doi.org/10.1155/1998/89897.

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We present systematic theoretical Cellular Automata (CA) studies of a novel nanometer scale Si device, namely vertically grown Metal Oxide Field Effect Transistors (MOSFET) with channel lengths between 65 and 120 nm. The CA simulations predict drain characteristics and output conductance as a function of gate length. The excellent agreement with available experimental data indicates a high quality oxide/semiconductor interface. Impact ionization is shown to be of minor importance. For inhomogeneous p-doping profiles along the channel, significantly improved drain current saturation is predicte

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11

Dunlap, Justin C. "Dark current in an active pixel complementary metal-oxide-semiconductor sensor." Journal of Electronic Imaging 20, no. 1 (2011): 013005. http://dx.doi.org/10.1117/1.3533328.

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12

Mietzner, T., J. Jakumeit, and U. Ravaioli. "Influence of Electron-Electron Interaction on Electron Distributions in Short Si-MOSFETs Analysed Using the Local Iterative Monte Carlo Technique." VLSI Design 13, no. 1-4 (2001): 175–78. http://dx.doi.org/10.1155/2001/68217.

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The effects of electron–electron interaction on the electron distribution in n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) are studied using the Local Iterative Monte Carlo (LIMO) technique. This work demonstrates that electron–electron scattering can be efficiently treated within this technique. The simulation results of a 90 nm Si-MOSFET are presented. We observe an increase of the high energy tail of the electron distribution at the transition from channel to drain.

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13

Demkov, Alexander A., Xiaodong Zhang, and Heather Loechelt. "Theoretical Investigation of Ultrathin Gate Dielectrics." VLSI Design 13, no. 1-4 (2001): 135–43. http://dx.doi.org/10.1155/2001/98032.

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We describe a theoretical methodology for screening potential gate dielectric materials. A recently proposed method for constructing realistic structural models of the Si-dielectric interface is used to generate the Si-SiO2-Si and Si-SiON-SiO2-Si model metal-oxide-semiconductor (MOS) structures. We discuss methods to estimate the valence band discontinuity at the corresponding interface. We use Landauer's ballistic transport approach to investigate the low bias leakage through these ultrathin dielectric layers.

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14

Maity, N. P., R. R. Thakur, Reshmi Maity, R. K. Thapa, and S. Baishya. "Analysis of Interface Charge Densities for High-k Dielectric Materials based Metal Oxide Semiconductor Devices." International Journal of Nanoscience 15, no. 05n06 (2016): 1660011. http://dx.doi.org/10.1142/s0219581x16600115.

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In this paper, the interface charge densities ([Formula: see text]) are studied and analyzed for ultra thin dielectric metal oxide semiconductor (MOS) devices using different high-k dielectric materials such as Al2O3, ZrO2 and HfO2. The [Formula: see text] have been calculated by a new approach using conductance method and it indicates that by reducing the thickness of the oxide, the [Formula: see text] increases and similar increase is also found by replacing SiO2 with high-k. For the same oxide thickness, SiO2 has the lowest [Formula: see text] and found to be the order of 10[Formula: see te

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15

Maiellaro, Giorgio, Giovanni Caruso, Salvatore Scaccianoce, Mauro Giacomini, and Angelo Scuderi. "40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors." Electronics 10, no. 17 (2021): 2114. http://dx.doi.org/10.3390/electronics10172114.

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This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38

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16

Aubreton, Olivier. "Retina for pattern matching in standard 0.6-μm complementary metal oxide semiconductor technology". Journal of Electronic Imaging 13, № 3 (2004): 559. http://dx.doi.org/10.1117/1.1762886.

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17

Mladenov, Valeri. "A Unified and Open LTSPICE Memristor Model Library." Electronics 10, no. 13 (2021): 1594. http://dx.doi.org/10.3390/electronics10131594.

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In this paper, a unified and open linear technology simulation program with integrated circuit emphasis (LTSPICE) memristor library is proposed. It is suitable for the analysis, design, and comparison of the basic memristors and memristor-based circuits. The library could be freely used and expanded with new LTSPICE memristor models. The main existing standard memristor models and several enhanced and modified models based on transition metal oxides such as titanium dioxide, hafnium dioxide, and tantalum oxide are included in the library. LTSPICE is one of the best software for analysis and de

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18

Choi, Kyu-Jin, Jae-Hyun Park, Seong-Kyun Kim, and Byung-Sung Kim. "K-Band Hetero-Stacked Differential Cascode Power Amplifier with High Psat and Efficiency in 65 nm LP CMOS Technology." Electronics 10, no. 8 (2021): 890. http://dx.doi.org/10.3390/electronics10080890.

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A K-band complementary metal-oxide-semiconductor (CMOS) differential cascode power amplifier is designed with the thin-oxide field effect transistor (FET) common source (CS) stage and thick-oxide FET common gate (CG) stage. Use of the thick-oxide CG stage affords the high supply voltage to 3.7 V and enables the high output power. Additionally, simple analysis shows that the gain degradation due to the low cut-off frequency of the thick-oxide CG FET can be compensated by the high output resistance of the thick-oxide FET if the inter-stage node is neutralized. The measured results of the propose

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19

Nair, Kartik, Bhavya Sekhani, Krina Shah, and Sunil Karamchandani. "Expiry Prediction and Reducing Food Wastage using IoT and ML." International journal of electrical and computer engineering systems 12, no. 3 (2021): 155–62. http://dx.doi.org/10.32985/ijeces.12.3.4.

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This paper details development of a low-cost, small-size, and portable electronic nose (E-nose) for the prediction of the expiry date of food products. The Sensor array is composed of commercially available metal oxide semiconductors sensors like MQ2 sensor, temperature sensor, and humidity sensor, which were interfaced with the help of ESP8266 and Arduino Uno for data acquisition, storage, and analysis of the dataset consisting of the odor from the fruit at different ripening stages. The developed system is used to analyze gas sensor values from various fruits like bananas and tomatoes. Respo

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20

CHOI, S. S., M. Y. JUNG, J. W. KIM, J. H. BOO, and J. S. YANG. "FABRICATION OF NEARFIELD OPTICAL PROBE ARRAY USING VARIOUS NANOFABRICATION PROCEDURES." International Journal of Nanoscience 02, no. 04n05 (2003): 283–91. http://dx.doi.org/10.1142/s0219581x03001309.

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The nanosize silicon oxide aperture on the cantilever array has been successfully fabricated as nearfield optical probe. The various semiconductor processes were utilized for subwavelength size aperture fabrication. The anisotropic etching of the Si substrate by alkaline solutions followed by anisotropic crystal orientation dependent oxidation, anisotropic plasma etching, isotropic oxide etching was carried out. The 3 and 4 micron size dot array were patterned on the Si(100) wafer. After fabrication of the V-groove shape by anisotropic TMAH etching, the oxide growth at 1000° C was performed to

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21

Kim, SangHyeon, Masafumi Yokoyama, Noriyuki Taoka, et al. "Experimental Study on Electron Mobility in InxGa1-xAs-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors With In Content Modulation and MOS Interface Buffer Engineering." IEEE Transactions on Nanotechnology 12, no. 4 (2013): 621–28. http://dx.doi.org/10.1109/tnano.2013.2265435.

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22

Chauhan, Manorama, Ravindra Singh Kushwah, Pavan Shrivastava, and Shyam Akashe. "Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits." International Journal of Nanoscience 13, no. 02 (2014): 1450012. http://dx.doi.org/10.1142/s0219581x14500124.

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In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using C

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23

Karjalainen, Päivi H., and Pekka Heino. "On-Wafer Capacitors Under Mechanical Stress." Journal of Electronic Packaging 129, no. 3 (2006): 287–90. http://dx.doi.org/10.1115/1.2753918.

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New packaging materials make it possible to produce flexible system in package (SIP) and system on package (SOP) modules. However, in these the integrated circuits are exposed to increased mechanical stresses. The stresses may become even more severe when thinned chips are used. The effect of mechanical stress on the characteristics of on-wafer capacitors was studied. The mechanical stress increased clearly the resonance frequency of poly-insulator-poly capacitors, but caused only minor impedance changes for metal-insulator-metal capacitors. No fatal stress-induced phenomenon was found and the

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24

Rengel, Raúl, and María J. Martín. "Harmonic distortion in laterally asymmetric channel metal-oxide-semiconductor field-effect transistors operating in the linear regime." International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 27, no. 5-6 (2013): 792–801. http://dx.doi.org/10.1002/jnm.1928.

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25

Chang, Shu-Tong, Chang-Chun Lee, and P. H. Sun. "Technology computer-aided design simulation study for a strained InGaAs channel n-type metal-oxide-semiconductor field-effect transistor with a high-k dielectric oxide layer and a metal gate electrode." Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena 29, no. 3 (2011): 032203. http://dx.doi.org/10.1116/1.3578466.

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26

Sun, Ling, Jianjun Gao, and Andreas Werthof. "Effect of guard-ring on the DC and high-frequency performance of deep-submicrometer metal oxide semiconductor field effect transistor." International Journal of RF and Microwave Computer-Aided Engineering 24, no. 2 (2013): 259–67. http://dx.doi.org/10.1002/mmce.20757.

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27

Jin, Minhyun, Hyeonseob Noh, Minkyu Song, and Soo Youn Kim. "Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits." Sensors 20, no. 13 (2020): 3649. http://dx.doi.org/10.3390/s20133649.

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In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According

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28

Chien, Hung-Chun. "Full-Phase Operation Transresistance-Mode Precision Full-Wave Rectifier Designs Using Single Operational Transresistance Amplifier." Active and Passive Electronic Components 2019 (March 3, 2019): 1–18. http://dx.doi.org/10.1155/2019/1584724.

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This study proposed the designs of two full-phase operation transresistance-mode (TRM) precision full-wave rectifiers. The first circuit consisted of a single operational transresistance amplifier (OTRA), four diodes, and a resistor. The second scheme was an OTRA combined with a full metal-oxide semiconductor field-effect transistor-based design, which is preferable for integrated circuit implementation because no passive components are used in the circuit topology. Based on our literature review, this is the first study that discussed a full-phase operation transresistance-mode precision full

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29

Trellakis, A., and U. Ravaioli. "Three-dimensional Spectral Solution of Schrödinger Equation." VLSI Design 13, no. 1-4 (2001): 341–47. http://dx.doi.org/10.1155/2001/76808.

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We present a fast and robust method for the full-band solution of Schrödinger's equation on a grid, with the goal of achieving a more complete description of high energy states and realistic temperatures. Using Fast Fourier Transforms, Schrödinger's equation in the one band approximation can be expressed as an iterative eigenvalue problem for arbitrary shapes of the conduction band. The resulting eigenvalue problem can then be solved using Krylov subspace methods as Arnoldi iteration. We demonstrate the algorithm by presenting an example concerning non-parabolic effects in an ultra-small Metal

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30

Jaikla, Winai, Sirigul Bunrueangsak, Fabian Khateb, Tomasz Kulej, Peerawut Suwanjan, and Piya Supavarasuwat. "Inductance Simulators and Their Application to the 4th Order Elliptic Lowpass Ladder Filter Using CMOS VD-DIBAs." Electronics 10, no. 6 (2021): 684. http://dx.doi.org/10.3390/electronics10060684.

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This paper presents inductance simulators using the voltage differencing differential input buffered amplifier (VD-DIBA) as an active building block. Three types of inductance simulators, including floating lossless inductance, series inductance-resistance, and parallel inductance-resistance simulators, are proposed, in addition to their application to the 4th order elliptic lowpass ladder filter. The simple design procedures of these inductance simulators using a circuit block diagram are also given. The proposed inductance simulators employ two VD-DIBAs and two passive elements. The compleme

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31

Wu, Min-Lin, Yung-Hsien Wu, Chun-Yen Chao, Chia-Chun Lin, and Chao-Yi Wu. "Crystalline ZrTiO$_{\bf 4}$-Gated Ge Metal–Oxide–Semiconductor Devices With Amorphous Yb$_{\bf 2}$O$_{\bf 3}$ as a Passivation Layer." IEEE Transactions on Nanotechnology 12, no. 6 (2013): 1018–21. http://dx.doi.org/10.1109/tnano.2013.2283252.

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32

KUMAR, M. JAGADESH, and TARUN VIR SINGH. "QUANTUM CONFINEMENT EFFECTS IN STRAINED SILICON MOSFETS." International Journal of Nanoscience 07, no. 02n03 (2008): 81–84. http://dx.doi.org/10.1142/s0219581x08005195.

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In this paper, we have examined the effect of quantum confinement of carriers on the threshold voltage of strained-silicon (s- Si ) nanoscale Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). Using results from quantum theory and two-dimensional simulation, we show that strain-induced threshold voltage roll-off in s- Si nanoscale MOSFETs can be overcome by decreasing s- Si layer thickness. Based on our simulation study, we provide an optimization between threshold voltage, strain and s- Si layer thickness.

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33

Chien, Feng-Tso, Zhi-Zhe Wang, Cheng-Li Lin, Tsung-Kuei Kang, Chii-Wen Chen, and Hsien-Chin Chiu. "150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers." Micromachines 11, no. 5 (2020): 504. http://dx.doi.org/10.3390/mi11050504.

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A rating voltage of 150 and 200 V split-gate trench (SGT) power metal-oxide- semiconductor field-effect transistor (Power MOSFET) with different epitaxial layers was proposed and studied. In order to reduce the specific on-resistance (Ron,sp) of a 150 and 200 V SGT power MOSFET, we used a multiple epitaxies (EPIs) structure to design it and compared other single-EPI and double-EPIs devices based on the same fabrication process. We found that the bottom epitaxial (EPI) layer of a double-EPIs structure can be designed to support the breakdown voltage, and the top one can be adjusted to reduce th

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34

Ye, Hua, Harry Efstathiadis, and Pradeep Haldar. "Numerical Thermal Simulation of Cryogenic Power Modules Under Liquid Nitrogen Cooling." Journal of Electronic Packaging 128, no. 3 (2005): 267–72. http://dx.doi.org/10.1115/1.2229226.

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Understanding the thermal performance of power modules under liquid nitrogen cooling is important for the design of cryogenic power electronic systems. When the power device is conducting electrical current, heat is generated due to Joule heating. The heat needs to be efficiently dissipated to the ambient in order to keep the temperature of the device within the allowable range; on the other hand, it would be advantageous to boost the current levels in the power devices to the highest possible level. Projecting the junction temperature of the power module during cryogenic operation is a crucia

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35

Li, Xi, Soheil Nazar Shahsavani, Xuan Zhou, Massoud Pedram, and Peter A. Beerel. "A Variation-aware Hold Time Fixing Methodology for Single Flux Quantum Logic Circuits." ACM Transactions on Design Automation of Electronic Systems 26, no. 6 (2021): 1–17. http://dx.doi.org/10.1145/3460289.

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Single flux quantum (SFQ) logic is a promising technology to replace complementary metal-oxide-semiconductor logic for future exa-scale supercomputing but requires the development of reliable EDA tools that are tailored to the unique characteristics of SFQ circuits, including the need for active splitters to support fanout and clocked logic gates. This article is the first work to present a physical design methodology for inserting hold buffers in SFQ circuits. Our approach is variation-aware, uses common path pessimism removal and incremental placement to minimize the overhead of timing fixes

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36

Salem, Thomas E., Stephen B. Bayne, and Don Porschet. "An Experimental Approach for Thermal Characterization of Water-Cooled Heat Sinks Using Fourier Analysis Techniques." Journal of Electronic Packaging 129, no. 4 (2007): 512–17. http://dx.doi.org/10.1115/1.2814056.

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As power electronic applications continue to switch higher levels of voltage and current in smaller-sized component packages, the resulting increase in power density requires efficient thermal management. This paper compares the thermal performance for operating a metal-oxide-semiconductor field-effect transistor on a water-cooled pole-arrayed heat sink versus a novel water-cooled microchannel heat sink. Details are presented on an innovative technique using Fourier analysis techniques for determining the thermal capacitance modeling parameter for the heat sinks from experimental data.

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37

Saggese, Gerardo, Mattia Tambaro, Elia A. Vallicelli, et al. "Comparison of Sneo-Based Neural Spike Detection Algorithms for Implantable Multi-Transistor Array Biosensors." Electronics 10, no. 4 (2021): 410. http://dx.doi.org/10.3390/electronics10040410.

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Real-time neural spike detection is an important step in understanding neurological activities and developing brain-silicon interfaces. Recent approaches exploit minimally invasive sensing techniques based on implanted complementary metal-oxide semiconductors (CMOS) multi transistors arrays (MTAs) that limit the damage of the neural tissue and provide high spatial resolution. Unfortunately, MTAs result in low signal-to-noise ratios due to the weak capacitive coupling between the nearby neurons and the sensor and the high noise power coming from the analog front-end. In this paper we investigat

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38

Ge, Zhiwei. "Field-programmable gate array-based hardware architecture for image processing with complementary metal-oxide-semiconductor image sensor." Journal of Electronic Imaging 19, no. 3 (2010): 033014. http://dx.doi.org/10.1117/1.3483904.

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39

Smith, Brian, and Cristina Amon. "Simultaneous Electrothermal Test Method for Pyroelectric Microsensors." Journal of Electronic Packaging 129, no. 4 (2007): 504–11. http://dx.doi.org/10.1115/1.2804101.

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Pyroelectric film materials, including polyvinylidene fluoride (PVDF) and its copolymers (e.g., P(VDF/trifluoroethylene)), are attractive candidates for low-cost infrared detection and imaging applications due to their compatibility with complementary metal-oxide semiconductor processing and inexpensive packaging requirements compared to semiconductor-based detectors. The pyroelectric coefficient (p) describes the material’s electric response to a change in sensor temperature and is the main contributor to the sensitivity and detectivity of the system. However, this value can vary greatly with

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40

Choi, Daniel, Viola Fucsko, E. H. Yang, Jung-Rae Park, Fahad Khalid, and Young-Kun Kim. "Vertical Arrays of Copper Nanotube Grown on Silicon Substrate by CMOS Compatible Electrochemical Process for IC Packaging Applications." Journal of Microelectronics and Electronic Packaging 6, no. 3 (2009): 154–57. http://dx.doi.org/10.4071/1551-4897-6.3.154.

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We present an electrodeposition-based fabrication process which can be complementary metal oxide semiconductor (CMOS) compatible for creating vertical arrays of copper (Cu) nanotubes for integrated circuit (IC) packaging applications. Since such nanotube structures offer high surface-to-volume ratios, low resistivity, and high thermal conductivity, they are especially suited for IC packaging applications requiring efficient heat transfer as well as electrical interconnect applications. In this work, Cu nanotube arrays were electrodeposited into alumina nanopore templates with pore diameters of

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41

Ro, Duckhoon, Changhong Min, Myounggon Kang, Ik Joon Chang, and Hyung-Min Lee. "A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems." Sensors 20, no. 1 (2019): 171. http://dx.doi.org/10.3390/s20010171.

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For stable and effective control of the sensor system, analog sensor signals such as temperature, pressure, and electromagnetic fields should be accurately measured and converted to digital bits. However, radiation environments, such as space, flight, nuclear power plants, and nuclear fusion reactors, as well as high-reliability applications, such as automotive semiconductor systems, suffer from radiation effects that degrade the performance of the sensor readout system including analog-to-digital converters (ADCs) and cause system malfunctions. This paper investigates an optimal ADC structure

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42

Cha, Kyuhyun, Jongwoon Yoon, and Kwangsoo Kim. "3.3-kV 4H-SiC Split-Gate DMOSFET with Floating p+ Polysilicon for High-Frequency Applications." Electronics 10, no. 6 (2021): 659. http://dx.doi.org/10.3390/electronics10060659.

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A split-gate metal–oxide–semiconductor field-effect transistor (SG-DMOSFET) is a well-known structure used for reducing the gate–drain capacitance (CGD) to improve switching characteristics. However, SG-DMOSFETs have problems such as the degradation of static characteristics and a high gate-oxide electric field. To solve these problems, we developed a SG-DMOSFET with floating p+ polysilicon (FPS-DMOSFET) and compared it with a conventional planar DMOSFET (C-DMOSFET) and a SG-DMOSFET through Technology Computer-Aided Design (TCAD) simulations. In the FPS-DMOSFET, floating p+ polysilicon (FPS) i

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Li, Yangyang, Chuanbin Zeng, Xiaojing Li, et al. "Applications of Direct-Current Current–Voltage Method to Total Ionizing Dose Radiation Characterization in SOI NMOSFETs with Different Process Conditions." Electronics 10, no. 7 (2021): 858. http://dx.doi.org/10.3390/electronics10070858.

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As a promising candidate in space radiation hardened applications, silicon-on-insulator (SOI) devices face the severe problem of total ionizing dose (TID) radiation because of the thick buried oxide (BOX) layer. The direct-current current–voltage (DCIV) method was applied for studying TID radiation of SOI metal–oxide–semiconductor field–effect transistors (MOSFETs) with different manufacture processes. It is found that the peak of high-voltage well (PX) devices shows a larger left-shift and a slower multitude increase along with radiation dose, compared with that of low-voltage well (PV) devic

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Tang, Jianming, Weidong Zhu, and Yunbo Bi. "A Computer Vision-Based Navigation and Localization Method for Station-Moving Aircraft Transport Platform with Dual Cameras." Sensors 20, no. 1 (2020): 279. http://dx.doi.org/10.3390/s20010279.

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In order to develop equipment adapted to the aircraft pulse final assembly line, a vision-based aircraft transport platform system is developed. This article explores a guiding method between assembly stations which is low-cost and easy to change routes by using two-dimensional code and two complementary metal oxide semiconductor (CMOS) cameras. The two cameras installed on the front and back of the platform read the two-dimensional code containing station information to guide the platform. In the process of guiding, the theoretical position and posture of the platform at each assembly station

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Teramoto, Akinobu. "Evaluation of Low-Frequency Noise in MOSFETs Used as a Key Component in Semiconductor Memory Devices." Electronics 10, no. 15 (2021): 1759. http://dx.doi.org/10.3390/electronics10151759.

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Methods for evaluating low-frequency noise, such as 1/f noise and random telegraph noise, and evaluation results are described. Variability and fluctuation are critical in miniaturized semiconductor devices because signal voltage must be reduced in such devices. Especially, the signal voltage in multi-bit memories must be small. One of the most serious issues in metal-oxide-semiconductor field-effect-transistors (MOSFETs) is low-frequency noise, which occurs when the signal current flows at the interface of different materials, such as SiO2/Si. Variability of low-frequency noise increases with

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Chen, Zeqi, Jianping Hu, Hao Ye, and Zhufei Chu. "T-Channel Field Effect Transistor with Three Input Terminals (Ti-TcFET)." Micromachines 11, no. 1 (2020): 64. http://dx.doi.org/10.3390/mi11010064.

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In this paper, a novel T-channel field effect transistor with three input terminals (Ti-TcFET) is proposed. The channel of a Ti-TcFET consists of horizontal and vertical sections. The top gate is above the horizontal channel, while the front gate and back gate are on either side of the vertical channel. The T-shaped channel structure increases the coupling area between the top gate and the front and back gates, which improves the ability of the gate electrodes to control the channel. What’s more, it makes the top gate have almost the same control ability for the channel as the front gate and t

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Pérez-Bailón, Jorge, Belén Calvo, and Nicolás Medrano. "A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications." Electronics 10, no. 17 (2021): 2108. http://dx.doi.org/10.3390/electronics10172108.

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This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a −40 to 120 °C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (Iq = 8.6 µA) and minimum area consumption (0.109 mm2) are maintained, including a reference voltage Vref = 0.4 V. It uses a high-gain dynamically biased folded-based error amp

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Abdalla, Yasser S. "A novel flash‐like all‐metal‐oxide semiconductor analog‐to‐digital converter suitable for system on chips systems." International Journal of Circuit Theory and Applications 48, no. 11 (2020): 1960–74. http://dx.doi.org/10.1002/cta.2866.

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Kommuri, Krishnaveni, and Venkata Ratnam Kolluru. "Implementation of modular MPPT algorithm for energy harvesting embedded and IoT applications." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 5 (2021): 3660. http://dx.doi.org/10.11591/ijece.v11i5.pp3660-3670.

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The establishment of the latest IoT systems available today such as smart cities, smart buildings, and smart homes and wireless sensor networks (WSNs) are let the main design restriction on the inadequate supply of battery power. Hence proposing a solar-based photovoltaic (PV) system which is designed DC-DC buck-boost converter with an improved modular maximum power point tracking (MPPT) algorithm. The output voltage depends on the inductor, capacitor values, metal oxide semiconductor field effect transistor (MOSFET) switching frequency, and duty cycle. This paper focuses on the design and sim

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Kang, Won-Gu Kang, Jong-Son Lyu Lyu, and Hyung Joun Yoo Yoo. "A Novel Body-Tied Silicon-On-Insulator(SOI) n-channel Metal-Oxide-Semiconductor Field-Effect Transistor with Grounded Body Electrode." ETRI Journal 17, no. 4 (1996): 1–12. http://dx.doi.org/10.4218/etrij.96.0196.0041.

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