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Journal articles on the topic 'Electrical circuit fabrication'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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Peng, Yitian, Yuanzhong Hu, and Weibing Lu. "Fabrication and Electrical Characterization of Multiwalled Carbon Nanotube-Based Circuit at Room Temperature." Journal of Nanomaterials 2011 (2011): 1–5. http://dx.doi.org/10.1155/2011/297534.

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Multiwalled carbon nanotube (MWCNT) deposited on a pair of predetermined aluminum electrodes treated with the (3-Aminopropyl)-triethoxysilane (APTES) self-assembled monolayers (SAMs). The MWCNT bridges electrodes and forms electrode/MWCNT/electrode circuit on silicon with 500 nm silicon dioxide. Then the Metal (Ti/Au) pads were fabricated on MWCNT to bury the MWCNT into metal electrodes. The electrical properties of MWCNT-based circuits before and after the fabrication of metal pads were characterized. Results indicate that metal pads on MWCNT improved the electrical properties MWCNT-based circuit largely.

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Singh, Vimlesh, Priyanka Bansal, and P. K.Singhal. "Microstrip line Antenna Fabrication Material." International Journal of Engineering & Technology 7, no. 2.8 (2018): 340. http://dx.doi.org/10.14419/ijet.v7i2.8.10437.

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This paper presents an extensive survey of electromagnetic materials used for antenna fabrication, which find application in Civilian life as well as defense life. When a densely packed microwave integrated circuit is designed, it requires protection from higher power transient because of specific polarization and frequency response. To meet specification of such kind of microwave circuits it is desired to exploit properties of fabricating materials, which are not found in nature but can be prepared with specific proportion of chemical element combination. This study provides in-depth responses of materials toward electromagnetic wave's characteristics such as dielectric, flexible electronics, electrical and thermal properties, which have vast potential in communication engineering.

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DJAHANSHAHI, HORMOZ, MAJID AHMADI, GRAHAM A. JULLIEN, and WILLIAM C. MILLER. "A LOW-VARIATION NONLINEAR NEURON CIRCUIT." Journal of Circuits, Systems and Computers 08, no. 04 (1998): 447–51. http://dx.doi.org/10.1142/s0218126698000249.

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A resistive-type neuron circuit is presented that combines nonlinear characteristics of four MOS transistors to realize a saturating function. Despite circuit simplicity, characteristic variations are found to be small based on circuit analyses and fabrication measurements. Maximum variation between neurons within one chip is 1.3%, while worst-case chip-to-chip variation from 10 fabrications is 2.2%.

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Kim, Ernest M., and Thomas F. Schubert. "A low-cost design experience for junior-level electronics circuits laboratories through emulation of industry-printed circuit board design practice." International Journal of Electrical Engineering & Education 54, no. 3 (2016): 208–22. http://dx.doi.org/10.1177/0020720916673650.

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Over a 2-year period, printed circuit board layout design and test were included in the laboratory portion of the second of two junior-level electronic circuits courses. Printed circuit board design using industry-accepted board specifications and standard industry Gerber file export experience was developed. The students’ printed circuit board design experience emulated real-world situations and cost criteria. The instructor served as the fabricator in this model of the industrial design situation. Students individually used industry standard schematic capture and layout software to develop a printed circuit board for a simplified discrete µA741 operational amplifier. The layout designs were submitted as industry standard Gerber files electronically to the instructor/fabricator for evaluation. Grades were assigned by evaluating the accuracy and cost effectiveness of the design by minimizing traces, reducing printed circuit board geometry, and limiting the number of vias, which ultimately reduces fabricator tooling cost. Feedback was provided by the instructor who acted as the industry fabricator to individual students. A single fabricated printed circuit board, designed by the instructor (and fabricated by a commercial printed circuit board manufacturer), was delivered to students for assembly and test. By delivering a single printed circuit board design to students, fabrication costs can be minimized and students can inspect the delivered board as an exemplar. Assessments of the student perceptions of knowledge of and confidence in applying printed circuit board techniques in designing and releasing a printed circuit board were conducted prior to and after the printed circuit board layout design and test. On a 5-point scale, overall student-reported knowledge increased by 2.14 and overall student confidence increased by 1.20 points. Faculty assessment of knowledge, as measured by scoring short answers to knowledge statements, correlated well with student report and showed an average increase of 2.70.

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CARD, HOWARD C., DEAN K. McNEILL, CHRISTIAN R. SCHNEIDER, ROLAND S. SCHNEIDER, and BRION K. DOLENKO. "TOLERANCE OF ON-CHIP LEARNING TO VARIOUS CIRCUIT INACCURACIES." Journal of Circuits, Systems and Computers 08, no. 02 (1998): 315–27. http://dx.doi.org/10.1142/s0218126698000146.

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An investigation is made of the tolerance of various in-circuit learning algorithms to component imprecision and other circuit limitations in artificial neural networks. In contrast with most previous work, the various circuit limitations are treated separately for their effects on learning. Supervised learning mechanisms including backpropagation and contrastive Hebbian learning, and unsupervised soft competitive learning were found to be sufficiently tolerant of those levels of arithmetic inaccuracy, noise, nonlinearity, weight decay, and statistical variation from fabrication that we have experienced in 1.2 μm analog CMOS circuits employing Gilbert multipliers as the primary computational element. These learning circuits also function properly in the presence of offset errors in analog multipliers and adders, provided that the computed weight updates are constrained by the circuitry to be made only when they exceed certain minimum or threshold values. These results may also be relevant for other analog circuit approaches and for compact (low bit rate) digital implementations, although in this case, the minimum weight increment defined by the bit precision could necessitate stochastic updating.

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Abu-Khalaf, Jumana, Razan Saraireh, Saleh Eisa, and Ala’aldeen Al-Halhouli. "Experimental Characterization of Inkjet-Printed Stretchable Circuits for Wearable Sensor Applications." Sensors 18, no. 10 (2018): 3476. http://dx.doi.org/10.3390/s18103476.

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This paper introduces a cost-effective method for the fabrication of stretchable circuits on polydimethylsiloxane (PDMS) using inkjet printing of silver nanoparticle ink. The fabrication method, presented here, allows for the development of fully stretchable and wearable sensors. Inkjet-printed sinusoidal and horseshoe patterns are experimentally characterized in terms of the effect of their geometry on stretchability, while maintaining adequate electrical conductivity. The optimal fabricated circuit, with a horseshoe pattern at an angle of 45°, is capable of undergoing an axial stretch up to a strain of 25% with a resistance under 800 Ω. The conductivity of the circuit is fully reversible once it is returned to its pre-stretching state. The circuit could also undergo up to 3000 stretching cycles without exhibiting a significant change in its conductivity. In addition, the successful development of a novel inkjet-printed fully stretchable and wearable version of the conventional pulse oximeter is demonstrated. Finally, the resulting sensor is evaluated in comparison to its commercially available counterpart.

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Amirnudin, Amirul Adlan, Farahiyah Mustafa, Anis Maisarah Mohd Asry, and Sy Yi Sim. "Vibration Based Energy Harvesting Interface Circuit using Diode-Capacitor Topologies for Low Power Applications." International Journal of Power Electronics and Drive Systems (IJPEDS) 8, no. 4 (2017): 1943. http://dx.doi.org/10.11591/ijpeds.v8.i4.pp1943-1947.

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<span>A battery-less energy harvesting interface circuit to extract electrical energy from vibration has been proposed in this paper for low power applications. The voltage doubler integrated with DC – DC boost converter circuits were designed and simulated using MultiSIM software. The circuit was then fabricated onto a printed circuit board (PCB), using standard fabrication process. The Cockcroft Walton doubler was chosen to be implemented in this study by utilizing diode-capacitor topologies with additional RC low pass filter. The DC – DC boost converter has been designed using a CMOS step -up DC – DC switching regulators, which are suitable for low input voltage system. The achievement of this interface circuit was able to boost up the maximum voltage of 5 V for input voltage of 800 mV.</span>

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Gierczak, Miroslaw Gracjan, Jacek Wróblewski, and Andrzej Dziedzic. "The design and fabrication of electromagnetic microgenerator with integrated rectifying circuits." Microelectronics International 34, no. 3 (2017): 131–39. http://dx.doi.org/10.1108/mi-02-2017-0010.

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Purpose The paper focuses on design, fabrication and characterization of electromagnetic microgenerators with integrated rectifying circuits to convert AC output signal to DC one. The work includes research on simulation of voltage-rectifying circuits, including charge pump, realization of the experimental printed circuit board (PCB) with selected electronic circuits and the execution of the final structure with integrated rectifying circuit. Measurements were performed on these circuits. Design/methodology/approach Electromagnetic microgenerators include multipole permanent magnets secured on rotor three-phase brushless direct current (BLDC) motor and planar multilayer multiple coils. These were fabricated using low temperature co-fired ceramics (LTCC) technology. In our experiment, six rectifying circuits were simulated and tested with a structure consisting of eight layers of coils and with an outer diameter of 50 mm fabricated earlier. Findings The microgenerator with Graetz bridge generates higher output power than the modified charge pump at the same rotary speed. However, it is less stable for the distance change between the structure and the magnets than the modified charge pump, which has more constant output power in a wider range of load resistance. Originality/value The presented electronic rectifying circuits are novel for LTCC-based electromagnetic microgenerator application. The structure with integrated rectifying circuits allows generation of electrical output power larger than 100 mW at the rotor speed of about 8,000 rpm.

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Meng, Fanfan, Claire Donnelly, Luka Skoric, Aurelio Hierro-Rodriguez, Jung-wei Liao, and Amalio Fernández-Pacheco. "Fabrication of a 3D Nanomagnetic Circuit with Multi-Layered Materials for Applications in Spintronics." Micromachines 12, no. 8 (2021): 859. http://dx.doi.org/10.3390/mi12080859.

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Three-dimensional (3D) spintronic devices are attracting significant research interest due to their potential for both fundamental studies and computing applications. However, their implementations face great challenges regarding not only the fabrication of 3D nanomagnets with high quality materials, but also their integration into 2D microelectronic circuits. In this study, we developed a new fabrication process to facilitate the efficient integration of both non-planar 3D geometries and high-quality multi-layered magnetic materials to prototype 3D spintronic devices, as a first step to investigate new physical effects in such systems. Specifically, we exploited 3D nanoprinting, physical vapour deposition and lithographic techniques to realise a 3D nanomagnetic circuit based on a nanobridge geometry, coated with high quality Ta/CoFeB/Ta layers. The successful establishment of this 3D circuit was verified through magnetotransport measurements in combination with micromagnetic simulations and finite element modelling. This fabrication process provides new capabilities for the realisation of a greater variety of 3D nanomagnetic circuits, which will facilitate the understanding and exploitation of 3D spintronic systems.

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KUMAR, RANJITH, ZHIYU LIU, and VOLKAN KURSUN. "TECHNIQUE FOR ACCURATE POWER AND ENERGY MEASUREMENT WITH THE COMPUTER-AIDED DESIGN TOOLS." Journal of Circuits, Systems and Computers 17, no. 03 (2008): 399–421. http://dx.doi.org/10.1142/s0218126608004381.

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Computer-aided design (CAD) tools are frequently employed to verify the design objectives before the fabrication of an integrated circuit. An important circuit parameter that requires accurate characterization is the power consumption due to the strict constraints on the acceptable power envelope of integrated systems. Circuit simulators typically provide built-in functions to measure the power consumption. However, the accuracy of the measured power is mostly overlooked since the approximations and the methodologies used by the existing built-in power estimation tools are not well documented. The research community tends to assume that the built-in functions provide accurate power figures. This blind-trust in the CAD tools, however, may lead to gross errors in power estimation. A generic methodology to accurately measure the power and energy consumption with the circuit simulators is described in this paper. An equation to calculate the device power consumption based on the different current conduction paths in a MOSFET is presented. An expression for the total power consumption of a complex circuit is derived by explicitly considering the different circuit terminals including the inputs, the outputs, and the body-contacts. Results indicate that the power measurements with the built-in functions of widely used commercial circuit simulators can introduce significant errors in a 65 nm CMOS technology. For deeply scaled nano-CMOS circuits, a conscious power and energy measurement with the proposed explicit methodology is recommended for an accurate pre-fabrication circuit characterization.

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LIU, QINGMIN, SURAJIT SUTAR, and ALAN SEABAUGH. "TUNNEL DIODE/TRANSISTOR DIFFERENTIAL COMPARATOR." International Journal of High Speed Electronics and Systems 14, no. 03 (2004): 640–45. http://dx.doi.org/10.1142/s0129156404002600.

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A new tunnel diode/transistor circuit topology is reported, which both increases speed and reduces power in differential comparators. This circuit topology is of special interest for use in direct digital synthesis applications. The circuit topology can be extended to provide performance improvements in high speed logic and signal processing applications. The circuits are designed based on InP/GaAsSb double heterojunction bipolar transistors and AlAs/InGaAs/AlAs resonant tunneling diodes. A self-aligned and scalable fabrication approach using nitride sidewalls and chemical mechanical polishing is outlined.

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Wang, Bing, Haining Zhang, Joon Phil Choi, Seung Ki Moon, Byunghoon Lee, and Jamyeong Koo. "A Post-Treatment Method to Enhance the Property of Aerosol Jet Printed Electric Circuit on 3D Printed Substrate." Materials 13, no. 24 (2020): 5602. http://dx.doi.org/10.3390/ma13245602.

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Aerosol jet printing of electronic devices is increasingly attracting interest in recent years. However, low capability and high resistance are still limitations of the printed electronic devices. In this paper, we introduce a novel post-treatment method to achieve a high-performance electric circuit. The electric circuit was printed with aerosol jet printing method on an ULTEM substrate. The ULTEM substrate was fabricated by the Fused Deposition Modelling method. After post-treatment, the electrical resistance of the printed electric circuit was changed from 236 mΩ to 47 mΩ and the electric property was enhanced. It was found that the reduction of electric resistance was caused by surface property changes. Different surface analysis methods including scanning electron microscopy (SEM) and x-ray photoelectron spectroscopy (XPS) were used to understand the effectiveness of the proposed method. The results showed that the microsurface structure remained the same original structure before and after treatment. It was found that the surface carbon concentration was significantly increased after treatment. Detailed analysis showed that the C-C bond increased obviously after treatment. The change of electrical resistance was found to be limited to the material’s surface. After polishing, the circuit resistance was changed back to its original value. As the electric circuit is the basic element of electric devices, the proposed method enables the fabrication of high performance devices such as capacitors, strain gauge, and other sensors, which has potential applications in many areas such as industrial, aerospace, and military usage.

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Roy, Sudipta. "EnFACE: a maskless process for circuit fabrication." Circuit World 35, no. 3 (2009): 8–11. http://dx.doi.org/10.1108/03056120910979495.

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Fillion, Ray. "Embedded Actives and Its Industry Effects." International Symposium on Microelectronics 2011, no. 1 (2011): 000382–87. http://dx.doi.org/10.4071/isom-2011-tp5-paper5.

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Over the 60 plus year history of microelectronics packaging, electronic devices have been mounted onto an interconnect structure to form a microelectronics circuit. The devices could be bare chips, CSPs or packaged components such as SMT or thru-hole carriers. The interconnect structures could be circuit boards, ceramic substrates or flex circuits. This methodology has enabled a clear divide between the fabrication, assembly and test of the semiconductor device, the fabrication and test of the interconnect structure and the assembly and test of the component/substrate assembly. Over the past decade a new packaging methodology, embedded actives (chips), has been developed that changes all of these industry norms. In an embedded actives packaging approach, one or more bare or chip scale semiconductor devices are embedded within the interconnect structure. Although these approaches have significant electrical performance, size and cost benefits, the normal barriers between chip packaging, substrate fabrication and component assembly are removed. The interconnect structure is not completed prior to component embedding and the embedded component cannot be tested at packaged part level without the interconnect structure. This complicates electrical testing and makes it virtually impossible to differentiate between a defective component, a defective interconnect or a defective component to substrate contact. This paper will look at the history of embedded active developments and go into the various processes and structures being used. It will cover their electrical, reliability and size advantages and will address the revolutionary changes that the microelectronics industry must make to effectively utilize these technologies.

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Rao, S., A. J. Strojwas, J. P. Lehoczky, and M. J. Schervish. "Monitoring multistage integrated circuit fabrication processes." IEEE Transactions on Semiconductor Manufacturing 9, no. 4 (1996): 495–505. http://dx.doi.org/10.1109/66.542165.

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CACCIOLATI, O., C. JOACHIM, J. P. MARTINEZ, and F. CARCENAC. "FABRICATION OF N-ELECTRODES NANOJUNCTIONS FOR MONOMOLECULAR ELECTRONIC INTERCONNECTS." International Journal of Nanoscience 03, no. 03 (2004): 233–45. http://dx.doi.org/10.1142/s0219581x04002036.

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A new e-beam nanolithography process is presented to fabricate N-electrodes nanojunctions for the electrical interconnection of a monomolecular circuit having N input/output. The fabricated electrodes of the junction have a width below 20 nm and are buried at the SiO 2 surface. N=20 of such electrodes can be positioned on a circle of a diameter below 200 nm. An interconnection roadmap for molecular electronics is discussed to put this new process in perspective with the different possible ways of interconnecting a monomolecular circuit via atomic wires, nanotubes or metallic nanowires.

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Gutierrez, Cassie, Rudy Salas, Gustavo Hernandez, et al. "CubeSat Fabrication through Additive Manufacturing and Micro-Dispensing." International Symposium on Microelectronics 2011, no. 1 (2011): 001021–27. http://dx.doi.org/10.4071/isom-2011-tha4-paper3.

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Fabricating entire systems with both electrical and mechanical content through on-demand 3D printing is the future for high value manufacturing. In this new paradigm, conformal and complex shapes with a diversity of materials in spatial gradients can be built layer-by-layer using hybrid Additive Manufacturing (AM). A design can be conceived in Computer Aided Design (CAD) and printed on-demand. This new integrated approach enables the fabrication of sophisticated electronics in mechanical structures by avoiding the restrictions of traditional fabrication techniques, which result in stiff, two dimensional printed circuit boards (PCB) fabricated using many disparate and wasteful processes. The integration of Additive Manufacturing (AM) combined with Direct Print (DP) micro-dispensing and robotic pick-and-place for component placement can 1) provide the capability to print-on-demand fabrication, 2) enable the use of micron-resolution cavities for press fitting electronic components and 3) integrate conductive traces for electrical interconnect between components. The fabrication freedom introduced by AM techniques such as stereolithography (SL), ultrasonic consolidation (UC), and fused deposition modeling (FDM) have only recently been explored in the context of electronics integration and 3D packaging. This paper describes a process that provides a novel approach for the fabrication of stiff conformal structures with integrated electronics and describes a prototype demonstration: a volumetrically-efficient sensor and microcontroller subsystem scheduled to launch in a CubeSat designed with the CubeFlow methodology.

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Mohd Hanif, Siti Hashimah, Walter Charles Primus, Abdul H. Shaari, and Hassan Jumiah. "Fabrication and Electrical Properties of Strontium Doped Lanthanum Manganite Titanite Oxide." Advanced Materials Research 1107 (June 2015): 278–82. http://dx.doi.org/10.4028/www.scientific.net/amr.1107.278.

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Composition of La0.7Sr0.3Mn0.4Ti0.6O3has been prepared using solid state reaction method where its crystal structure and electrical properties has been analyzed using X-ray Diffractometer (XRD) and Low frequency LCR meter, respectively. The result, shows that the sample has cubic perovskite structure with the existence of impurities phase. In electrical measurement, the frequency dependence of complex capacitance plot shows the sample have strong dispersion at lower frequency and the impedance plane plot shows a semicircle due to the grain effect. The sample electrical properties are also represented in equivalent electrical circuit which consists of a quasi d.c and in parallel with conductance.

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Kang, Byung Ju, Chang Kyu Lee, and Je Hoon Oh. "All-inkjet-printed electrical components and circuit fabrication on a plastic substrate." Microelectronic Engineering 97 (September 2012): 251–54. http://dx.doi.org/10.1016/j.mee.2012.03.032.

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Cruz, Carlos Augusto de Moraes, Carlos Alberto Dos Reis Filho, Davies William de Lima Monteiro, Thiago Brito Bezerra, and Luciano Lourenço Furtado Da Silva. "Gate-Oxide Voltage Overstress Treatment in Charge Pump Circuits for Standard CMOS Technologies." Journal of Integrated Circuits and Systems 10, no. 2 (2015): 65–73. http://dx.doi.org/10.29292/jics.v10i2.407.

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Charge pump circuits operating at voltage levels above that of the power supply usually suffer from gate-oxide voltage overstress. Such reliability problem has become a concern especially as the gate-oxide thickness is scaled down. Devising charge pump circuits that avoid such a problem is far simpler for CMOS triple-well technologies than for standard technologies, nevertheless fabrication costs are higher. Two approaches are usually applied to eliminate gate-oxide overstress in charge pumps designed for standard CMOS technologies, the first is multiple phase control, and the second is dual phase control with doubled voltage swing. The latter has been shown to produce more power efficient circuits, however solutions using such approach still present gate-oxide overstress in some transistors. In this work, it is shown that a slight change in some of the circuit connections is able to ultimately overcome the problem. Moreover, experimental results have shown that such circuit topology can reach a voltage multiplication efficiency of about 98 %.

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Shamkhalichenar, Hamed, Collin J. Bueche, and Jin-Woo Choi. "Printed Circuit Board (PCB) Technology for Electrochemical Sensors and Sensing Platforms." Biosensors 10, no. 11 (2020): 159. http://dx.doi.org/10.3390/bios10110159.

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The development of various biosensors has revolutionized the healthcare industry by providing rapid and reliable detection capability. Printed circuit board (PCB) technology has a well-established industry widely available around the world. In addition to electronics, this technology has been utilized to fabricate electrical parts, including electrodes for different biological and chemical sensors. High reproducibility achieved through long-lasting standard processes and low-cost resulting from an abundance of competitive manufacturing services makes this fabrication method a prime candidate for patterning electrodes and electrical parts of biosensors. The adoption of this approach in the fabrication of sensing platforms facilitates the integration of electronics and microfluidics with biosensors. In this review paper, the underlying principles and advances of printed board circuit technology are discussed. In addition, an overview of recent advancements in the development of PCB-based biosensors is provided. Finally, the challenges and outlook of PCB-based sensors are elaborated.

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Murduck, J. M., A. Kirschenbaum, A. Mayer, V. Morales, and C. Lavoie. "High-performance Nb integrated circuit process fabrication." IEEE Transactions on Appiled Superconductivity 13, no. 2 (2003): 87–90. http://dx.doi.org/10.1109/tasc.2003.813651.

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Deng, Yiping, Lu Liao, Chengguang Wu, et al. "A New Type of Self Driven Door Handle." International Journal of Software Science and Computational Intelligence 9, no. 4 (2017): 67–79. http://dx.doi.org/10.4018/ijssci.2017100105.

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In this article, authors report on a smart door handle that can efficiently collect and utilize ambient energy to power itself. A Triboelectric Nanogenerator which presents characteristics including easy fabrication, small size and light weight is embedded in the door. When begin to turn the handle, the TENG can convert the mechanical energy into the electrical energy, and the power can up to 0.023W. At the same time, the internal circuit will send a single to identify the action of opening the door, and then the wireless receiver will make appropriate responses after receiving the signal. In this article, the authors designed a wireless transmission circuit to ensure that the transmitter and receiver can communicate in real time. Due to the TENG's output is AC signal which can't power the device directly, so the power management circuit was designed to process the signal. To analyze and compare the output signal, the authors designed two power management circuits. Both the circuits can convert the AC signal into the DC signal, the voltage can up to 5V and the current can up to 3mA.

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Clingenpeel, Timothy, Arian Rahimi, Seahee Hwangbo, Yong-Kyu Yoon, and Aric Shorey. "Fabrication and characterization of advanced through glass via interconnects." International Symposium on Microelectronics 2016, no. 1 (2016): 000288–92. http://dx.doi.org/10.4071/isom-2016-wp23.

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Abstract This work presents the fabrication process, electrical characteristics, and circuit model of through glass via (TGV) structures consisting of TGV holes with each diameter of 100 μm and different conductors including copper and composite in the frequency range of 300 kHz to 20 GHz. The Cu/NiFe superlattice metaconductors in combination with high-quality glass (Corning SGW3) are intended to reduce radio-frequency losses especially in 10 GHz and above for next generation communication applications such as 5G communications. The measured results of the copper structure are compared to simulated results. Superlattice metaconductor results will be presented. Based on the simulation and measurement results, a circuit model is demonstrated.

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Goosey, M. T. "New Chemistries for Advanced Printed Circuit Board Fabrication." Circuit World 18, no. 4 (1992): 55–56. http://dx.doi.org/10.1108/eb046179.

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RAMSEY, B. J., P. S. A. EVANS, and D. HARRISON. "A NOVEL CIRCUIT FABRICATION TECHNIQUE USING OFFSET LITHOGRAPHY." Journal of Electronics Manufacturing 07, no. 01 (1997): 63–67. http://dx.doi.org/10.1142/s0960313197000075.

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Suo, Chun Guang, Wen Bin Zhang, and Shi Su. "Fabrication of Micro DMFC Stack Using MEMS Technology." Advanced Materials Research 690-693 (May 2013): 985–88. http://dx.doi.org/10.4028/www.scientific.net/amr.690-693.985.

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This paper presents two kinds of direct methanol fuel cell (μDMFC) stack in planar array. The silicon-based DMFC stack is designed in a flip-flop configuration using MEMS technology, and the stainless steel stack is fabricated using stamping technology. Compared to stainless steel stack, the flip-flop silicon-based stack may reduce the connection space and lower the contact resistance between the membrane electrode assembly and the plates. The electrical characterization of this μDMFC stack was carried out by tests. The experimental results showed the prototype was able to generate an open-circuit voltage of 2.7V and a maximum power density of 2.2mW/cm2 at room temperature, demonstrating the feasibility of this new configuration. Application of μDMFC stacks as portable power sources were demonstrated using small electric devices powered by this stack.

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Weikle, R. M., T. W. Crowe, and E. L. Kollberg. "Multiplier and Harmonic Generator Technologies for Terahertz Applications." International Journal of High Speed Electronics and Systems 13, no. 02 (2003): 429–56. http://dx.doi.org/10.1142/s012915640300179x.

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Harmonic generation based on frequency multipliers has proven to be the most successful and widely used solid-state technology for generating power at submillimeter wavelengths. Over the last several years, the development of new device technologies, implementation of innovative circuits, and application of advanced integrated-circuit processing techniques to frequency multiplier design have resulted in unprecedented levels of performance throughout the submillimeter-wave frequency band. This paper reviews the technological innovations, device options, circuit architectures, and fabrication technologies that have made harmonic generation such a successful approach to source development in the submillimeter spectrum.

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Pyatkov, Felix, Svetlana Khasminskaya, Vadim Kovalyuk, et al. "Sub-nanosecond light-pulse generation with waveguide-coupled carbon nanotube transducers." Beilstein Journal of Nanotechnology 8 (January 5, 2017): 38–44. http://dx.doi.org/10.3762/bjnano.8.5.

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Carbon nanotubes (CNTs) have recently been integrated into optical waveguides and operated as electrically-driven light emitters under constant electrical bias. Such devices are of interest for the conversion of fast electrical signals into optical ones within a nanophotonic circuit. Here, we demonstrate that waveguide-integrated single-walled CNTs are promising high-speed transducers for light-pulse generation in the gigahertz range. Using a scalable fabrication approach we realize hybrid CNT-based nanophotonic devices, which generate optical pulse trains in the range from 200 kHz to 2 GHz with decay times below 80 ps. Our results illustrate the potential of CNTs for hybrid optoelectronic systems and nanoscale on-chip light sources.

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Satti, Afraiz Tariq, Jinsoo Park, Jangwoong Park, Hansang Kim, and Sungbo Cho. "Fabrication of Parylene-Coated Microneedle Array Electrode for Wearable ECG Device." Sensors 20, no. 18 (2020): 5183. http://dx.doi.org/10.3390/s20185183.

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Microneedle array electrodes (MNE) showed immense potential for the sensitive monitoring of the bioelectric signals by penetrating the stratum corneum with high electrical impedance. In this paper, we introduce a rigid parylene coated microneedle electrode array and portable electrocardiography (ECG) circuit for monitoring of ECG reducing the motion artifacts. The developed MNE showed stability and durability for dynamic and long-term ECG monitoring in comparison to the typical silver-silver chloride (Ag/AgCl) wet electrodes. The microneedles showed no mechanical failure under the compression force up-to 16 N, but successful penetration of skin tissue with a low insertion force of 5 N. The electrical characteristics of the fabricated MNE were characterized by impedance spectroscopy with equivalent circuit model. The designed wearable wireless ECG monitoring device with MNE proved feasibility of the ECG recording which reduces the noise of movement artifacts during dynamic behaviors.

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Cresswell, Michael W., Jeffry J. Sniegowski, Rathindra N. Ghoshtagore, et al. "Recent Developments in Electrical Linewidth and Overlay Metrology for Integrated Circuit Fabrication Processes." Japanese Journal of Applied Physics 35, Part 1, No. 12B (1996): 6597–609. http://dx.doi.org/10.1143/jjap.35.6597.

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Shukla, Naman, Dharamlal Prajapati, and Sanjay Tiwari. "Investigation on Design and Device Modeling of High Performance CH3NH3PbI3-xClx Perovskite Solar Cells." Journal of Ravishankar University (PART-B) 34, no. 1 (2021): 58–63. http://dx.doi.org/10.52228/jrub.2021-34-1-8.

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Perovskite solar cells fabricated with inexpensive and simple technology exhibits high efficiency has witnessed worldwide boom in research. The optimization of solar cell can be done through modeling and simulation. The optical and electrical modeling are the ways to optimize different parameter such as thickness, defect density, doping density and material selection for fabricating stable and highly efficient perovskite solar cells. In this research work, electrical modeling of solar cell is done throughSolar Cell Capacitance Simulator(SCAPS-1D).The architecture of the solar cell is n-i-p device structure. CH3NH3PbI3-xClx acts as light absorber active layer, TiO2 as electron transport layer and Spiro-OMeTADas hole transport layer with device structure FTO/ TiO2/ CH3NH3PbI3-xClx/ Spiro-OMeTAD/Au. The open circuit voltage Voc, short circuit current density Isc, fill factor and power conversion efficiency are 1.28 V, 21.63 mA/cm2, 0.78 and 21.53% respectively. The result showed that the optimize parameter can be applied for fabrication of the solar cell experimentally. Various metal contact materials of the anodeare also studied and analyzed.

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Lee, Changyeop, Gyuseong Cho, Troy Unruh, Seop Hur, and Inyong Kwon. "Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad." Sensors 20, no. 10 (2020): 2765. http://dx.doi.org/10.3390/s20102765.

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According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

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Tatu, Serioja Ovidiu, and Emilia Moldovan. "Millimeter Wave Multi-Port Interferometric Radar Sensors: Evolution of Fabrication and Characterization Technologies." Sensors 20, no. 19 (2020): 5477. http://dx.doi.org/10.3390/s20195477.

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Recent advances in millimeter wave technologies, both in component and system design, in line with important size and cost reductions, have opened up new applications in ultra-high-speed wireless communications, radar and imaging sensors. The paper presents the evolution of millimeter wave circuit and modules fabrication and characterization technologies in the past decades. Novel planar low-cost fabrication technologies have been successfully developed in this period. In combination with the standard rectangular wave-guide technology, these offer great opportunities for prototyping and testing of future millimeter wave transceivers or front-ends, which integrate antenna arrays, down-converters, modulators, amplifiers, etc., in a compact fixture. The paper uses, as a suggestive example, the evolution of the multi-port interferometric front-ends implementation from millimeter wave bulky components and systems to miniaturized and high-efficient ones. Circuit and system designs are carefully done to avoid (as much as possible) complicated calibration methods or difficult post-processing of baseband data. This requires an increased effort in design and fabrication, but it allows miniaturization, low-power consumption, while keeping very good overall performances. Useful and straightforward laboratory characterization techniques of circuits and systems are described in detail.

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Spry, David J., Philip G. Neudeck, Liang Yu Chen, et al. "Fabrication and Testing of 6H-SiC JFETs for Prolonged 500 °C Operation in Air Ambient." Materials Science Forum 600-603 (September 2008): 1079–82. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1079.

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This paper reports on the fabrication and testing of 6H-SiC junction field effect transistors (JFETs) and a simple differential amplifier integrated circuit that have demonstrated 2000 hours of electrical operation at 500 °C without degradation. The high-temperature ohmic contacts, dielectric passivation, and packaging technology that enabled such 500 °C durability are briefly described. Key JFET parameters of threshold voltage, on-state resistance, transconductance, and on-state current, as well as the gain of the differential amplifier integrated circuit, exhibited less than 7% change over the first 2000 hours of 500 °C operational testing.

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Sharma, Vijay Kumar. "Design of Low Leakage PVT Variations Aware CMOS Bootstrapped Driver Circuit." Journal of Circuits, Systems and Computers 26, no. 09 (2017): 1750137. http://dx.doi.org/10.1142/s0218126617501377.

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This paper describes a novel complementary metal oxide semiconductor (CMOS) bootstrapped driver circuit for driving large resistive capacitive (RC) loads. The proposed bootstrapped driver reduces the leakage as well as process, voltage and temperature (PVT) variations from the boosted nodes with higher switching speed. Very large scale integration (VLSI) designers need boosted output for the logic circuits which are operating in ultra-deep submicron regime under widespread use of low voltage. Proposed CMOS bootstrapped driver circuit is easy in design; built with minimum number of transistors and have high boosting efficiency with sharp output performance. Comparative evaluations with existing bootstrapped driver circuits are reported. Simulation results are derived by HSPICE tool with predictive technology model (PTM) bulk CMOS process fabrication at 32 nm technology node. The ability of large leakage reduction makes this driver superior as compared to active drivers. An average of 96.97% leakage current is saved at nominal ultra-low voltage of 0.15 V. Monte-Carlo analysis indicates that the proposed bootstrapped driver has less sensitivity of PVT variations. The power consumption and delay sensitivities are reduced by 10 × and 4.12 × as compared to conventional circuit.

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Metra, Cecilia, Michele Favalli, and Bruno Riccò. "Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits." VLSI Design 11, no. 1 (2000): 23–34. http://dx.doi.org/10.1155/2000/42016.

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In this paper we propose signal coding and CMOS gates that are suitable to self-checking circuits with combinational functional blocks implemented also by next generation, very deep submicron technology. In particular, our functional blocks satisfy the Strongly Fault-Secure property with respect to a wide set of possible, internal faults including not only conventional stuck-ats, but also transistor stuck-ons, transistor stuck-opens, resistive bridgings, delays, crosstalks and transient faults, that are very likely to affect next generation ICs. Compared to alternative, existing solutions, that proposed here does not imply any critical constraint on the circuit electrical parameters. Therefore, it is suitable to be adopted to design very deep submicron self-checking circuits which, compared to todays' circuits, will present significantly increased sensitivity to parameter variations occurring during fabrication.

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Park, Steve, Gaurav Giri, Leo Shaw, et al. "Large-area formation of self-aligned crystalline domains of organic semiconductors on transistor channels using CONNECT." Proceedings of the National Academy of Sciences 112, no. 18 (2015): 5561–66. http://dx.doi.org/10.1073/pnas.1419771112.

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The electronic properties of solution-processable small-molecule organic semiconductors (OSCs) have rapidly improved in recent years, rendering them highly promising for various low-cost large-area electronic applications. However, practical applications of organic electronics require patterned and precisely registered OSC films within the transistor channel region with uniform electrical properties over a large area, a task that remains a significant challenge. Here, we present a technique termed “controlled OSC nucleation and extension for circuits” (CONNECT), which uses differential surface energy and solution shearing to simultaneously generate patterned and precisely registered OSC thin films within the channel region and with aligned crystalline domains, resulting in low device-to-device variability. We have fabricated transistor density as high as 840 dpi, with a yield of 99%. We have successfully built various logic gates and a 2-bit half-adder circuit, demonstrating the practical applicability of our technique for large-scale circuit fabrication.

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AGARWAL, BIPUL, RAJASEKHAR PULLELA, UDDALAK BHATTACHARYA, et al. "ULTRAHIGH fmax AlInAs/GaInAs TRANSFERRED-SUBSTRATE HETEROJUNCTION BIPOLAR TRANSISTORS FOR INTEGRATED CIRCUITS APPLICATIONS." International Journal of High Speed Electronics and Systems 09, no. 02 (1998): 643–70. http://dx.doi.org/10.1142/s0129156498000270.

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Transferred-substrate heterojunction bipolar transistors (HBTs) have demonstrated very high bandwidths and are potential candidates for very high speed integrated circuit (IC) applications. The transferred-substrate process permits fabrication of narrow and aligned emitter-base and collector-base junctions, reducing the collector-base capacitance and increasing the device f max . Unlike conventional double-mesa HBTs, transferred-substrate HBTs can be scaled to submicron dimensions with a consequent increase in bandwidth. This paper introduces the concept of transferred-substrate HBTs. Fabrication process in the AlInAs/GaInAs material system is presented, followed by DC and RF performance. A demonstration IC is shown along with some integrated circuits in development.

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Kannan Megalingam, Rajesh, Shree Rajesh Raagul Vadivel, Sreekumar S, Swathi Sekhar, Thejus R Nair, and Midhun RR. "Design and Implementation of CNC Milling Bot for Milled Circuit Board Fabrication." International Journal of Engineering & Technology 7, no. 3.12 (2018): 1205. http://dx.doi.org/10.14419/ijet.v7i3.12.17838.

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This research paper presents an alternative way to fabricate a Milled Circuit Board (MCB) with the help of a Computer Numerical Controlled (CNC) milling robot. Printed Circuit Boards (PCB) are one of the most widely used control modules in electrical and electronic industries. In this research paper we propose a computer controlled milling machine which can be used for quick fabrication of double layered PCBs called MCB where a user wants to test the circuit without the need to wait for the conventional PCB fabrication. The end effector of the CNC milling machine has the provision to move in 3 axes-x, y and z in accordance with the input received from the controller. DipTrace, an EDA/CAD software is used for creating the schematic diagram for the milled circuit boards. The design to be engraved on the copper clad board is uploaded to a software called CopperCam, where it can be converted to G-code files after making the necessary modifications. These G-code files are then uploaded to the CNC machine using the software Universal G-code Sender, thus enabling the microcontroller to direct the rotation of motors and coordinate the movements of the end effector so as to engrave the board design on to a copper clad.

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Vygranenko, Yuri, Miguel Fernandes, Paula Louro, et al. "Amorphous Silicon Photovoltaic Modules on Flexible Plastic Substrates." MRS Advances 1, no. 43 (2016): 2923–28. http://dx.doi.org/10.1557/adv.2016.430.

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ABSTRACTThis paper reports on a monolithic 10 cm × 10 cm area PV module integrating an array of 72 a-Si:H n-i-p cells on a 100 μm thick polyethylene-naphtalate substrate. The n-i-p stack is deposited using a PECVD system at 150 °C substrate temperature. The design optimization and device performance analysis are performed using a two-dimensional distributed circuit model of the photovoltaic cell. The circuit simulator SPICE is used to calculate current and potential distributions in a network of sub-cell circuits, and also to map Joule losses in the front TCO electrode and the metal grid. Experimental results show that the shunt leakage is one of the factors reducing the device performance. Current-voltage characteristics of individual a-Si:H p-i-n cells were analyzed to estimate a variation of shunt resistances. Using the LBIC technique, the presence of multiple shunts in the n-i-p cell was detected. To understand the nature of electrical shunts, the change in the surface roughness of all device layers was analyzed throughout fabrication process. It is found that surface defects in plastic foils, which are thermally induced during the device fabrication, form microscopic pinholes filled with highly conductive top electrode material.

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Ceponis, Badokas, Deveikis, et al. "Evolution of Scintillation and Electrical Characteristics of AlGaN Double-Response Sensors During Proton Irradiation." Sensors 19, no. 15 (2019): 3388. http://dx.doi.org/10.3390/s19153388.

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Wide bandgap AlGaN is one of the most promising materials for the fabrication of radiation hard, double-response particle detectors for future collider facilities. However, the formation of defects during growth and fabrication of AlGaN-based devices is unavoidable. Furthermore, radiation defects are formed in detector structures during operation at extreme conditions. In this work, study of evolution of the proton-induced luminescence spectra and short-circuit current has been simultaneously performed during 1.6 MeV proton irradiation. GaN and AlGaN (with various Al concentrations) epi-layers grown by metalorganic chemical vapour deposition technique and Schottky diode structures have been examined. Variations of spectral and electrical parameters could be applied for the remote dosimetry of large hadron fluences.

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Kim, Hyunho. "Passive device embedded substrate for application of RF module." Circuit World 42, no. 2 (2016): 84–88. http://dx.doi.org/10.1108/cw-07-2015-0033.

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Purpose The purpose of this study is to form fabrication and electrical characteristics of passive device embedded substrate that is embedded chip bead inductor and chip capacitor inside substrate for the application of radio frequency (RF) modules. Design/methodology/approach Passive device embedded substrate was fabricated using embedding process that consists of lamination process, laser drilling at the electrode Cu pads of passive components, electro-less Cu plating formation process such as photolithography, electrolytic Cu plating and etching. Impedance and capacitance characteristics of the fabricated passive device embedded substrate were evaluated. Findings By checking what embedded components are placed in the appropriate place using failure analysis via connection performance between copper plane and embedded components was verified. For measuring electrical characteristics of the fabricated passive device embedded substrate, the evaluation was done using test methods like continuity test for checking interconnections which are not connected to any embedded components and in-circuit test for checking interconnections which are connected to any embedded component. From in-circuit testing for embedding passive components with series and parallel circuits, the authors verified how to test passive device embedded substrate by using capacitance and impedance measurement with the comparison of measured results between good samples and bad samples. Originality/value Ultra miniaturized and low-profile mobile products are driving the need for embedded passive component integration technologies using a novel manufacturing-compatible organic substrate and interconnect technologies. Fabrication and test methods for passive device embedded substrate described in this paper are expected to lead to be developed to make quality measurable for the application of RF modules.

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Rho, Byung Sup, Woo-Jin Lee, Jung Woon Lim, Ki Young Jung, Kyung Soon Cha, and Sung Hwan Hwang. "Fabrication and Reliability of Rigid-Flexible Optical Electrical Printed Circuit Board for Mobile Devices." IEEE Photonics Technology Letters 20, no. 12 (2008): 964–66. http://dx.doi.org/10.1109/lpt.2008.922918.

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BROCK, DARREN K. "RSFQ TECHNOLOGY: CIRCUITS AND SYSTEMS." International Journal of High Speed Electronics and Systems 11, no. 01 (2001): 307–62. http://dx.doi.org/10.1142/s0129156401000861.

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Rapid Single-Flux-Quantum (RSFQ) logic is a superconductor IC technology that, with only a modest number of researchers worldwide, has produced some of the world's highest performance digital and mixed-signal circuits. This achievement is due, in part, to a constellation of characteristics that manifest themselves at the circuit level – namely, high-speed digital logic at low-power, ideal interconnects, quantum accuracy, scalability, and simplicity of fabrication. A necessary key to translating these advantages to the system-level involves understanding the I/O, synchronization, and packaging issues associated with a cryogenic technology. The objective of this paper is to review the status of current RSFQ circuit-level infrastructure components and their potential impact on system-level applications.

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Iwai, Hiroshi, Kuniyuki Kakushima, and Hei Wong. "CHALLENGES FOR FUTURE SEMICONDUCTOR MANUFACTURING." International Journal of High Speed Electronics and Systems 16, no. 01 (2006): 43–81. http://dx.doi.org/10.1142/s0129156406003539.

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The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In this paper, future semiconductor manufacturing challenges for nano-sized devices and ultra large scale circuits are analyzed. The portraits of future integration circuit fabrication and the distribution of semiconductor manufacturing centers in next decade are sketched. The possible limits for the scaling will also be elaborated.

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Baumann, F. H., D. L. Chopp, T. Díaz de la Rubia, et al. "Multiscale Modeling of Thin-Film Deposition: Applications to Si Device Processing." MRS Bulletin 26, no. 3 (2001): 182–89. http://dx.doi.org/10.1557/mrs2001.40.

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Metallization is the back end of the integrated-circuit (IC) fabrication process where the transistor interconnections are formed. Figure 1 shows the metallized part of a static random-access memory chip. Metal lines for electrical connections (Al and Cu) in Si devices are deposited as blanket films and then etched or polished away to define the conducting lines.

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Geiling, Thomas, Lothar Dressler, Tilo Welker, and Martin Hoffmann. "Fine Dust Measurement with Electrical Fields – Concept of a Hybrid Particle Detector." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, CICMT (2013): 000131–36. http://dx.doi.org/10.4071/cicmt-2013-wp15.

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Fine dust measurements are only conducted at few locations in our daily environment, although it is getting clearer that fine dust poses a high risk on human health. A reason for this deficit is the lack of suitable measurement systems, especially for indoor environments. Of special interest are particles with critical dimension smaller than 10 μm. They constitute the highest risk to human health as they are not filtered out by the respiratory system. By miniaturizing particle detector concepts point-of-care applications are rendered possible and production costs can be greatly reduced with microsystem fabrication technologies. The pursued detector principle is based on the interaction of single particles with electric fields. The field is created within a micro-aperture machined in a silicon substrate. Two electrodes are deposited near the aperture and form a capacitive setup. An air flow drives particles through this aperture one by one. Passing particles distort the electric field, and their presence is detected by an impedance measurement. The changes induced by a single particle are tiny and require precise measurement circuits. Our contribution presents the design of a hybrid particle detector: The sensing element consists of an array of these micro apertures with lead-outs to a measurement circuit. This element is mounted on a LTCC module, which provides all necessary electrical and fluidic functions to operate the particle detector within a larger sensor platform. Sensitive parts of the measurement circuit are mounted on the LTCC module and positioned closely to the sensing elements. Microfluidic channels guide the air flow from the sensor platform to the micro-aperture and back. Therefore, the hybrid module is both: a ceramic interconnect and a ceramic microsystem.

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Nathan, Arokia. "Microsensors for physical signals: Principles, device design, and fabrication technologies." Canadian Journal of Physics 74, S1 (1996): 115–30. http://dx.doi.org/10.1139/p96-844.

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Microsensors are miniaturized devices, fabricated using silicon-based and related technologies, that convert input physical and chemical signals into an output electrical signal. The key driving force in microsensor research has been the integrated circuit (IC) and micromachining technologies. The latter, in particular, is fueling tremendous activity in micro-electromechanical systems (MEMS). In terms of technology and design tools, MEMS is at a stage where microelectronics was 30 years ago and is expected to evolve at an equally rapid pace. The synergy between the IC, micromachining, and integrated photonics technologies can potentially spawn a new generation of microsystems that will feature a unique marriage of microsensor, signal-conditioning and -processing circuitry, micromechanics, and optomechanics possibly on a single chip. In this paper, the physical transduction principles, materials considerations, process-fabrication technologies, and computer-aided-design (CAD) tools will be reviewed along with pertinent examples drawn from our microsensor research activity at the Microelectronics Laboratory, University of Waterloo.

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Spry, David J., Philip G. Neudeck, Liang-Yu Chen, et al. "Processing and Characterization of Thousand-Hour 500 °C Durable 4H-SiC JFET Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (2016): 000249–56. http://dx.doi.org/10.4071/2016-hitec-249.

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Abstract This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 °C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over ~ 1-μm scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 °C operational testing. These results advance the technology foundation for realizing long-term durable 500 °C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

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