Dissertations / Theses on the topic 'Electrical Circuits'
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Senthinathan, Ramesh 1961. "ELECTRICAL CHARACTERISTICS OF INTEGRATED CIRCUIT PACKAGES." Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/276425.
Full textMadhyastha, Sadhana. "Design of circuit breakers for large area CMOS VLSI circuits." Thesis, McGill University, 1989. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=59551.
Full textQazi, Masood. "Circuit design for embedded memory in low-power integrated circuits." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/75645.
Full textCataloged from PDF version of thesis.
Includes bibliographical references (p. 141-152).
This thesis explores the challenges for integrating embedded static random access memory (SRAM) and non-volatile memory-based on ferroelectric capacitor technology-into lowpower integrated circuits. First considered is the impact of process variation in deep-submicron technologies on SRAM, which must exhibit higher density and performance at increased levels of integration with every new semiconductor generation. Techniques to speed up the statistical analysis of physical memory designs by a factor of 100 to 10,000 relative to the conventional Monte Carlo Method are developed. The proposed methods build upon the Importance Sampling simulation algorithm and efficiently explore the sample space of transistor parameter fluctuation. Process variation in SRAM at low-voltage is further investigated experimentally with a 512kb 8T SRAM test chip in 45nm SOI CMOS technology. For active operation, an AC coupled sense amplifier and regenerative global bitline scheme are designed to operate at the limit of on current and off current separation on a single-ended SRAM bitline. The SRAM operates from 1.2 V down to 0.57 V with access times from 400ps to 3.4ns. For standby power, a data retention voltage sensor predicts the mismatch-limited minimum supply voltage without corrupting the contents of the memory. The leakage power of SRAM forces the chip designer to seek non-volatile memory in applications such as portable electronics that retain significant quantities of data over long durations. In this scenario, the energy cost of accessing data must be minimized. This thesis presents a ferroelectric random access memory (FRAM) prototype that addresses the challenges of sensing diminishingly small charge under conditions favorable to low access energy with a time-to-digital sensing scheme. The 1 Mb IT1C FRAM fabricated in 130 nm CMOS operates from 1.5 V to 1.0 V with corresponding access energy from 19.2 pJ to 9.8 pJ per bit. Finally, the computational state of sequential elements interspersed in CMOS logic, also restricts the ability to power gate. To enable simple and fast turn-on, ferroelectric capacitors are integrated into the design of a standard cell register, whose non-volatile operation is made compatible with the digital design flow. A test-case circuit containing ferroelectric registers exhibits non-volatile operation and consumes less than 1.3 pJ per bit of state information and less than 10 clock cycles to save or restore with no minimum standby power requirement in-between active periods.
by Masood Qazi.
Ph.D.
Kapur, Kishen Narain. "Mechanical and electrical characterization of IC leads during fatigue cycling." Diss., Online access via UMI:, 2009.
Find full textIncludes bibliographical references.
Ghazizadeh, Ali. "Optimum mounting of electronic circuit boards for components and circuits survivability." Thesis, University of Ottawa (Canada), 1994. http://hdl.handle.net/10393/6936.
Full textBakir, Muhannad S. "Sea of Leads electrical-optical polymer pillar chip I/O interconnections for gigascale integration." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04082004-180010/unrestricted/bakir%5Fmuhannad%5Fs%5F200312%5Fphd.pdf.
Full textYazghi, Najlae. "Interactive E-learning and Problem for Electrical Circuits." Honors in the Major Thesis, University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETH/id/1015.
Full textBachelors
Engineering and Computer Science
Electrical Engineering
Tronko, V. D., M. O. Chuzha, В. Д. Тронько, and М. О. Чужа. "Measuring current in electrical circuits using a polarimeter." Thesis, National aviation university, 2021. https://er.nau.edu.ua/handle/NAU/50502.
Full textВ представленій роботі запропоновано оптичний пристрій для вимірювання струму. Він складається з поляриметра, індикатора та вхідного пристрою. В основу його роботи покладено функціональна залежність зміни параметрів поляризованого світла в поляриметрі від значень струму, що вимірюються. Запропонований вимірювач струму дає можливість зменшити габарити та масу конструкції, а також підвищити точність вимірювань.
Soong, Chia-Wei. "ELECTRICAL CHARACTERIZATION OF SiC JFET-BASED INTEGRATED CIRCUITS." Case Western Reserve University School of Graduate Studies / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=case1386674317.
Full textWong, Calvin J. H. "Neural circuits controlling electrical communication in gymnotiform fish /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 1997. http://wwwlib.umi.com/cr/ucsd/fullcit?p9735272.
Full textDoyle, A. J. "Devices for radio frequency interference limitation in electrical circuits." Thesis, University of Oxford, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.298270.
Full textCheng, Leong Ching. "Ferroelectric microwave circuits." Thesis, University of Birmingham, 2009. http://etheses.bham.ac.uk//id/eprint/6578/.
Full textWatts, Michael Robert 1974. "Polarization independent microphotonic circuits." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/33929.
Full textIncludes bibliographical references (p. 165-170).
Microphotonic circuits have been proposed for applications ranging from optical switching and routing to optical logic circuits. However many applications require microphotonic circuits to be polarization independent, a requirement that is difficult to achieve with the high index contrast waveguides needed to form microphotonic devices. Chief among these microphotonic circuits is the optical add/drop multiplexer which requires polarization independence to mate to the standard single-mode fiber forming today's optical networks. Herein, we present the results of an effort to circumvent the polarization dependence of a microphotonic add/drop multiplexer with an integrated polarization diversity scheme. Rather than attempt to overcome the polarization dependence of the microphotonic devices in the circuit directly, the arbitrary polarization emanating from the fiber is split into orthogonal components, one of which is rotated to enable a single on-chip polarization. The outputs are passed through identical sets of devices and recombined at the output through the reverse process.
(cont.) While at the time of this publication the full polarization diversity scheme has yet to be implemented, the sub-components have demonstrated best-in-class performance, leaving integration as the remaining task. We present the results of a significant effort to design integrated polarization rotators, splitters, and splitter-rotators needed to implement the integrated polarization diversity scheme. Rigorous electromagnetic simulations were used to design these devices along with the microring-resonator based filters used to form the optical add/drop multiplexer microphotonic circuit. These device designs were passed onto fabrication, and the fabricated devices were characterized and the results compared to theoretical predictions. The integrated polarization rotators and splitters demonstrated broadband, low loss, and low cross-talk performance while the integrated polarization splitter-rotators demonstrated equally impressive performance and represent the first demonstrations of a device of this kind. Similarly impressive performance was exhibited by the microring-resonator filters which achieved the deepest through port extinction and largest free-spectral-range of a functioning high order microring-resonator filter.
by Michael Robert Watts.
Ph.D.
Christoffersen, Carlos Enrique. "Global Modeling of Nonlinear Microwave Circuits." NCSU, 2000. http://www.lib.ncsu.edu/theses/available/etd-20001206-175435.
Full textA global modeling concept for modeling microwave circuits isdescribed. This concept allows the modeling of electromagnetic (EM)and thermal effects to be included in the simulation of electroniccircuits, by viewing EM and thermal subsystems as subcircuits. Then,circuit analysis techniques are developed from a general statevariable reduction formulation. This general formulation, based on thestate variables of the nonlinear devices, allows the analysis of largemicrowave circuits because it reduces the size of the nonlinear systemof equations to be solved. One of the derived analysis techniques isbased on convolution and therefore provides modeling offrequency-defined network elements not present in conventional circuitsimulators. Another analysis technique based on wavelets that wouldenable the multiresolution analysis of circuits is investigated. Also,a reduced state variable formulation using conventional time marchingschemes is developed. It is shown that this can achieve more than anorder of magnitude improvement in simulation speed compared to that oftraditional circuit simulation methods. All these developments areimplemented in a circuit simulator program, called Transim. Thisprogram provides unprecedented flexibility for the addition of newdevice models or circuit analysis algorithms. Transim supports thelocal reference concept, which is fundamental to the analysis ofspatially distributed circuits and also to simultaneousthermal-electrical simulations. Transim is applied to the transientsimulation of a 47-section nonlinear transmission line consideringfrequency dependent attenuation for the first time and the transientsimulation, also for the first time, of two quasi-optical poweramplifier arrays.
Wornle, Frank. "An investigation into non-linear phenomena in electrical circuits." Thesis, Glasgow Caledonian University, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.395794.
Full textKhalid, Ahmed Usman. "FPGA emulation of quantum circuits." Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=98979.
Full textLuck, James Leslie. "The application of the GaAs MISFET in dynamic electrical circuits." Thesis, King's College London (University of London), 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.243455.
Full textKuznetsov, Eugene. "Trust in analog : analog circuit techniques for reducing the risk of malicious circuits and software." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/66431.
Full textCataloged from PDF version of thesis.
Includes bibliographical references (p. 47).
Malicious circuits and software present a significant security risk, especially in control applications. This work is concerned with increasing the trustworthiness of control circuitry by reducing its complexity. The security benefits of substituting analog control techniques in place of digital control are analyzed, and both discrete and integrated circuit designs are demonstrated.
by Eugene Kuznetsov.
M.Eng.
Spencer, Matthew Edmund. "Design Considerations for Nano-Electromechanical Relay Circuits." Thesis, University of California, Berkeley, 2015. http://pqdtopen.proquest.com/#viewpdf?dispub=3733438.
Full textComplementary metal oxide semiconductor (CMOS) technology has a minimum energy per operation, and that limitation is one of the myriad hurdles CMOS faces as it reaches small scales. This minimum energy is set by the balance between leakage energy and dynamic energy in subthreshold CMOS circuits, and sets floors on the achievable energy of digital units. A new, post-CMOS device with a sharper subthreshold slope than CMOS would be able to sidestep this minimum energy constraint.
A candidate device called a nano-electromechancial (NEM) relay has recently emerged. NEM relays are small, integrated, capacitively-actuated, mechanical switches. The devices have demonstrated extremely high subthreshold slopes: ten orders of magnitude over a millivolt of swing. However, in the same lithographic process they are twenty times larger than a minimum sized CMOS device, their gate capacitance is ten times that of a minimum sized CMOS device, and their mechanical motion is an order of magnitude slower than a CMOS inverter. Can NEM relays improve digital systems even with these drawbacks?
With proper circuit design, simulations say "yes". This dissertation examines three of the critical components of digital systems—logic, timing, and memory—and proposes NEM circuits which mitigate the weaknesses of the technology while achieving design goals. Simulations show that optimized relay logic, which arranges for all of the slow movement of relays to happen at the same time, can achieve an improvement of 10x in energy-per-operation below the CMOS minimum energy point at a penalty of 10x in delay and 3x in area. This logic style is experimentally demonstrated. In addition, relay latch based timing with staticization in the feedback path is simulated, which results in a working relay pipeline with zero mechanical delays of timing overhead. Finally, a new device called NEMory is proposed to build dense, non-volatile, mechanical memory. A hybrid NEMory/CMOS array is simulated, and its performance is compared to other memory solutions. The NEMory density is higher than any non-volatile memory except for multi-level cell, o-chip Flash, and its read and write energy are lower than any other non-volatile technology. Finally, the scaling and process limits of realizing mechanical devices are discussed in the context of future work.
Al, Bastami Anas Ibrahim. "Power monitoring in integrated circuits." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/92973.
Full textThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 201-203).
Power monitoring is needed in most electrical systems, and is crucial for ensuring reliability in everything from industrial and telecom applications, to automotive and consumer electronics. Power monitoring of integrated circuits (ICs) is also essential, as today ICs exist in most electrical and electronic systems, in a vast range of applications. Many ICs, including power ICs, have functional blocks across the chip that are used for different purposes. Measuring circuit block currents in both analog and digital ICs is important in a wide range of applications, including power management as well as IC testing and fault detection and analysis. For example, the presence of different kinds of faults in IC circuit blocks during IC fabrication causes the currents flowing through these circuit blocks to change from the expected values. There has been general interest in monitoring currents through different circuit blocks in an attempt to identify the location and type of the faults. Previous works on non intrusive load monitoring as well as on power-line communications (PLCs) provide motivation for the work presented here. The techniques are extended and used to develop a new method for power monitoring in ICs. Most solutions to the challenge of measuring currents in different circuit blocks of the IC involve adding circuitry that is both costly and power consuming. In this work, a new method is proposed to enable individual measurement of current consumed in each circuit block within an IC while adding negligible area and power overhead. This method works by encoding the individual current signatures in the main supply current of the IC, which can then be sensed and sampled off-chip, and then disaggregated through signal processing. A demonstration of this power monitoring scheme is given on a modular discrete platform that is implemented based on the UC3842 current-mode controller IC, which can also be used for educational purposes.
by Anas Ibrahim Al Bastami.
S.M.
Daitch, Samuel Isaac. "Translating alloy using Boolean circuits." Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/33129.
Full textIncludes bibliographical references (p. 71-72).
Alloy is a automatically analyzable modelling language based on first-order logic. An Alloy model can be translated into a Boolean formula whose satisfying assignments correspond to instances in the model. Currently, the translation procedure mechanically converts each piece of the Alloy model individually into its most straightforward Boolean representation. This thesis proposes a more efficient approach to translating Alloy models. The key is to take advantage of the fact that an Alloy model contains patterns that are used repeatedly. This makes it natural to give a model a more structured Boolean representation, namely a Boolean circuit. Reusable pieces in the model correspond to circuit components. By identifying the most frequently used components and optimizing their corresponding Boolean formulas, the size of the overall formula for the model would be reduced without significant additional work. A smaller formula would potentially decrease the time required to determine satisfiability, resulting in faster analysis overall.
by Samuel Isaac Daitch.
M.Eng.
Price, Michael Ph D. (Michael R. ). Massachusetts Institute of Technology. "Energy-scalable speech recognition circuits." Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/106090.
Full textCataloged from PDF version of thesis.
Includes bibliographical references (pages 135-141).
As people become more comfortable with speaking to machines, the applications of speech interfaces will diversify and include a wider range of devices, such as wearables, appliances, and robots. Automatic speech recognition (ASR) is a key component of these interfaces that is computationally intensive. This thesis shows how we designed special-purpose integrated circuits to bring local ASR capabilities to electronic devices with a small size and power footprint. This thesis adopts a holistic, system-driven approach to ASR hardware design. We identify external memory bandwidth as the main driver in system power consumption and select algorithms and architectures to minimize it. We evaluate three acoustic modeling approaches-Gaussian mixture models (GMMs), subspace GMMs (SGMMs), and deep neural networks (DNNs)-and identify tradeoffs between memory bandwidth and recognition accuracy. DNNs offer the best tradeoffs for our application; we describe a SIMD DNN architecture using parameter quantization and sparse weight matrices to save bandwidth. We also present a hidden Markov model (HMM) search architecture using a weighted finite-state transducer (WFST) representation. Enhancements to the search architecture, including WFST compression and caching, predictive beam width control, and a word lattice, reduce memory bandwidth to 10 MB/s or less, despite having just 414 kB of on-chip SRAM. The resulting system runs in real-time with accuracy comparable to a software recognizer using the same models. We provide infrastructure for deploying recognizers trained with open-source tools (Kaldi) on the hardware platform. We investigate voice activity detection (VAD) as a wake-up mechanism and conclude that an accurate and robust algorithm is necessary to minimize system power, even if it results in larger area and power for the VAD itself. We design fixed-point digital implementations of three VAD algorithms and explore their performance on two synthetic tasks with SNRs from -5 to 30 dB. The best algorithm uses modulation frequency features with an NN classifier, requiring just 8.9 kB of parameters. Throughout this work we emphasize energy scalability, or the ability to save energy when high accuracy or complex models are not required. Our architecture exploits scalability from many sources: model hyperparameters, runtime parameters such as beam width, and voltage/frequency scaling. We demonstrate these concepts with results from five ASR tasks, with vocabularies ranging from 11 words to 145,000 words.
by Michael Price.
Ph. D.
Netolická, Karolína. "Equivalence checking of retimed circuits." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/32104.
Full textThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (p. 25).
This thesis addresses the problem of verifying the equivalence of two circuits, one or both of which have undergone register retiming as well as logic resynthesis. The aim of the thesis is to improve the ability of Formality, an equivalence checking tool written at Synopsys, to handle retimed circuits. At the beginning of this project Formality already had an implementation of peripheral retiming, an algorithm that can handle a large set of retimed circuits. In this thesis, I explain the performance, usability and special case coverage problems found in the original implementation. I review other retiming verification algorithms and conclude that none of them would perform satisfactorily in Formality. Finally, I explain the modifications made to peripheral retiming in order to solve some of the identified issues and propose partial solutions for the problems that have not been solved yet.
by Karolína Netolická.
M.Eng.
Zaveri, Jesal. "Electrical and fluidic interconnect design and technology for 3D ICS." Thesis, Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39550.
Full textZaabab, Abdel Hafid. "SCFL VLSI circuits for improved yield." Thesis, University of Ottawa (Canada), 1993. http://hdl.handle.net/10393/6599.
Full textSaadallah, Nisrine. "High-speed low-power asynchronous circuits." Thesis, McGill University, 2004. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=80140.
Full textIn Chapter two we present a new asynchronous pipeline logic family with improved latency and throughput compared to several other asynchronous pipeline circuits. The channels between pipeline stages use data encoding and a small set of minimum-delay timing constraints that permit modular design with few dependencies on technology and layout. We develop circuit blocks that implement linear pipelines as well as forking, joining and data-dependent decisions. An implementation in 0.18mum CMOS exhibits a latency of 56ps per pipeline stage and throughput of 4.8-giga data item per second (GDI/s) in Hspice simulation.
We also present the design of a low-control-overhead asynchronous microprocessor integrated with a high-speed sampling FIFO. This is an experiment in exploring the benefits of asynchronous design in high-speed embedded DSP applications. It reports on the design approach, implementation and performance, including a comparison with the synchronous version of the microprocessor.
Shenoy, Sandeep P. (Sandeep Pundalika). "Switching activity in CMOS digital circuits." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=24071.
Full textThe objective of this thesis is to develop and implement a method to further improve upon the switching activity estimate through consideration of reconvergent fanout regions in the circuit. The idea is to impose functional consistency upon the waveforms at the nodes of a subset of the circuit to obtain an exact count of the number of transitions and potentially the exact waveforms which give rise to that. The result is the same as if an exact simulation was performed, but the novelty here is in the technique. An exact simulation would have exponential complexity as all possible waveforms on the PIs to the sub-circuit would have to be enumerated. Branch and bound techniques are used here instead to execute a progressively limited analysis which avoids exponential complexity. Furthermore heuristics are used to speed up the algorithm.
In addition a simple greedy algorithm has been developed and implemented to identify the sub-circuits where application of the above described technique would have the best results. The greedy algorithm represents only a preliminary step, and further work needs to be done on a more comprehensive circuit partitioning technique.
Smith, Nathan. "Substrate integrated waveguide circuits and systems." Thesis, McGill University, 2010. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=92388.
Full textCette thèse examine des interconnexions, des composantes et des systèmes basés sur des guides d'ondes intégrés au substrat (GIS). Les GIS sont des interconnexions de haute performance à large bande qui possèdent d'excellentes caractéristiques d'immunité contre les interférences électromagnétiques et qu'on pourrait utiliser dans des systèmes microondes et des circuits d'ondes millimétriques. Le coût des GIS est très faible comparativement à celui des guides d'ondes métalliques communs, car leur fabrication utilise des techniques peu coûteuses de production de cartes de circuits imprimés. Cette thèse étudie, au moyen de simulations à onde entière, le design de l'interconnexion et les modes supportés par le GIS. De plus, la thèse évalue les transitions des GIS ainsi que les méthodes de miniaturisation visant à diminuer l'empreinte du guide d'onde. Ensuite, la thèse expose le développement d'un répartiteur de puissance GIS Wilkinson qui possède d'excellentes propriétés isolantes allant jusqu'à 40dB entre les bornes de sortie. La thèse examine aussi une autre composante GIS: un résonateur à cavité GIS. La thèse décrit la conception d'un résonateur à cavité GIS qui est alimenté par une ligne microbande et une sonde passées par une aperture sur le mur supérieur de la cavité. L'aperture dans le mur supérieur crée une encoche plissée rayonnante, et des mesures ont révélé un gain de 7,76dB pour l'antenne adossée d'une cavité de 16,79 GHz. L'antenne possède une bande passante de 250MHz (perte de réflexion > 10dB). En plus de ce résonateur, un oscillateur micro-onde est conçu pour produire une tonalité de 10dBm. Les mesures de l'oscillateur fabriqué montrent un faible bruit de phase de -82dBc/Hz. Enfin, une nouvelle composante de GIS (un réflecteur effilé) est conçue pour compenser la caractéristique dispersive d'une interconnexion GIS près de la fréquence de coupure. Deux systèmes de correction de la disp
Zangerle, Hermann. "Behavior of single charge devices included in different electrical circuits /." Duisburg : WiKu-Verl. Stein, 2007. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=015637779&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.
Full textMacqueen, Christopher Neil. "Time based load-flow analysis and loss costing in electrical distribution systems." Thesis, Durham University, 1994. http://etheses.dur.ac.uk/1700/.
Full textMarks, Jeffery. "SOI for Frequency Synthesis in RF Integrated Circuits." NCSU, 2003. http://www.lib.ncsu.edu/theses/available/etd-03062003-034010/.
Full textThe purpose of this research has been to explore the use of the Honeywell silicon on insulator fabrication process for use in a frequency synthesizer. The research includes the fabrication of a frequency synthesizer and ring oscillators which are used to evaluate the fabrication process. Experimental results are compared to the theoretical results, providing some insight into circuit design with the silicon on insulator process. Recommendations are presented to enhance the frequency stability of such circuits. A novel method for reducing phase noise in ring oscillators through manipulation of the floating body is also presented.
Lim, Daihyun 1976. "Extracting secret keys from integrated circuits." Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/18059.
Full textIncludes bibliographical references (p. 117-119).
Modern cryptographic protocols are based on the premise that only authorized participants can obtain secret keys and access to information systems. However, various kinds of tampering methods have been devised to extract secret keys from widely fielded conditional access systems such as smartcards and ATMs. As a solution, Arbiter-based Physical Unclonable Functions (PUFs) are proposed. This technique exploits statistical delay variation of wires and transistors across integrated circuits (ICs) in the manufacturing processes to build a secret key unique to each IC. We fabricated Arbiter-based PUFs in custom silicon and investigated the identification based PUFs in custom silicon and investigated the identification capability, reliability, and security of this scheme. Experimental results and theoretical studies show that a sufficient amount of variation exists across ICs. This variation enables each IC to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage. Thus, arbiter-based PUFs are well-suited to build key-cards and membership cards that must be resistant to cloning attacks.
by Daihyun Lim.
S.M.
Gill, Malvinder Singh. "Optically powered electrical resonant circuit incorporating reactive sensors and having fibre optic links." Thesis, Brunel University, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.363284.
Full textGroom, C. G. "Fuzzy logic and its application to dynamic security assessment of electrical power systems." Thesis, University of Bath, 1994. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.239955.
Full textDjadi, Younes. "Yield study of gallium arsenide VLSI circuits." Thesis, University of Ottawa (Canada), 1993. http://hdl.handle.net/10393/11040.
Full textNabavi-Lishi, Abdolreza. "Delay and current evaluation in CMOS circuits." Thesis, McGill University, 1993. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=41166.
Full textThe extension to general CMOS circuits is achieved through a collapsing method which reduces each gate to an equivalent inverter. Unlike previous attempts to solve this problem, our technique is not limited to single input transitions or to step inputs. It also takes into account the relative positions of the switching inputs in series-connected transistors.
The improvement in computation speed, for delay and maximum current in large circuits, approaches 4 orders of magnitude compared to HSPICE using the level-3 MOSFET model. For current waveforms the speed improvement approaches 3 orders of magnitude. The accuracy of computing the delay and the supply current is usually within 10% and 12%, respectively. Although the technique has been tested on static CMOS gate circuits, the extension to dynamic circuits is straightforward.
Radecka, Katarzyna. "Arithmetic transform in verification of datapath circuits." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=84419.
Full textThe thesis first presents the methodology for simulation-based verification under a fault model. We propose an implicit fault model that is especially suitable for arithmetic circuit verification. The model is based on the AT representation of the faults, enabling the verification by the Universal Diagnosis Set (UDS) approach to test vector generation. We draw useful relations between the Arithmetic and Walsh-Hadamard spectrum that bound the AT error spectrum, and place the verification in the context of inducing a class of small error circuits.
Next, we address the problem of identifying redundant errors, which significantly degrade the performance of the overall verification. New algorithms are presented for exact and approximate identification of redundant faults by don't care calculation and satisfiability formulation. These algorithms can further benefit from employing fast manufacturing fault detection schemes.
Finally, we propose extensions to AT that are suitable for equivalence checking of sequential datapaths. We show that the proposed forms further facilitate verification of imprecise arithmetic circuits by a direct polynomial maximization over Boolean inputs.
Tannir, Dani A. "Efficient nonlinear distortion analysis of RF circuits." Thesis, McGill University, 2006. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=99541.
Full textVeillette, Benoît R. "A study of delta-sigma oscillator circuits." Thesis, McGill University, 1995. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=22837.
Full textChan, Na-Han. "Rapid current analysis for CMOS digital circuits." Thesis, McGill University, 1994. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=26380.
Full textExtension tests on benchmark circuits containing up to 555 gates, which were analysed with CUREST using thousands of primary input patterns, demonstrate that the current analysis time is in the range of 1ms per gate per input pattern, using a SUN4/490 workstation with 32 Mb of main memory, running the SUN OS 4.103 operating system. The peak value of the total supply current, the current rise-time, and the time at which the peak occurs are usually computed to within 10% of HSPICE. However, appreciable errors often occur in the average current. This is because at the moment we do not have a good model for dealing with incomplete transitions associated with glitches in a CMOS gate.
Kong, Xiaohua 1974. "Protocol modeling and recasting for handshaking circuits." Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=86072.
Full textOur methods of modeling will be applied to asynchronous circuit synthesis; the methods will also be applied to interface recasting, by which we mean transforming the communication protocol of a module interface while preserving its functional behavior. Therefore, a circuit that uses one protocol for communication at its interface can be recast to another circuit that uses a different protocol at its interface while preserving the functional behavior of the original circuit. Furthermore, our methods would permit a single module to use several different protocols at its interfaces. By applying our methods, an additional degree of flexibility will be offered to designers in asynchronous data transmission design: namely, the choice of protocols for synchronizing circuit components without affecting the functional behavior of such components.
This thesis introduces the formal definitions of semi-hiding and converse semi-hiding operators, along with a study of the algebraic properties of these operators. First-cut algorithms for semihiding and converse semi-hiding operations have been implemented in FIREMAPS. Using these operators, specifications of circuit modules could be analyzed in the active-edge domain with less complexity and mapped to transition-level specifications if necessary.
Huang, Shaomei 1974. "High performance interfacing for mixed-timing circuits." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=80019.
Full textWu, Yu. "Modeling and Fabrication of Artificial Cellular Circuits." The Ohio State University, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1574436898591485.
Full textChen, Yonggang Suhling J. C. Jaeger Richard C. "CMOS stress sensor circuits." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Fall/Dissertations/CHEN_YONGGANG_42.pdf.
Full textLiando, Johnny 1964. "Enhancement and evaluation of SCIRTSS (sequential circuits test search system) on ISCAS'89 benchmark sequential circuits." Thesis, The University of Arizona, 1990. http://hdl.handle.net/10150/278283.
Full textJasper, David Brian. "RF pHEMT Switch Model for Multiband Cell Phone Circuits." NCSU, 2004. http://www.lib.ncsu.edu/theses/available/etd-11032004-220504/.
Full textCowan, Christopher Lee. "Drafting in Self-Timed Circuits." PDXScholar, 2019. https://pdxscholar.library.pdx.edu/open_access_etds/5099.
Full textManheller, Marcel [Verfasser]. "Optical and electrical addressing in molecule-based logic circuits / Marcel Manheller." Aachen : Hochschulbibliothek der Rheinisch-Westfälischen Technischen Hochschule Aachen, 2012. http://d-nb.info/102645378X/34.
Full textLong, David Ian. "Behavioural simulation of mixed analogue/digital circuits." Thesis, Bournemouth University, 1996. http://eprints.bournemouth.ac.uk/278/.
Full textKao, James T. (James Ting Yu). "Remote microscope for inspection of integrated circuits." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/11118.
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