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1

Mermet, Jean. Electronic Chips & Systems Design Languages. Boston, MA: Springer US, 2001.

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2

Jean-Michel, Mermet, ed. Electronic chips & systems design languages. Boston: Kluwer Academic Publishers, 2001.

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3

Mermet, Jean, ed. Electronic Chips & Systems Design Languages. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3326-6.

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4

Vajda, András. Programming many-core chips. New York, NY: Springer, 2011.

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5

A, Harper Charles, ed. Electronic assembly fabrication: Chips, circuit boards, packages, and components. New York: McGraw-Hill, 2002.

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6

Vajda, András. Programming many-core chips. New York, NY: Springer, 2011.

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7

Salinas, David. Stresses in solder joints of electronic packages. Monterey, Calif: Naval Postgraduate School, 1991.

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8

service), SpringerLink (Online, ed. Focal-Plane Sensor-Processor Chips. New York, NY: Springer Science+Business Media, LLC, 2011.

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9

In the matter of certain GPS chips, associated software and systems, and products containing same: Investigation no. 337-TA-596. Washington, DC: U.S. International Trade Commission, 2010.

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10

Tong, Ho-Ming. Advanced Flip Chip Packaging. Boston, MA: Springer US, 2013.

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11

Yoo, Hoi-Jun. Low-power NoC for high-performance SoC design. Boca Raton, Fl: Taylor & Francis, 2008.

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12

Bashir, Al-Hashimi, and Institution of Electrical Engineers, eds. System-on-chip: Next generation electronics. London: Institution of Electrical Engineers, 2006.

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13

Inc, Technical Insights, ed. Molecular electronics: Beyond the silicon chip. 2nd ed. Fort Lee, N.J: Technical Insights, 1985.

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14

Pasricha, Sudeep. On-chip communication architectures: System on chip interconnect. Amsterdam: Elsevier / Morgan Kaufmann Publishers, 2008.

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15

Pasricha, Sudeep. On-chip communication architectures: System on chip interconnect. Boston: Elsevier/Morgan Kaufmann, 2008.

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16

Western Electronic Show and Convention (1998 Anaheim, Calif.). Wescon/98: Systems-on-a-chip - next generation IP networks, chip-level design, system design, embedded systems, aerospace applications, quality/reliability/test, EDA, system environment, system interface, wireless system design, network system design, bio-medical systems : conference proceedings : Anaheim Convention Center, Anaheim, California, September 15-17, 1998. [New York]: Institute of Electrical and Electronics Engineers, 1998.

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17

Dao zhuang xin pian feng zhuang de xia tian chong liu dong yan jiu. Beijing: Ke xue chu ban she, 2008.

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18

Vardaman, Jan. Flip chip markets and infrastructure developments. Austin, Tex: TechSearch International, 2001.

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19

Chakrabarty, Krishnendu. Test resource partitioning for system-on-a-chip. Boston: Kluwer Academic Publishers, 2002.

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20

Riko, Radojcic, and Rao Gopal K, eds. Guidebook for managing silicon chip reliability. Boca Raton, Fla: CRC Press, 1999.

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21

United States. National Aeronautics and Space Administration., ed. Final design and integration of micro-chip inductive edge sensors for the seven segment demonstrator: Final report for testing of integrated edge sensors in test packages. [Washington, DC: National Aeronautics and Space Administration, 1997.

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22

Mukutmoni, Devadatta. AMPHIB: A users manual. Monterey, Calif: Naval Postgraduate School, 1993.

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23

1959-, Bailey Brian, and Piziali Andrew, eds. ESL design and verification: A prescription for electronic system-level methodology. Boston: Elsevier, 2007.

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24

Fayez, Gebali, Elmiligi Haytham, and El-Kharashi Mohamed Watheq, eds. Networks-on-chips: Theory and practice. Boca Raton: Taylor & Francis, 2009.

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25

Reflow soldering processes and troubleshooting: SMT, BGA, CSP and flip chip technologies. Boston: Newnes, 2002.

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26

Ismail, Yehea I. On-chip inductance in high speed integrated circuits. Boston: Kluwer Academic Publishers, 2001.

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27

Ismail, Yehea I. On-chip inductance in high speed integrated circuits. Boston: Kluwer Academic Publishers, 2001.

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28

Henshaw, John McAdam. An investigation of electronic techniques in plastic-based integrated chip cards. [s.l: The Author], 1998.

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29

Tanzawa, Toru. On-chip High-Voltage Generator Design. New York, NY: Springer New York, 2013.

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30

Tanzawa, Toru. On-chip high-voltage generator design. New York: Springer, 2013.

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31

1955-, Paterson Peter, and Singh Leena 1971-, eds. System-On-A-Chip verification: Methodology and techniques. Boston, MA: Kluwer Academic Publishers, 2001.

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32

Rashinkar, Prakash. System-On-A-Chip verification: Methodology and techniques. Boston, MA: Kluwer Academic Publishers, 2001.

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33

H, Lau John, ed. Chip on board technologies for multichip modules. New York: Van Nostrand Reinhold, 1994.

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34

Rodolfo, Azevedo, Santos Luiz, and SpringerLink (Online service), eds. Electronic System Level Design: An Open-Source Approach. Dordrecht: Springer Science+Business Media B.V., 2011.

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35

Mermet, J. Electronic Chips & Systems Design Languages (The Chdl Series). Springer, 2001.

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36

Vajda, András. Programming Many-Core Chips. Springer, 2014.

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37

Vajda, András. Programming Many-Core Chips. Springer, 2011.

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38

Zarándy, Ákos. Focal-Plane Sensor-Processor Chips. Springer, 2014.

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39

Stringham, Gary. RTL Design Practices: How to Design FPGAs, ASICs, ASSPs, and Other Chips to Improve Firmware Development. Pearson Education, Limited, 2020.

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40

Study of conformal coating on chip-on-board technology for space applications. Greenbelt, Md: National Aeronautics and Space Administration, Goddard Space Flight Center, 1997.

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41

Atom chips . Germany : Wiley-VCH, 2011.

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42

Wong, C. P., Ho-Ming Tong, and Yi-Shao Lai. Advanced Flip Chip Packaging. Springer, 2016.

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43

Wong, C. P., Ho-Ming Tong, and Yi-Shao Lai. Advanced Flip Chip Packaging. Springer, 2013.

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44

Low-Power NoC for High-Performance SoC Design (System-on-Chip Design and Technologies). CRC, 2008.

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45

Yoo, Hoi-Jun, Kangmin Lee, and Jun Kyong Kim. Low-Power NoC for High-Performance SoC Design. Taylor & Francis Group, 2018.

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46

Yoo, Hoi-Jun, Kangmin Lee, and Jun Kyong Kim. Low-Power Noc for High-Performance Soc Design. Taylor & Francis Group, 2008.

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47

Yoo, Hoi-Jun, Kangmin Lee, and Jun Kyong Kim. Low-Power NoC for High-Performance SoC Design. Taylor & Francis Group, 2018.

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48

Yoo, Hoi-Jun, Kangmin Lee, and Jun Kyong Kim. Low-Power NoC for High-Performance SoC Design. Taylor & Francis Group, 2018.

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49

habchi, Marouane El. No More Regret: The Electronic Chip. Independently Published, 2022.

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50

Wescon/98: Systems-on-a-chip - next generation IP networks, chip-level design, system design, embedded systems, aerospace applications, quality/reliability/test, ... Anaheim, California, September 15-17, 1998. IEEE Service Center, 1998.

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