Journal articles: 'Electronic chips'

1

Jackel, L. D., H. P. Graf, and R. E. Howard. "Electronic neural network chips." Applied Optics 26, no. 23 (December 1, 1987): 5077. http://dx.doi.org/10.1364/ao.26.005077.

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2

Vallishayee, Rakesh R., Steven A. Orszag, Eric Jackson, and Eytan Barouch. "Manufacturability of Electronic Chips." Theoretical and Computational Fluid Dynamics 10, no. 1-4 (January 1, 1998): 407–23. http://dx.doi.org/10.1007/s001620050073.

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3

Miller, David A. B. "Optical interconnects to electronic chips." Applied Optics 49, no. 25 (July 14, 2010): F59. http://dx.doi.org/10.1364/ao.49.000f59.

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4

Hayes, J. "Deep As Chips [AI chips]." Engineering & Technology 15, no. 11 (December 1, 2020): 72–75. http://dx.doi.org/10.1049/et.2020.1113.

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5

Harris, A. "Frozen chips [RFID chips]." Computing and Control Engineering 17, no. 3 (June 1, 2006): 16–21. http://dx.doi.org/10.1049/cce:20060302.

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6

Grönroos, Päivi, Nur-E-Habiba, Kalle Salminen, Marja Nissinen, Tomi Tuomaala, Kim Miikki, Qiang Zhang, et al. "Immunoassays Based on Hot Electron-Induced Electrochemiluminescence at Disposable Cell Chips with Printed Electrodes." Sensors 19, no. 12 (June 19, 2019): 2751. http://dx.doi.org/10.3390/s19122751.

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Novel hot electron-emitting working electrodes and conventional counter electrodes were created by screen printing. Thus, low-cost disposable electrode chips for bioaffinity assays were produced to replace our older expensive electrode chips manufactured by manufacturing techniques of electronics from silicon or on glass chips. The present chips were created by printing as follows: (i) silver lines provided the electronic contacts, counter electrode and the bottom of the working electrode and counter electrode, (ii) the composite layer was printed on appropriate parts of the silver layer, and (iii) finally a hydrophobic ring was added to produce the electrochemical cell boundaries. The applicability of these electrode chips in bioaffinity assays was demonstrated by an immunoassay of human C-reactive protein (i) using Tb(III) chelate label displaying long-lived hot electron-induced electrochemiluminescence (HECL) and (ii) now for the first time fluorescein isothiocyanate (FITC) was utilized as an a low-cost organic label displaying a short-lived HECL in a real-world bioaffinity assay.

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7

Szu, Harold, Jung Kim, and Insook Kim. "Live neural network formations on electronic chips." Neurocomputing 6, no. 5-6 (October 1994): 551–64. http://dx.doi.org/10.1016/0925-2312(94)90006-x.

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8

Ivanov, Yuri D., Kristina A. Malsagova, Vladimir P. Popov, Tatyana O. Pleshakova, Andrey F. Kozlov, Rafael A. Galiullin, Ivan D. Shumov, et al. "Nanoribbon-Based Electronic Detection of a Glioma-Associated Circular miRNA." Biosensors 11, no. 7 (July 13, 2021): 237. http://dx.doi.org/10.3390/bios11070237.

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Nanoribbon chips, based on “silicon-on-insulator” structures (SOI-NR chips), have been fabricated. These SOI-NR chips, whose surface was sensitized with covalently immobilized oligonucleotide molecular probes (oDNA probes), have been employed for the nanoribbon biosensor-based detection of a circular ribonucleic acid (circRNA) molecular marker of glioma in humans. The nucleotide sequence of the oDNA probes was complimentary to the sequence of the target oDNA. The latter represents a synthetic analogue of a glioma marker—NFIX circular RNA. In this way, the detection of target oDNA molecules in a pure buffer has been performed. The lowest concentration of the target biomolecules, detectable in our experiments, was of the order of ~10−17 M. The SOI-NR sensor chips proposed herein have allowed us to reveal an elevated level of the NFIX circular RNA in the blood of a glioma patient.

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9

Takei, Yusuke, Ken-ichi Nomura, Yoshinori Horii, Daniel Zymelka, Hirobumi Ushijima, and Takeshi Kobayashi. "Fabrication of Simultaneously Implementing “Wired Face-Up and Face-Down Ultrathin Piezoresistive Si Chips” on a Film Substrate by Screen-Offset Printing." Micromachines 10, no. 9 (August 26, 2019): 563. http://dx.doi.org/10.3390/mi10090563.

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We realized the implementation of an ultrathin piezoresistive Si chip and stretchable printed wires on a flexible film substrate using simple screen-offset printing technology. This process does not require a special MEMS fabrication equipment and is applicable to face-up chips where electrodes are formed on the top surface of the chip, as well as to face-down chips where electrodes are formed on the bottom surface of the chip. This fabrication process is quite useful in the field of flexible hybrid electronics (FHE) as a method for mounting and wiring electronic components on a flexible substrate. In this study, we confirmed that face-up and face-down chips could be mounted on polyimide film tape. Furthermore, it was confirmed that the two types of chips could be simultaneously mounted even if they exist on the same substrate. Five-μm-thick piezoresistive Si chips were transferred and wired on a polyimide film tape using screen-offset printing, and a band-plaster type blood pulse sensor was fabricated. Moreover, we successfully demonstrated that the blood pulse could be measured with neck, inner elbow, wrist, and ankle.

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10

Jassim, Daniya Amer, and Taha A. Elwi. "Optical nano monopoles for interconnection electronic chips applications." Optik 249 (January 2022): 168142. http://dx.doi.org/10.1016/j.ijleo.2021.168142.

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11

Eytan, Ariel, Christophe Liberek, Isabelle Graf, and Jean Golaz. "Electronic Chips Implant: A New Culture-bound Syndrome?" Psychiatry: Interpersonal & Biological Processes 65, no. 1 (March 2002): 72–74. http://dx.doi.org/10.1521/psyc.65.1.72.19761.

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12

Sharma, Chander Shekhar, Severin Zimmermann, Manish K. Tiwari, Bruno Michel, and Dimos Poulikakos. "Optimal thermal operation of liquid-cooled electronic chips." International Journal of Heat and Mass Transfer 55, no. 7-8 (March 2012): 1957–69. http://dx.doi.org/10.1016/j.ijheatmasstransfer.2011.11.052.

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13

Edwards, C. "Cheap as chips." Engineering & Technology 5, no. 8 (June 5, 2010): 36–37. http://dx.doi.org/10.1049/et.2010.0807.

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14

Baliga, J. "Chips Go Vertical." IEEE Spectrum 41, no. 3 (March 2004): 43–47. http://dx.doi.org/10.1109/mspec.2004.1270547.

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15

Asanović, Krste, and Ralph Wittig. "Big Chips." IEEE Micro 31, no. 4 (July 2011): 3–5. http://dx.doi.org/10.1109/mm.2011.72.

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16

Li, Mingli, Na Gong, Jinhui Wang, and Zhibin Lin. "Phase Change Material for Thermal Management in 3D Integrated Circuits Packaging." International Symposium on Microelectronics 2015, no. 1 (October 1, 2015): 000649–53. http://dx.doi.org/10.4071/isom-2015-tha44.

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Effective thermal control and management in three-dimensional electronic packaging are desirable to ensure the heat generated in integrated circuits can be dissipated. Conventional base materials in electronics from substrate to protective layers, due to low coefficient of thermal conductivity, cannot help to cool down the circuits, while such elevated temperature could highly impact the performance of the chips. In this study, phase change material (PCM) is selected for potential applications in thermal management of electronic packaging due to its isothermal nature and high thermal storage capability. PCM based composite is developed through the impregnation technology using highly porous expanded graphite. Heat transfer test results reveal that the PCM based composite displays superior heat storage capacity, while maintaining the favorable feature of thermal and chemical stabilization for electronic applications. Toward the end, the concept of implementation of PCM based composite is proposed in thermal control of 3D integrated circuits. It is expected the proposed composite will improve heat dissipation, and ultimately enhance the performance of the chips.

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17

Pandey, Shashank, and Carlos Mastrangelo. "Towards Transient Electronics through Heat Triggered Shattering of Off-the-Shelf Electronic Chips." Micromachines 13, no. 2 (January 31, 2022): 242. http://dx.doi.org/10.3390/mi13020242.

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With most of the critical data being stored in silicon (Si) based electronic devices, there is a need to develop such devices with a transient nature. Here, we have focused on developing a programmable and controllable heat triggered shattering transience mechanism for any off-the-shelf (OTS) Si microchip as a means to develop transient electronics which can then be safely and rapidly disabled on trigger when desired. This transience mechanism is based on irreversible and spontaneous propagation of cracks that are patterned on the back of the OTS chip in the form of grooves and then filled with thermally expandable (TE) material. Two types of TE materials were used in this study, commercially available microsphere particles and a developed elastomeric material. These materials expand >100 times their original volume on the application of heat which applies wedging stress of the groove boundaries and induces crack propagation resulting in the complete shattering of the OTS Si chip into tiny silicon pieces. Transience was controlled by temperature and can be triggered at ~160–190 °C. We also demonstrated the programmability of critical parameters such as transience time (0.35–12 s) and transience efficiency (5–60%) without the knowledge of material properties by modeling the swelling behavior using linear viscoelastic models.

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18

Sparkes, M. "Gambling on chips [radiofrequency identification chips - security]." Manufacturing Engineer 85, no. 4 (August 1, 2006): 10–11. http://dx.doi.org/10.1049/me:20060403.

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19

Gu, Yue, and Yongjun Huo. "Advanced Electronic Packaging Technology: From Hard to Soft." Materials 16, no. 6 (March 15, 2023): 2346. http://dx.doi.org/10.3390/ma16062346.

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20

Jiang, Ping, Yu Xin Song, Bi Qin Chen, Megan Harney, and Michael B. Korzenski. "Environmentally Benign Solution for Recycling Electronic Waste Using the Principles of Green Chemistry." Advanced Materials Research 878 (January 2014): 406–12. http://dx.doi.org/10.4028/www.scientific.net/amr.878.406.

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In electronic waste recycling industry, printed wire boards (PWBs)/integrated chips (ICs) recycling is one of the most challenge tasks due to the fact that PWBs/ICs are diverse and complex in terms of materials and components makeup,as well as the original equipment manufacturing processes. In this paper, we will present environmental benign solution to recover valuable metals from PWB and integrated circuit chips (ICs) dissembled from waste PWB, based on green chemistry methodologies. We will demonstrate that the process/chemistry can selectively separate and recover precious metals from base metals. The 95%-99% recovery rate of precious metals can be achieved from the recycling of PWB and integrated circuit chips.

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21

Zulkarnain, Iskandar, Hestu Nugroho Warasto, and Ibnu Sina. "Pendampingan Cara Membuat Iklan pada Usaha Keripik Singkong Ibu Imah Rosyidah." Indonesian Journal of Society Engagement 3, no. 1 (June 26, 2022): 50–56. http://dx.doi.org/10.33753/ijse.v3i1.75.

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The development of the advertising world at this time is increasingly rapid and supported by the growth of print media and the number of television stations (electronic media) which continues to increase, making companies have to be selective in making advertisements to support their sales. Appropriate and efficient marketing and promotion strategies are needed to build a brand image so that the products offered are embedded in the minds of consumers. To see the relationship between advertising and the brand image of the Cassava Chips Production Center with purchasing decisions, the research will be conducted in Gunung Sindur, Bogor, a business owned by Mrs. Imah Rosyidah. The selection of the object of research on Mrs. Imah's Cassava Chips in Gunung Sindur was due to the growing interest in cassava chips in the Gunung Sindur area and its surroundings. The Cassava Chips Production Center, Ibu Imah, is a mini-business that sells various flavors of cassava chips. Consumers who will become customers of this production certainly need comfort. Consumer purchasing decisions to buy cassava chips that they want to consume, when they have a tendency to like both the endorser model and the functions and benefits of the cassava chips themselves. The cassava chips advertisement is one of the advertisements that is planned to be displayed in both print and electronic mass media. Usually, the product advertisement displays an influential figure (Influencer) which aims to attract consumers, especially teenagers. In this advertisement, how to show the unique taste of cassava chips found in all consumers.

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22

Aspelmeyer, Markus. "Enlightened chips." Nature Photonics 1, no. 2 (February 2007): 94–95. http://dx.doi.org/10.1038/nphoton.2006.90.

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23

Schipp, Fred. "Recent Trends in Counterfeit Electronic Parts." EDFA Technical Articles 20, no. 3 (August 1, 2018): 10–16. http://dx.doi.org/10.31399/asm.edfa.2018-3.p010.

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Abstract Counterfeiting continues to be a concern in the electronics industry, particularly for microprocessors, memory chips, and high temperature range ICs. This article provides an understanding of the extent of the problem, identifies frequently copied parts, and proposes measures to help keep counterfeiters in check.

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24

RajeevBansal. "Fish And Chips." IEEE Antennas and Propagation Magazine 39, no. 2 (April 1997): 96. http://dx.doi.org/10.1109/map.1997.584508.

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25

Ahmed Mohammed Adham, Ahmed Mohammed Adham. "Ammonia Base Nanofluid as a Coolant for Electronic Chips." International Journal of Mechanical and Production Engineering Research and Development 9, no. 3 (2019): 569–80. http://dx.doi.org/10.24247/ijmperdjun201960.

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26

Miller, D. A. B. "Rationale and challenges for optical interconnects to electronic chips." Proceedings of the IEEE 88, no. 6 (June 2000): 728–49. http://dx.doi.org/10.1109/5.867687.

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27

Lee, Seong, Joon-Woong Noh, Young-Sam Kwon, Seong Taek Chung, John L. Johnson, Seong Jin Park, and Randall M. German. "Getting the heat out of hi-tech electronic chips." Metal Powder Report 61, no. 8 (September 2006): 50–52. http://dx.doi.org/10.1016/s0026-0657(06)70677-4.

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28

Sciammarella, C. A., L. Lamberti, C. Pappalettere, G. Volpicella, and F. M. Sciammarella. "Measurement of deflections experienced by electronic chips during soldering." Journal of Strain Analysis for Engineering Design 41, no. 8 (November 2006): 597–608. http://dx.doi.org/10.1243/03093247jsa168.

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29

Edwards, C. "Chips feel the crunch." Engineering & Technology 3, no. 17 (October 11, 2008): 34–37. http://dx.doi.org/10.1049/et:20081703.

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30

Chiang, C. T., and C. Y. Wu. "Implantable neuromorphic vision chips." Electronics Letters 40, no. 6 (2004): 361. http://dx.doi.org/10.1049/el:20040269.

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31

Thomas, Stuart. "Robot chips get smart." Nature Electronics 5, no. 8 (August 23, 2022): 480. http://dx.doi.org/10.1038/s41928-022-00830-x.

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32

Thomas, Stuart. "AI chips that flip." Nature Electronics 6, no. 3 (March 28, 2023): 178. http://dx.doi.org/10.1038/s41928-023-00945-9.

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33

Thomas, Stuart. "Chips with a pulse." Nature Electronics 6, no. 5 (May 26, 2023): 330. http://dx.doi.org/10.1038/s41928-023-00972-6.

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34

Monier-Vinard, Eric, Najib Laraqi, Cheikh Dia, Minh Nguyen, and Valentin Bissuel. "Analytical thermal modelling of multilayered active embedded chips into high density electronic board." Thermal Science 17, no. 3 (2013): 695–706. http://dx.doi.org/10.2298/tsci120826072m.

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The recent Printed Wiring Board embedding technology is an attractive packaging alternative that allows a very high degree of miniaturization by stacking multiple layers of embedded chips. This disruptive technology will further increase the thermal management challenges by concentrating heat dissipation at the heart of the organic substrate structure. In order to allow the electronic designer to early analyze the limits of the power dissipation, depending on the embedded chip location inside the board, as well as the thermal interactions with other buried chips or surface mounted electronic components, an analytical thermal modelling approach was established. The presented work describes the comparison of the analytical model results with the numerical models of various embedded chips configurations. The thermal behaviour predictions of the analytical model, found to be within ?10% of relative error, demonstrate its relevance for modelling high density electronic board. Besides the approach promotes a practical solution to study the potential gain to conduct a part of heat flow from the components towards a set of localized cooled board pads.

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35

Markov, Igor. "Chips in 3D." IEEE Design & Test of Computers 27, no. 4 (July 2010): 68–69. http://dx.doi.org/10.1109/mdt.2010.81.

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36

Lange, E., Y. Nitta, and K. Kyuma. "Optical neural chips." IEEE Micro 14, no. 6 (December 1994): 29–41. http://dx.doi.org/10.1109/40.331383.

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37

Nakamura, T. "Introducing cool chips." IEEE Micro 19, no. 4 (July 1999): 9–10. http://dx.doi.org/10.1109/mm.1999.782562.

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38

Nakamura, T. "Cool chips III." IEEE Micro 20, no. 6 (November 2000): 83–84. http://dx.doi.org/10.1109/mm.2000.888713.

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39

Dally, W. J., M. Tremblay, and A. J. Baum. "Hot chips 12." IEEE Micro 21, no. 2 (March 2001): 13–15. http://dx.doi.org/10.1109/mm.2001.917998.

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40

Kubiatowicz, J., and A. Wolfe. "Hot Chips 13." IEEE Micro 22, no. 2 (March 2002): 6–7. http://dx.doi.org/10.1109/mm.2002.997874.

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41

Renau, Jose, and Will Eatherton. "Hot Chips 22." IEEE Micro 31, no. 2 (March 2011): 4–5. http://dx.doi.org/10.1109/mm.2011.27.

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42

Naffziger, Samuel, and Donald Newell. "Hot Chips 25." IEEE Micro 34, no. 2 (March 2014): 4–5. http://dx.doi.org/10.1109/mm.2014.31.

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43

Kubiatowicz, John, and Stefan Rusu. "Hot Chips 30." IEEE Micro 39, no. 2 (March 1, 2019): 6–8. http://dx.doi.org/10.1109/mm.2019.2899510.

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44

Keatch, Robert P., and Brian Lawrenson. "Practical Microelectronics for Electronic Engineering Students." International Journal of Electrical Engineering & Education 35, no. 2 (April 1998): 117–38. http://dx.doi.org/10.1177/002072099803500203.

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This article describes practical microelectronic projects and the facilities at the University of Dundee, where students learn to optimise the various fabrication processes and manufacture custom silicon chips and discrete devices. This subject is potentially very wide, including theory of devices and manufacturing technology, and some fundamental aspects of circuit design.

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45

Shkarayev, Sergey, Sergey Savastiouk, and Oleg Siniaguine. "Stress and Reliability Analysis of Electronic Packages With Ultra-Thin Chips." Journal of Electronic Packaging 125, no. 1 (March 1, 2003): 98–103. http://dx.doi.org/10.1115/1.1535932.

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This research concerns itself with a stress and reliability analysis of electronic packages with ultra-thin chips based on the finite element method. The effect of chip and substrate thickness, substrate material, presence of underfill, dimensions, and shape of the bump on stress reduction is analyzed. Obtained results clearly show that chip thinning, when used with an appropriate design of the entire package, can significantly decrease stresses and stress intensity factors and improve the reliability of the package. The developed software provides an effective design tool to quantify the reliability, stresses, and deflections of a package with ultra-thin chips.

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46

Li, Chun Guang, Xiao Ming Ma, and Hai Jun Tang. "Experimental Research on Energy Spectrum Analysis on Chips from Aeroengine Oil System." Applied Mechanics and Materials 635-637 (September 2014): 957–61. http://dx.doi.org/10.4028/www.scientific.net/amm.635-637.957.

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Inspection on chips from oil system is an important method for modern aeroengine condition monitoring. Energy spectrum analysis technique is the most widely used and effective method in inspection on metal chips. In this method, size and quantity of chips are observed by scanning electronic microscope and qualitative and quantitative analysis of element contents are finished by energy dispersive spectrometer. Through above experiments, material type of metal chips can be analyzed and material mark can be determined by comparison with the materials list used in the aeroengine. In this article, characteristics and advantages of energy spectrum analysis technology are systematically introduced and typical appearance feature and energy spectrum curve of common l chips are summarized in engineering practice. In addition, problems and prospects of energy spectrum analysis technique are proposed.

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47

Lee, Ah-Hyoung, Jihun Lee, Farah Laiwalla, Vincent Leung, Jiannan Huang, Arto Nurmikko, and Yoon-Kyu Song. "A Scalable and Low Stress Post-CMOS Processing Technique for Implantable Microsensors." Micromachines 11, no. 10 (October 5, 2020): 925. http://dx.doi.org/10.3390/mi11100925.

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Implantable active electronic microchips are being developed as multinode in-body sensors and actuators. There is a need to develop high throughput microfabrication techniques applicable to complementary metal–oxide–semiconductor (CMOS)-based silicon electronics in order to process bare dies from a foundry to physiologically compatible implant ensembles. Post-processing of a miniature CMOS chip by usual methods is challenging as the typically sub-mm size small dies are hard to handle and not readily compatible with the standard microfabrication, e.g., photolithography. Here, we present a soft material-based, low chemical and mechanical stress, scalable microchip post-CMOS processing method that enables photolithography and electron-beam deposition on hundreds of micrometers scale dies. The technique builds on the use of a polydimethylsiloxane (PDMS) carrier substrate, in which the CMOS chips were embedded and precisely aligned, thereby enabling batch post-processing without complication from additional micromachining or chip treatments. We have demonstrated our technique with 650 μm × 650 μm and 280 μm × 280 μm chips, designed for electrophysiological neural recording and microstimulation implants by monolithic integration of patterned gold and PEDOT:PSS electrodes on the chips and assessed their electrical properties. The functionality of the post-processed chips was verified in saline, and ex vivo experiments using wireless power and data link, to demonstrate the recording and stimulation performance of the microscale electrode interfaces.

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48

Santra, Chita Ranjan. "A Mini Review on Graphene - A Wonder Material for New Industrial and Biomedical Applications." American Journal of Applied Bio-Technology Research 2, no. 1 (January 1, 2021): 26–29. http://dx.doi.org/10.15864/ajabtr.214.

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In this mini review we have demonstrated the enormous possibility of next generation electronic and biomedical applications of graphene and its derivatives (graphene oxides). Graphene and its derivatives (graphene oxide, GO, and reduced graphene oxide, rGO) are being evolved as “miracle materials” with manifold applications in different sectors of science and technology (starting from electronics, computer chips energy storage , clean water to tissue engineering in biological science).

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49

Yuvaraj, S., D. Padmanaban, G. PraveenKumar, Satendra Sahu, Masharipova Umida, and R. Yokeshwaran. "Performance Analysis Of SRAM and Dram in Low Power Application." E3S Web of Conferences 399 (2023): 01014. http://dx.doi.org/10.1051/e3sconf/202339901014.

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All electronic systems must function quickly in the current environment, and 80 percent of electronic chips have memory components. SRAM (Static Random Access Memory) has thus become a major key component in many VLSI Chips in order to reduce the size of the memory chips, to increase the speed, to reduce leakage current, and to increase the power efficiency. Due to its high storage density and quick access time, it has also become a popular data storage device. SRAM has been given priority in the research community due to the recent sharp development in low power and low voltage memory devices. In this study, the design and performance of SRAM and DRAM cells were analyzed. This paper outlines the development and application of modified 6T SRAM cell with increased power efficiency.

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50

Kayashima, Hideto, and Hideharu Amano. "TCI Tester: A Chip Tester for Inductive Coupling Wireless Through-Chip Interface." Journal of Low Power Electronics and Applications 13, no. 3 (August 4, 2023): 48. http://dx.doi.org/10.3390/jlpea13030048.

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The building block computation system is constructed by stacking various chips three-dimensionally. The stacked chips incorporate the same TCI IP (Through Chip Interface Intellectual Property) but cannot provide identical characteristics, requiring adjustments in power supply and bias voltage. However, providing characteristics measurement hardware for all chips is difficult due to the limitation of chip area or pin numbers. To address this problem, we developed TCI Tester, a small chip to measure electric characteristics by stacking on TCI of every chip. By stacking two TCI Tester chips, it appears that the up-directional data transfer has a stricter condition than down directional one on power supply voltage and operational frequency. Also, the transfer performance is poorer than designed. Similar measurement results are obtained by stacking TCI Tester on other chips with TCI IP. To investigate the reason, we analyzed the power grid resistance of various chips with the TCI IP. Results also showed that the chips with higher resistance have a narrow operational condition and poorer performance. The results suggest that the power grid design is important for keeping the performance through the TCI channel.

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Journal articles on the topic 'Electronic chips'

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