Dissertations / Theses: 'Electronic circuits Analog electronic systems'

1

Sabzavari, Abbas Mostafavi. "Fault simulation and diagnosis in analog electronic systems." Thesis, University of Exeter, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.328233.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Knight, Clinton D. "WWW-based testing of analog circuits." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/14863.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Yoon, Heebyung. "Fault detection and identification techniques for embedded analog circuits." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/13041.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Hu, Yichuan. "Analog non-linear coding for improved performance in compressed sensing." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 76 p, 2009. http://proquest.umi.com/pqdweb?did=1885755731&sid=5&Fmt=2&clientId=8331&RQT=309&VName=PQD.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

El-Gamal, Mohamed A. "Fault location and parameter identification in analog circuits." Ohio : Ohio University, 1990. http://www.ohiolink.edu/etd/view.cgi?ohiou1172776742.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Peng, Sheng-Yu. "Charge-based analog circuits for reconfigurable smart sensory systems." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/29655.

Full text

Abstract:

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Degertekin, F.; Committee Member: Ghovanloo, Maysam; Committee Member: Minch, Bradley. Part of the SMARTech Electronic Thesis and Dissertation Collection.

APA, Harvard, Vancouver, ISO, and other styles

7

Killens, Jacob. "Utilizing standard CMOS process floating gate devices for analog design." Master's thesis, Mississippi State : Mississippi State University, 2001. http://library.msstate.edu/etd/show.asp?etd=etd-04092001-110957.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Chawla, Ravi. "Power-efficient analog systems to perform signal-processing using floating-gate MOS device for portable applications." Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-01052005-144937/unrestricted/chawla%5Fravi%5F200505%5Fphd.pdf.

Full text

Abstract:

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.
Paul Hasler, Committee Member ; Joy Laskar, Committee Chair ; Phil Allen, Committee Member ; Dave Anderson, Committee Member ; Mark T. Smith, Committee Member. Includes bibliographical references.

APA, Harvard, Vancouver, ISO, and other styles

9

Hall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.

Full text

Abstract:

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by David Anderson.
Prvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.

APA, Harvard, Vancouver, ISO, and other styles

10

Coimbra, Ricardo Pureza. "Geração de tensão de referencia e sinal de sensoriamento termico usando transistores MOS em forte inversão." [s.n.], 2009. http://repositorio.unicamp.br/jspui/handle/REPOSIP/262029.

Full text

Abstract:

Orientador: Carlos Alberto dos Reis Filho
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-14T00:43:32Z (GMT). No. of bitstreams: 1 Coimbra_RicardoPureza_M.pdf: 4991793 bytes, checksum: 2b5fb9293ae9abe4c248964485ff74e3 (MD5) Previous issue date: 2009
Resumo: Fontes de referência de tensão e sensores de temperatura são blocos extensivamente utilizados em sistemas microeletrônicos. Como alternativa à aplicação de estruturas consolidadas, mas protegidas por acordos de propriedade intelectual, é permanente a demanda pelo desenvolvimento de novas técnicas e estruturas originais destes circuitos. Também se destaca o crescente interesse por soluções de baixa tensão, baixo consumo e compatíveis com processos convencionais de fabricação. Este trabalho descreve o desenvolvimento de um circuito que atende a estas exigências, fornecendo uma tensão de referência e um sinal de sensoriamento térmico, obtidos a partir de um arranjo adequado de transistores MOS, que operam em regime de forte inversão. O princípio de operação do circuito desenvolvido foi inspirado no conceito de que é possível empilhar n transistores MOS, polarizados com corrente adequada, de tal forma que a queda de tensão sobre a pilha de transistores, com amplitude nVGS, apresente a mesma taxa de variação térmica que a tensão VGS produzida por um único transistor. Nesta condição, a diferença entre as duas tensões é constante em temperatura, constituindo-se em uma referência de tensão. No entanto, o empilhamento de dois ou mais transistores impossibilita a operação do circuito sob baixa tensão. Isto motivou a adaptação da técnica, obtendo a tensão nVGS com o auxílio de um arranjo de resistores, sem o empilhamento de transistores. Desta forma, o potencial limitante da tensão mínima de alimentação tornou-se a própria tensão de referência, cuja amplitude é próxima de um único VGS. A estrutura desenvolvida fornece também um sinal de tensão com dependência aproximadamente linear com a temperatura absoluta, que pode ser aplicado para sensoriamento térmico. Foram fabricados protótipos correspondentes a diversas versões de dimensionamento do circuito para comprovação experimental de seu princípio de operação. O melhor desempenho verificado corresponde à geração de uma tensão de referência com coeficiente térmico de 8,7ppm/ºC, no intervalo de -40ºC a 120ºC, operando com tensão de 1V. Embora o estado da arte seja representado por índices tão baixos quanto 1ppm/ºC, para a mesma faixa de temperatura, a característica compacta do circuito e seu potencial de aplicação sob as condições de baixa tensão e baixo consumo lhe conferem valor como contribuição para este campo de pesquisa e desenvolvimento.
Abstract: Voltage references and temperature sensors are blocks extensively used in microelectronic systems. As an alternative to the use of consolidated structures that are protected by intellectual property agreements, there is a permanent demand for the development of new techniques and structures for these circuits. It can be also highlighted the growing interest for low-voltage and low-power solutions, implemented in conventional IC technologies. This work describes the development of a circuit that meets these requirements by providing a voltage reference and temperature sensing signal obtained from a suitable arrangement of MOS transistors biased in strong inversion. The operation principle of the circuit developed is based on the concept that it is possible for a stack of n MOS transistors, biased by an appropriate current, to show a voltage drop, equal to nVGS, with the same thermal variation rate as a VGS voltage produced by a single transistor. Hence, the difference between the two voltage signals is temperature independent, characterizing a voltage reference. However, the stacking of two or more transistors prevents the operation of the circuit under low voltage. This fact motivated to adapt the technique by obtaining the voltage nVGS with the aid of an array of resistors and no stacked transistors. The minimum supply voltage becomes limited only by the reference voltage itself, whose amplitude is close to a single VGS. The circuit developed also provides a voltage signal almost linearly dependent with the absolute temperature, which can be applied for thermal sensing. Prototypes corresponding to various dimensional versions of the circuit were produced to experimentally verify the principle of operation. The best performance corresponds to the generation of a voltage reference signal with 8.7ppm/ºC thermal coefficient, from -40ºC to 120ºC, under a 1V supply voltage. Although the state of the art is represented by values as low as 1ppm/ºC, at the same temperature range, the circuit's compact aspect together with the possibility to attend low-voltage and low-power requirements grants it value as contribution to this field of research and development
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica

APA, Harvard, Vancouver, ISO, and other styles

11

Cajueiro, João Paulo Cerquinho. "Fonte de tensão de referencia ajustavel implementada com transistores MOS." [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260509.

Full text

Abstract:

Orientador: Carlos Alberto dos Reis Filho
Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-05T12:05:57Z (GMT). No. of bitstreams: 1 Cajueiro_JoaoPauloCerquinho_D.pdf: 1564955 bytes, checksum: 6ff645ea51f6ee2dcb9e7ab8db6363aa (MD5) Previous issue date: 2005
Resumo: Uma nova técnica de compensação de temperatura para implementar tensões de referência em circuitos CMOS é descrita, desde o seu fundamento teórico até a comprovação experimental feita com amostras de circuitos integrados protótipos que a implementam. A ténica proposta se baseia no fato de que a tensão entre gate1, e fonte, VGS, de um transistor MOS pode tanto aumentar como diminuir com o aumento da temperatura, dependendo da corrente com que opera. Com base nisto, é possível empilhar n transistores, que estejam polarizados com uma corrente adequada de tal maneira que a queda de tensão sobre esta pilha de transistores, que tem amplitude nVGS, tenha, ao mesmo tempo, a mesma taxa de variação térmica que a tensão VGS produzida por um único transistor. Em tais condições, a diferença entre estas duas tensões é constante, tornando-se uma referencia de tensão. Uma implementação alternativa à pilha de transistores para produzir a tensão nVGS consiste num único transistor de gate ?utuante no qual a tensão VGS equivalente tem amplitude ajustável em campo. Diversos circuitos que se baseiam nesta técnica foram projetados e alguns deles fabricados em tecnologia CMOS 0,35 µm.O desempenho do melhor circuito fabricado atingiu coe?ciente térmico de 100 ppm/°C na faixa térmica de -40 a 120 °C. Outras configurações foram simuladas mostrando que é possível atingir coeficientes térmicos menores que 10 ppm/°C. O estado da arte é representado por referências de tensão que têm coeficientes térmicos de 1 ppm/°C na mesma faixa térmica em que se caracterizam os circuitos desenvolvidos. Tais referências de tensão se baseiam principalmente nos circuitos chamados de bandgap. Há também, um produto recente da empresa Intersil que utiliza um transistor que opera como memória análoga fornecendo uma tensão referência memorizada com altíssima estabilidade térmica. O princípio em que este produto se baseia, entretanto, é diferente do que está sendo proposto neste trabalho apesar do uso comum de um transistor de gate ?utuante. A contribuição deste trabalho não está no desempenho que as fontes de referência que se baseiam no princípio atingiram. Sua contribuição reside na forma como pode ser implementada, utilizando somente transistores MOS e no fato de que tem amplitude ajustável em campo. 1A palavra gate está sendo usada em toda extensão do texto, em lugar da palavra ¿porta¿, para identi?car o terminal de alta resistência de um transistor MOS
Abstract: A new technique of temperature compensation to implement a voltage reference in CMOS circuits is described, from theoretical basis to experimental evidence made with samples of integrated circuits prototypes that implement it. The proposed technique is based on the fact that the voltage between gate and source, VGS, of a MOS transistor can either increase as diminish with the increase of temperature, depending on the current with that it operates. Based in this, it is possible to pile up n transistors, that are polarized with an adequate current in such way that the voltage on this stack of transistors, that has amplitude nVGS, has, at the same time, the same thermal variation than the VGS voltage produced in only one transistor. In such conditions, the difference between these two voltages is constant, becoming a voltage reference. An alternative implementation to the stack of transistors to produce the nVGS volage consists of a ?oating gate transistor in which equivalent VGS has adjustable amplitude in ?eld. Diverse circuits that are based on this technique had been projected and some of them manufactured in technology CMOS 0,35 µm. The performance of the best manufactured circuit reached 100 ppm/°C of thermal coefficient in the thermal band of -40 to 120 °C. Other con?gurations had been simulated showing that it is possible to reach thermal coe?cients lesser that 10 ppm/°C. The state of the art is represented by voltage references that have thermal coefficients of 1 ppm/°C in the same thermal band where the developed circuits had been characterized. Such voltage references are mainly based on the circuits called bandgap. There is, also, a recent product of the Intersil company who uses a transistor that operates as analogical memory supplying a voltage reference memorized with highest thermal stability. The base principle of this product is, however, different of that being considered in this work despite the use of a ?oating gate transistor. The contribution of this work is not in the performance that the reference sources that are based on the principle had reached. Its contribution inhabits in the form as it can be implemented, only using MOS transistors and in the fact that it has adjustable amplitude in ?eld
Doutorado
Eletrônica, Microeletrônica e Optoeletrônica
Doutor em Engenharia Elétrica

APA, Harvard, Vancouver, ISO, and other styles

12

U, Seng-Pan. "Tecnicas de interpolacao em filtros multiritmo com condensadores comutados para Interfaces Analogicas com filtragem de alta-frequencia = Multirate Switched-Capacitor interpolation techniques for very high-frequency Analog Front-End filtering." Thesis, University of Macau, 2002. http://umaclib3.umac.mo/record=b1873496.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Zampronho, Neto Fernando. "Analise, projeto e layout de uma topologia de circuito regulador de tensão para aplicação em microprocessadores." [s.n.], 2009. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259236.

Full text

Abstract:

Orientadores: Jacobus Willibrordus Swart, Jader Alves de Lima Filho
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-15T17:45:20Z (GMT). No. of bitstreams: 1 ZampronhoNeto_Fernando_M.pdf: 5842798 bytes, checksum: 248329a719c06d1a00d97f94590f1b92 (MD5) Previous issue date: 2009
Resumo: Este trabalho tem como objetivo o estudo de uma arquitetura de regulador de tensão do tipo multi-fase para alimentação de microprocessadores, os quais demandam pequena variação em sua tensão, mesmo face aos seus agressivos transitórios de corrente. O estudo engloba a análise, que descreve as vantagens e desvantagens de topologias de reguladores chaveados, o projeto, a simulação, a fabricação e a caracterização experimental do regulador. Na etapa de projeto, uma nova abordagem no dimensionamento do filtro externo LC é apresentada, considerando-se seus respectivos elementos parasitas, a partir da introdução do parâmetro .fator de não idealidade., ou n, que é compreendido no intervalo [0, 1]. Quanto mais n se aproxima da unidade, menores serão os elementos parasitas do filtro, facilitando a escolha dos capacitores e indutores no mercado. Adicionalmente, é proposta uma técnica de projeto do compensador em freqüência, aplicada em topologias realimentadas por tensão. Esta consiste na soma de sua tensão de saída com a diferença de potencial entre dois de seus nós internos, que ocorre apenas durante o transitório de carga, reduzindo o tempo de resposta do regulador. Simulações mostraram uma queda de mais de 25% na ondulação da tensão de carga utilizando esta técnica, em comparação com a solução convencional. O processo, simulador e modelos utilizados neste trabalho são, respectivamente, o AMS H35, PSPICE e Bsim3v3. O layout do regulador foi feito via Mentor Graphics e possui área efetiva de 0,444mm2. A fabricação na foundry AMS foi viabilizada pelo programa multi-usuário da FAPESP. A caracterização experimental compara o tempo de resposta do regulador nas mesmas condições da etapa de simulação. Resultados experimentais indicaram uma redução de 96,1% na ondulação da tensão de carga durante seu transitório de corrente utilizando a técnica proposta, em comparação a solução convencional, validando a nova técnica de projeto do compensador em freqüência. O presente trabalho é concluído enfatizando-se os objetivos alcançados e principais resultados experimentais obtidos, dificuldades de projeto e limitações da arquitetura do regulador chaveado estudada
Abstract: This work aims to study the topology of multi-phase voltage regulators applied to microprocessors, where only tiny variations in the supply voltage are allowed, even when facing aggressive current transients. This study consists in the analysis, which describes the advantages and disadvantages of switched voltage regulator topologies, design, simulation, layout and experimental characterization of the proposed regulator. In the design phase, a new approach in sizing the external LC filter is herein described, considering their stray elements, through the introduction of the .non ideality. parameter, or n, which is valid within interval [0,1]. As more as n approaches unity, less parasitic elements the filter will have, easing the choice of the capacitors and inductors commercially available. In addition to this, a new technique applied to voltage feedback topologies is proposed, which consists in adding the output voltage of the frequency compensator to a voltage between two of its internal nodes. With such an approach, the response time of the regulator to load transients decreases. Simulation results show a reduction over 25% in the output voltage ripple using this new approach, when comparing to the traditional solution. The process, simulator and models used in this work are, respectively, AMS H35, PSPICE and Bsim 3v3. The layout of the regulator was edited through Mentor Graphics, and it has an effective area of 0.444mm2. The fabrication in foundry AMS was done by multi-user program of FAPESP. The experimental characterization compares the response time of the regulator in the same conditions of simulation phase. Experimental results indicated a 96,1% reduction in load voltage ripple during transient, when comparing the purposed technique with the traditional solution, validating the excellent performance of the regulator with the new design technique. This work is concluded by emphasizing the reached objectives and main experimental results reached, design difficulties and limitations of the switched-regulator architecture studied
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica

APA, Harvard, Vancouver, ISO, and other styles

14

Purohit, Siddharth. "Compact modeling of silicon carbide (SiC) vertical junction field effect transistor (VJFET) in PSpice using Angelov model and PSpice simulation of analog circuit building blocks using SiC VJFET model." Master's thesis, Mississippi State : Mississippi State University, 2006. http://sun.library.msstate.edu/ETD-db/ETD-browse/browse.

Full text

APA, Harvard, Vancouver, ISO, and other styles

15

Aluru, Gunasekhar. "Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849770/.

Full text

Abstract:

The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expensive and require high-performance platforms. One of the key challenges today is to select appropriate CAD or EDA tools which are open-source for academic purposes. This thesis provides a detailed examination of an open-source EDA tool called Electric VLSI Design system. An excellent and efficient CAD tool useful for students and teachers to implement ideas by modifying the source code, Electric fulfills these requirements. This thesis' primary objective is to explain the Electric software features and architecture and to provide various digital and analog designs that are implemented by this software for educational purposes. Since the choice of an EDA tool is based on the efficiency and functions that it can provide, this thesis explains all the analysis and synthesis tools that electric provides and how efficient they are. Hence, this thesis is of benefit for students and teachers that choose Electric as their open-source EDA tool for educational purposes.

APA, Harvard, Vancouver, ISO, and other styles

16

U, Seng-Pan. "多率開關電容內插技術及其在超高頻模擬前端濾波的應用." Thesis, University of Macau, 2002. http://umaclib3.umac.mo/record=b1637078.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Tassoudji, Mohammad Ali. "Electromagnetic interference in electronic circuits and systems." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/35392.

Full text

Abstract:

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
Includes bibliographical references (p. 191-198).
by Mohammad Ali Tassoudji.
Ph.D.

APA, Harvard, Vancouver, ISO, and other styles

18

Md, Ali Sawal Hamid. "System level performance and yield optimisation for analogue integrated circuits." Thesis, University of Southampton, 2009. https://eprints.soton.ac.uk/69724/.

Full text

Abstract:

Advances in silicon technology over the last decade have led to increased integration of analogue and digital functional blocks onto the same single chip. In such a mixed signal environment, the analogue circuits must use the same process technology as their digital neighbours. With reducing transistor sizes, the impact of process variations on analogue design has become prominent and can lead to circuit performance falling below specification and hence reducing the yield. This thesis explores the methodology and algorithms for an analogue integrated circuit automation tool that optimizes performance and yield. The trade-offs between performance and yield are analysed using a combination of an evolutionary algorithm and Monte Carlo simulation. Through the integration of yield parameter into the optimisation process, the trade off between the performance functions can be better treated that able to produce a higher yield. The results obtained from the performance and variation exploration are modelled behaviourally using a Verilog-A language. The model has been verified with transistor level simulation and a silicon prototype. For a large analogue system, the circuit is commonly broken down into its constituent sub-blocks, a process known as hierarchical design. The use of hierarchical-based design and optimisation simplifies the design task and accelerates the design flow by encouraging design reuse. A new approach for system level yield optimisation using a hierarchical-based design is proposed and developed. The approach combines Multi-Objective Bottom Up (MUBU) modelling technique to model the circuit performance and variation and Top Down Constraint Design (TDCD) technique for the complete system level design. The proposed method has been used to design a 7th order low pass filter and a charge pump phase locked loop system. The results have been verified with transistor level simulations and suggest that an accurate system level performance and yield prediction can be achieved with the proposed methodology.

APA, Harvard, Vancouver, ISO, and other styles

19

Bhattacharya, Sambuddha. "Template-driven parasitic-aware optimization of analog/RF IC layouts /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6121.

Full text

APA, Harvard, Vancouver, ISO, and other styles

20

Hong, Seong-Kwan. "Performance driven analog layout compiler." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/15037.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Deese, Anthony Steven Nwankpa Chika O. "Analog methods for power system analysis and load modeling /." Philadelphia, Pa. : Drexel University, 2008. http://hdl.handle.net/1860/2822.

Full text

APA, Harvard, Vancouver, ISO, and other styles

22

Anglesea, John Robert Edward. "The optimisation of multisensor arrays in electronic odour sensing systems." Thesis, University of Derby, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.270027.

Full text

APA, Harvard, Vancouver, ISO, and other styles

23

Odame, Kofi. "Exploiting device nonlinearity in analog circuit design." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/29751.

Full text

Abstract:

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Butera, Robert; Committee Member: Minch, Bradley; Committee Member: Taylor, David. Part of the SMARTech Electronic Thesis and Dissertation Collection.

APA, Harvard, Vancouver, ISO, and other styles

24

Hou, Junwei. "Concurrent fault simulation for mixed-signal circuits." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15735.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Lui, Siu-hong. "Analog circuit design by nonconvex polynomial optimization two design examples /." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39557418.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

Dai, Hong. "Development of a decomposition approach for testing large analog circuits." Ohio : Ohio University, 1989. http://www.ohiolink.edu/etd/view.cgi?ohiou1172006982.

Full text

APA, Harvard, Vancouver, ISO, and other styles

27

Cheung, Wing-tai. "Geometric programming and signal flow graph assisted design of interconnect and analog circuits." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39558526.

Full text

APA, Harvard, Vancouver, ISO, and other styles

28

Butka, Brian K. "An investigation of marrow-bandgap semiconductors : devices, circuits, and systems." Diss., Georgia Institute of Technology, 1989. http://hdl.handle.net/1853/15489.

Full text

APA, Harvard, Vancouver, ISO, and other styles

29

Ellis, Kimberly Paige. "Analysis of setup management strategies in electronic assembly systems." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/30757.

Full text

APA, Harvard, Vancouver, ISO, and other styles

30

Chakrabarti, Sudip. "Test generation for fault isolation in analog and mixed-mode circuits." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/14899.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Ozdemir, Ersin. "Evolutionary methods for the design of digital electronic circuits and systems." Thesis, Cardiff University, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.326874.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

St, Leger Aaron. "Power system security assessment through analog computation /." Click for resource, 2008. http://hdl.handle.net/1860/2815.

Full text

APA, Harvard, Vancouver, ISO, and other styles

33

Pansare, Manoj M. "Modeling and simulation of analog devices using PRECISE." Thesis, Virginia Tech, 1988. http://hdl.handle.net/10919/43263.

Full text

Abstract:

The design and development of computer models to simulate analog devices and their effects on circuit applications has been investigated at length. The focus of this research is the development of theoretical and computer models for discrete devices using the popular simulator PRECISE, PRogram for Evaluating Circuits in an Interactive Simulation Environment [3], using a new method for model construction. This new method develops a model approximating the mathematics of the simulation via perturbations and iterations [19]. The models developed by the new method in each case yield a minimum simulation accuracy of 90 percent in circuit applications. In comparison, models developed by the conventional method, which uses measured data to complete physical constructs of SPICE 2G.6 [5], offer a lower accuracy for the same circuits. Hence, the new method is more effective than the old method and also much faster, since the model generation process is now automated and does not require time-consuming manual measurements and calculations spread out over a long period of time. With further development, a computer model can also be developed for the theoretical model presented in this thesis for the Gallium Arsenide Metal Semiconductor Field Effect Transistor (GaAs MESFET) device using the same methodology that has been used to develop the computer model for the Bipolar Junction Transistor (BUT) device. Hence this research, in addition to developing a library of a hundred and fifty odd successful models in the PRECISE and SPICE formats for the diode and BUT, can also be used to develop a new model for the GaAs MESFET, which would make both PRECISE and SPICE easier and more user friendly as circuit simulators.
Master of Science

APA, Harvard, Vancouver, ISO, and other styles

34

Pous, i. Sabadí Carles. "Case based reasoning as an extension of fault dictionary methods for linear electronic analog circuits diagnosis." Doctoral thesis, Universitat de Girona, 2004. http://hdl.handle.net/10803/7728.

Full text

Abstract:

El test de circuits és una fase del procés de producció que cada vegada pren més importància quan es desenvolupa un nou producte. Les tècniques de test i diagnosi per a circuits digitals han estat desenvolupades i automatitzades amb èxit, mentre que aquest no és encara el cas dels circuits analògics. D'entre tots els mètodes proposats per diagnosticar circuits analògics els més utilitzats són els diccionaris de falles. En aquesta tesi se'n descriuen alguns, tot analitzant-ne els seus avantatges i inconvenients.
Durant aquests últims anys, les tècniques d'Intel·ligència Artificial han esdevingut un dels camps de recerca més importants per a la diagnosi de falles. Aquesta tesi desenvolupa dues d'aquestes tècniques per tal de cobrir algunes de les mancances que presenten els diccionaris de falles. La primera proposta es basa en construir un sistema fuzzy com a eina per identificar. Els resultats obtinguts son força bons, ja que s'aconsegueix localitzar la falla en un elevat tant percent dels casos. Per altra banda, el percentatge d'encerts no és prou bo quan a més a més s'intenta esbrinar la desviació.
Com que els diccionaris de falles es poden veure com una aproximació simplificada al Raonament Basat en Casos (CBR), la segona proposta fa una extensió dels diccionaris de falles cap a un sistema CBR. El propòsit no és donar una solució general del problema sinó contribuir amb una nova metodologia. Aquesta consisteix en millorar la diagnosis dels diccionaris de falles mitjançant l'addició i l'adaptació dels nous casos per tal d'esdevenir un sistema de Raonament Basat en Casos. Es descriu l'estructura de la base de casos així com les tasques d'extracció, de reutilització, de revisió i de retenció, fent èmfasi al procés d'aprenentatge.
En el transcurs del text s'utilitzen diversos circuits per mostrar exemples dels mètodes de test descrits, però en particular el filtre biquadràtic és l'utilitzat per provar les metodologies plantejades, ja que és un dels benchmarks proposats en el context dels circuits analògics. Les falles considerades son paramètriques, permanents, independents i simples, encara que la metodologia pot ser fàcilment extrapolable per a la diagnosi de falles múltiples i catastròfiques. El mètode es centra en el test dels components passius, encara que també es podria extendre per a falles en els actius.
Testing circuits is a stage of the production process that is becoming more and more important when a new product is developed. Test and diagnosis techniques for digital circuits have been successfully developed and automated. But, this is not yet the case for analog circuits. Even though there are plenty of methods proposed for diagnosing analog electronic circuits, the most popular are the fault dictionary techniques. In this thesis some of these methods, showing their advantages and drawbacks, are analyzed.
During these last decades automating fault diagnosis using Artificial Intelligence techniques has become an important research field. This thesis develops two of these techniques in order to fill in some gaps in fault dictionaries techniques. The first proposal is to build a fuzzy system as an identification tool. The results obtained are quite good, since the faulty component is located in a high percentage of the given cases. On the other hand, the percentage of successes when determining the component's exact deviation is far from being good.
As fault dictionaries can be seen as a simplified approach to Case-Based Reasoning, the second proposal extends the fault dictionary towards a Case Based Reasoning system. The purpose is
not to give a general solution, but to contribute with a new methodology. This second proposal improves a fault dictionary diagnosis by means of adding and adapting new cases to develop a
Case Based Reasoning system. The case base memory, retrieval, reuse, revise and retain tasks are described. Special attention to the learning process is taken.
Several circuits are used to show examples of the test methods described throughout the text. But, in particular, the biquadratic filter is used to test the proposed methodology because it is
defined as one of the benchmarks in the analog electronic diagnosis domain. The faults considered are parametric, permanent, independent and simple, although the methodology can be extrapolated to catastrophic and multiple fault diagnosis. The method is only focused and tested on passive faulty components, but it can be extended to cover active devices as well.

APA, Harvard, Vancouver, ISO, and other styles

35

張永泰 and Wing-tai Cheung. "Geometric programming and signal flow graph assisted design of interconnect and analog circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39558526.

Full text

APA, Harvard, Vancouver, ISO, and other styles

36

Son, Kyung-Im. "A multi-class, multi-dimensional classifier as a topology selector for analog circuit design / by Kyung-Im Son." Thesis, Connect to this title online; UW restricted, 1998. http://hdl.handle.net/1773/5919.

Full text

APA, Harvard, Vancouver, ISO, and other styles

37

Lui, Siu-hong, and 呂小康. "Analog circuit design by nonconvex polynomial optimization: two design examples." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39557418.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

St, Leger Aaron Nwankpa Chika O. "Power system security assessment through analog computation /." Philadelphia, Pa. : Drexel University, 2008. http://hdl.handle.net/1860/2815.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Abramson, David. "MITE Architectures for Reconfigurable Analog Arrays." Thesis, Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4920.

Full text

Abstract:

With the introduction of the floating-gate transistor into reconfigurable architectures, great advances have been made in the field. Recently, Hall et. al. have proposed the first truly large-scale field programmable analog array (FPAA). As an outgrowth of this work, a new class of FPAAs based on translinear elements has begun to be developed. The use of translinear elements, multiple input translinear elements (MITEs) specifically, allows for extreme versatility in the functions implemented by the system while keeping the computational elements of the FPAA regular. In addition, synthesis procedures have been developed for translinear elements. This facilitates the implementation of large-scale systems on the FPAA because the circuit design can be extracted using the synthesis procedures based on equations entered by the user. Two architectures are proposed for the new FPAA. The first architecture uses fine grain reconfigurability, every gate capacitor and the drain of each MITE can be connected arbitrarily, in order to create reconfigurable MITE networks. Circuits including a squaring circuit, a square root circuit, a translinear loop, a vector magnitude circuit, and a 1st-order log-domain filter were implemented using this architecture and results are presented. In addition, examples are shown to illustrate the compilation of the circuits onto the FPAA. The second proposed architecture uses a mix of fine and medium granularity in order to simplify the implementation of larger systems. Examples are given and again the compilation of the circuits onto the FPAA is shown.

APA, Harvard, Vancouver, ISO, and other styles

40

Srinivasan, Venkatesh. "Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11588.

Full text

Abstract:

In this work, programmable analog techniques using floating-gate transistors have been developed to design precision analog circuits, low-power signal processing primitives and adaptive systems that learn on-chip. Traditional analog implementations lack programmability with the result that issues such as mismatch are corrected at the expense of area. Techniques have been proposed that use floating-gate transistors as an integral part of the circuit of interest to provide both programmability and the ability to correct for mismatch. Traditionally, signal processing has been performed in the digital domain with analog circuits handling the interface with the outside world. Such a partitioning of responsibilities is inefficient as signal processing involves repeated multiplication and addition operations that are both very power efficient in the analog domain. Using programmable analog techniques, fundamental signal processing primitives such as multipliers have been developed in a low-power fashion while preserving accuracy. This results in a paradigm shift in signal processing. A co-operative analog/digital signal processing framework is now possible such that the partitioning of tasks between the analog and digital domains is performed in a power efficient manner. Complex signal processing tasks such as adaptive filtering that learn the weight coefficients are implemented by exploiting the non-linearities inherent with floating-gate programming. The resulting floating-gate synapses are compact, low-power and offer the benefits of non-volatile weight storage. In summary, this research involves developing techniques for improving analog circuit performance and in developing power-efficient techniques for signal processing and on-chip learning.

APA, Harvard, Vancouver, ISO, and other styles

41

Roh, Jeongjin. "Mixed-signal signature analysis for systems-on-a-chip." Access restricted to users with UT Austin EID Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3035971.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Tohme, Philip Edward. "Optical switching and its application in Sonet-based transmission systems." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-10242009-020314/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Bell, Ian M. "Developments in testing and design for test of mixed signal electronic circuits and systems." Thesis, University of Hull, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.441756.

Full text

APA, Harvard, Vancouver, ISO, and other styles

44

Shana'a, Osama K. "Circuit Implementation of a High-speed Continuous-time Current-mode Field Programmable Analog Array (FPAA)." PDXScholar, 1996. https://pdxscholar.library.pdx.edu/open_access_etds/5103.

Full text

Abstract:

The growing interest in programmable analog circuits has led to the development of Field Programmable Analog Arrays (FPAAs). An FPAA consists of: 1) a programmable cell that can be reconfigured to perform several analog functions. 2) an architecture that interconnects a number of copies of the programmable cell. In this thesis, the full monolithic circuit implementation of the analog part of the programmable cell is presented. Chapter I gives an introduction to the idea of FPAA and introduces the FPAA architecture and the cell block diagram. Chapter II deals with the design and verification of a differential current-mode four-quadrant multiplier. The weighting-summing circuit with the normalizing stage is discussed in Chapter III. Chapter IV presents the design of a current-mode low-voltage programmable integratorgain circuit. Programmability was achieved by changing the bias current in the designed circuits; no analog switches were used in the signal path. This shows no effect on the performance of the circuits. The presented programming method, however, relies on the availability of a programmable current source with a storage capability. The design of this current source is discussed in chapter V. Conclusions are summarized in Chapter VI. The presented designs throughout the whole thesis were supported by detailed analytical derivations with the necessary SPICE simulations to verify the performance.

APA, Harvard, Vancouver, ISO, and other styles

45

Ravi, Sanjay. "Inter-pulse interval based mixed signal representations/." Full text open access at:, 2008. http://content.ohsu.edu/u?/etd,656.

Full text

APA, Harvard, Vancouver, ISO, and other styles

46

Carastro, Lawrence A. "Predictive statistical analysis of embedded meander resistors via measurement of canonical building blocks." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15482.

Full text

APA, Harvard, Vancouver, ISO, and other styles

47

Kelber, Kristina, Wolfgang Schwarz, and Ronald Tetzlaff. "18th IEEE Workshop on Nonlinear Dynamics of Electronic Systems." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-39134.

Full text

APA, Harvard, Vancouver, ISO, and other styles

48

Tomlin, Toby-Daniel. "Analysis and modelling of jitter and phase noise in electronic systems : phase noise in RF amplifiers and jitter in timing recovery circuits." University of Western Australia. School of Electrical, Electronic and Computer Engineering, 2004. http://theses.library.uwa.edu.au/adt-WU2004.0021.

Full text

Abstract:

Timing jitter and phase noise are important design considerations in most electronic systems, particularly communication systems. The desire for faster transmission speeds and higher levels of integration, combined with lower signal levels and denser circuit boards has placed greater emphasis on managing problems related to phase noise, timing jitter, and timing distribution. This thesis reports original work on phase noise modelling in electronic systems. A new model is proposed which predicts the up-conversion of baseband noise to the carrier frequency in RF amplifiers. The new model is validated by comparing the predicted phase noise performance to experimental measurements as it applies to a common emitter (CE), bipolar junction transistor (BJT) amplifier. The results show that the proposed model correctly predicts the measured phase noise, including the shaping of the noise about the carrier frequency, and the dependence of phase noise on the amplifier parameters. In addition, new work relating to timing transfer in digital communication systems is presented. A new clock recovery algorithm is proposed for decoding timing information encoded using the synchronous residual time-stamp (SRTS) method. Again, theoretical analysis is verified by comparison with an experimental implementation. The results show that the new algorithm correctly recovers the source clock at the destination, and satisfies the jitter specification set out by the ITU-T for G.702 signals.

APA, Harvard, Vancouver, ISO, and other styles

49

Dong, Rumei. "Modeling of the cardiovascular system with integrated finite elemant and electrical analog methods /." View online ; access limited to URI, 2006. http://0-wwwlib.umi.com.helin.uri.edu/dissertations/fullcit/3239905.

Full text

APA, Harvard, Vancouver, ISO, and other styles

50

Khane, Vaibhav B. "Analogy based modeling of natural convection." Diss., Rolla, Mo. : Missouri University of Science and Technology, 2009. http://scholarsmine.mst.edu/thesis/pdf/Khane_09007dcc807046fe.pdf.

Full text

Abstract:

Thesis (M.S.)--Missouri University of Science and Technology, 2009.
Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 25, 2009) Includes bibliographical references (p. 23-24).

APA, Harvard, Vancouver, ISO, and other styles

Dissertations / Theses on the topic 'Electronic circuits Analog electronic systems'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles