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Dissertations / Theses on the topic 'Electronic Circuits and Devices'
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1
Butka, Brian K. "An investigation of marrow-bandgap semiconductors : devices, circuits, and systems." Diss., Georgia Institute of Technology, 1989. http://hdl.handle.net/1853/15489.
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Wallace, Chik-Ho Choy. "Modelling and electro-optic quantum-wells modulation devices." Thesis, University of Surrey, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.267967.
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Wasshuber, Christoph. "About single-electron devices and circuits /." Wien : Österr. Kunst- und Kulturverl, 1998. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=008183172&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.
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Poddar, Ravi. "Accurate, high speed predictive modeling of passive devices." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/14905.
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Michaelides, Stylianos. "Physics-based process modeling, reliability prediction, and design guidelines for flip-chip devices." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/16028.
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Palojärvi, P. (Pasi). "Integrated electronic and optoelectronic circuits and devices for pulsed time-of-flight laser rangefinding." Doctoral thesis, University of Oulu, 2003. http://urn.fi/urn:isbn:9514269667.
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The main focus of this work concerned with the development of integrated electronic and optoelectronic circuits and devices for pulsed time-of-flight laser rangefinding is on the construction of the receiver channel, system level integration aimed at realisation of the laser radar module and in integration of all the receiver functions of laser radar on one chip.
Since the timing discriminator is a very important part of a pulsed
time-of-flight laser rangefinder, two timing discrimination methods are presented and verified by means of circuit implementations, a leading edge discriminator and a high-pass timing discriminator. The walk error of the high-pass timing discriminator is ±4 mm in a dynamic range of 1:620 and the uncompensatable walk error of the leading edge discriminator is ±30 mm in a dynamic range of 1:4000. Additionally a new way of combining the timing discriminator with time interval measurement is presented which achieves a walk error of ±0.5 mm in a dynamic range of 1:21.
The usability of the receiver channel chip is verified by constructing three prototypes of pulsed TOF laser radar module. The laser
radar achieves mm-level accuracy in a measurement range from 4 m to 34 m with non-cooperative targets. This performance is similar to that of earlier realisations using discrete components or even better and has markedly reduced power consumption and size.
The integration level has been increased further by implementing a photodetector on the same chip as the rest of the receiver electronics. The responsivity of the photodetector is about 0.3 A/W at 850 nm wavelength and the noise of the receiver is reduced by a factor of about two relative to realisations using an external photodetector, because of the absence of parasitic capacitances and inductances caused by packages, PCB wiring, bond wires and ESD and I/O cell structures.
The functionality of a multi-channel pulsed TOF laser radar chip is demonstrated using the photodiode structure investigated here. The chip includes four photodetectors with receiver channels and a three-channel time-to-digital converter. The chip together with external optics and a laser pulse transmitter enables distances to be measured in three directions with a single optical pulse, thus showing the feasibility of implementing all the receiver functions of a pulsed time-of-flight imager on a single chip using a current semiconductor process.
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Wang, Yi-Fu 1958. "Evaluation of correlated double sampling used with solid state imagers." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277187.
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Correlated double sampling (CDS) is a widely used signal processing technique for removal of the Nyquist (reset) noise which is associated with charge sensing circuits employed in a solid state imager. In this thesis work, the power spectral density at the output of a correlated double sampling circuit with first-order low-pass filtered white noise at the input is calculated. A circuit constructed with discrete elements is made to simulate the output stage of a charge-coupled device (CCD). A low-pass filtered wide-band noise from a noise generator is added to the reset reference level when the output signal from this simulator is sampled by the correlated double sampling technique. The experiment measurements show that only about 10% of the noise power measured by simple sampling is obtained when CDS is employed. An autoregressive (AR) model is assumed to fit the sampled data and a recursive algorithm, based on least-squares solutions for the AR parameters using forward and backward linear prediction, is adopted for spectrum estimation. Some conclusions on choosing the bandwidth of the low pass filter for optimum operation is also included.
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Al-Hakim, Husam A. "Stray inductance effects and protection in GTO thyristor circuits." Thesis, Loughborough University, 1990. https://dspace.lboro.ac.uk/2134/6860.
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The recently developed gate turn-off thyristor is now becoming well established as the first choice switching device in high power converters for applications such as uninterruptible power supplies, frequency changers, and AC and some DC variable speed motor drives. The special operating features of these devices in conventional circuit configurations are investigated. The GTO thyristor physical behaviour and operating characteristics are first described and supported by measurements made at turn-off currents of up to 600A on a specially constructed test circuit. From this, it is shown that, owing to the extremely fast rates of fall of anode current at turn-off, voltage overshoot effects caused by the stray circuit inductances are highly dangerous to the device, and effective snubbing is essential. A detailed study of these stray inductance effects in constructed DC chopper and H-bridge inverter circuits follows. The circuits are modelled to include these strays, with appropriate mathematical analysis and computer simulation, to determine which stray inductances are the most influential in causing GTO thyristor voltage stress. The different switching patterns are considered for the H-bridge to provide quasi-square and various pulse width modulated (PWM) output voltage waveforms, and the detailed current transfer paths in the various circuit devices and snubber components defined and mathematically analysed in each case. Practical switching effects of diode reverse recovery and GTO mismatched switching times are demonstrated and possible damaging conditions revealed. All analytical and computed results are supported by experimental measurements. A GTO thyristor will be damaged by attempting to turn-off an over-current, and satisfactory protection against this is essential. Conventional fusing is usually inadequate, and a better method is to use a fast active system utilising either a crowbar and fuse, or rapid direct gate turn-off. Both methods are investigated and experimental results provided. It is concluded that, with appropriate circuit layout and component choice, the unavoidable stray inductance effects can be limited to manageable levels. The most severe effects are caused by the DC source inductance which is the most difficult to minimise. Others within the power circuit, if kept small, will have a marginal effect. Fast over-current protection is achievable
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Pansare, Manoj M. "Modeling and simulation of analog devices using PRECISE." Thesis, Virginia Tech, 1988. http://hdl.handle.net/10919/43263.
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The design and development of computer models to simulate analog devices and their effects on circuit applications has been investigated at length. The focus of this research is the development of theoretical and computer models for discrete devices using the popular simulator PRECISE, PRogram for Evaluating Circuits in an Interactive Simulation Environment [3], using a new method for model construction.
This new method develops a model approximating the mathematics of the simulation via perturbations and iterations [19]. The models developed by the new method in each case yield a minimum simulation accuracy of 90 percent in circuit applications. In comparison, models developed by the conventional method, which uses measured data to complete physical constructs of SPICE 2G.6 [5], offer a lower accuracy for the same circuits. Hence, the new method is more effective than the old method and also much faster, since the model generation process is now automated and does not require time-consuming manual measurements and calculations spread out over a long period of time.
With further development, a computer model can also be developed for the theoretical model presented in this thesis for the Gallium Arsenide Metal Semiconductor Field Effect Transistor (GaAs MESFET) device using the same methodology that has been used to develop the computer model for the Bipolar Junction Transistor (BUT) device. Hence this research, in addition to developing a library of a hundred and fifty odd successful models in the PRECISE and SPICE formats for the diode and BUT, can also be used to develop a new model for the GaAs MESFET, which would make both PRECISE and SPICE easier and more user friendly as circuit simulators.Master of Science
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Agar, Joshua Carl. "Highly conductive stretchable electrically conductive composites for electronic and radio frequency devices." Thesis, Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/44875.
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The electronics industry is shifting its emphasis from reducing transistor size and operational frequency to increasing device integration, reducing form factor and increasing the interface of electronics with their surroundings. This new emphasis has created increased demands on the electronic package. To accomplish the goals to increase device integration and interfaces will undoubtedly require new materials with increased functionality both electrically and mechanically.
This thesis focuses on developing new interconnect and printable conductive materials capable of providing power, ground and signal transmission with enhanced electrical performance and mechanical flexibility and robustness. More specifically, we develop: 1.) A new understanding of the conduction mechanism in electrically conductive composites (ECC). 2.) Develop highly conductive stretchable silicone ECC (S-ECC) via in-situ nanoparticle formation and sintering. 3.) Fabricate and test stretchable radio frequency devices based on S-ECC. 4.) Develop techniques and processes necessary to fabricate a stretchable package for stretchable electronic and radio frequency devices.
In this thesis we provide convincing evidence that conduction in ECC occurs predominantly through secondary charge transport mechanism (tunneling, hopping). Furthermore, we develop a stretchable silicone-based ECC which, through the incorporation of a special additive, can form and sinter nanoparticles on the surface of the metallic conductive fillers. This sintering process decreases the contact resistance and enhances conductivity of the composite. The conductive composite developed has the best reported conductivity, stretchability and reliability. Using this S-ECC we fabricate a stretchable microstrip line with good performance up to 6 GHz and a stretchable antenna with good return loss and bandwidth.
The work presented provides a foundation to create high performance stretchable electronic packages and radio frequency devices for curvilinear spaces. Future development of these technologies will enable the fabrication of ultra-low stress large area interconnects, reconfigurable antennas and other electronic and RF devices where the ability to flex and stretch provides additional functionality impossible using conventional rigid electronics.
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Elsayed, Mohamed Verfasser], Renato [Akademischer Betreuer] [Negra, and Max Christian [Akademischer Betreuer] Lemme. "Thin-film technology for graphene-based electronic devices and circuits / Mohamed Elsayed ; Renato Negra, Max Christian Lemme." Aachen : Universitätsbibliothek der RWTH Aachen, 2019. http://d-nb.info/1195779119/34.
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Antoniu, Angela Vasilut. "Contributions to the study of certain electrostatic hazards in the manufacturing process of electronic devices and circuits." Poitiers, 2010. http://theses.edel.univ-poitiers.fr/theses/2010/Vasilut-Antoniu-Angela/2010-Vasilut-Antoniu-Angela-These.pdf.
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Les risques des décharges électrostatiques (DES) sur des dispositifs et systèmes électroniques dépend de l'état de charge de l'opérateur et des objets situés à proximité. Cette thèse a eu comme objectif de contribuer à la mise au point d'une méthodologie de mesure pour caractériser l'état de charge des opérateurs et des matériaux textiles, afin d'établir leur capacité de produire DES nuisibles. Des méthodes de mesure directes et indirectes ont été proposées pour l'évaluation de la charge des opérateurs dans trois situations d'intérêt pratique. D'autres techniques, telles que la mesure de potentiel de surface et de l'intensité du champ électrique ont été utilisées pour le monitoring de l'état de charge des matériaux textiles. Des modèles comportementaux ont été établis pour la charge et la décharge de ces matériaux, en faisant appel à la méthodologie des plans d'expériences. Les essais réalisés sur des échantillons de polypropylène et de polyester ont permis de valider aussi deux méthodes permettant d'accélérer la diminution de la charge des médias isolants non-tissés en utilisant des générateurs d'ions ou des décharges couronne produites par des électrodes alimentées à des hautes tensions sinusoïdales ou triangulaires, de fréquences allant jusqu’à 400 Hz. Un exemple d'accumulation d'électricité statique sur une plaquette de silicium est aussi discuté, en rapport avec une application à la fabrication des microsystèmes électromécaniques. L'amélioration de la méthodologie de mesure est un pré-requis pour l'adoption des meilleures stratégies destinées à maîtriser les risques électrostatiques dans un environnement industrielThe risk of electrostatic discharge (ESD) on electronic devices and systems depends on the charge state of the operator and nearby objects. This thesis aimed at contributing to the development of a measurement methodology to characterize the state of charge of the operators and textile materials, in order to determine their ability to produce harmful effects. Direct and indirect measuring methods have been proposed for assessing the charge of operators in three situations of practical interest. Other techniques, such as surface potential and electric field intensity measurements were used for monitoring the state of charge of textile materials. Behavioural models have been established for the charging and discharging of these materials, using the methodology of experimental design. Tests on samples of polypropylene and polyester have also validated two methods for accelerating the reduction of the charge of insulating nonwoven media using ion generators or corona discharge produced by electrodes energized from sinusoidal or triangular high voltage supplies, at frequencies up to 400 Hz. An example of static electricity on a silicon wafer is also discussed in relation with an application to the fabrication of mechanical and electronic micro-systems. Refinement of the measurement methodology is a prerequisite for the adoption of best strategies to control electrostatic risks in an industrial environment
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Eshragh, Nadereh. "Dynamic routing in circuit-switched non-hierarchical networks." Thesis, Durham University, 1989. http://etheses.dur.ac.uk/6650/.
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This thesis studies dynamic routing in circuit-switched non-hierarchical networks based on learning automata algorithms. The application of a mathematical model for a linear reward penalty algorithm is explained. Theoretical results for this scheme verified by simulations shows the accuracy of the model. Using simulation and analysis, learning automata algorithms are compared to several other strategies on different networks. The implemented test networks may be classified into two groups. The first group are designed for fixed routing and in such networks fixed routing performs better than any dynamic routing scheme. It will be shown that dynamic routing strategies perform as well as fixed routing when trunk reservation is employed. The second group of networks are designed for dynamic routing and trunk reservation deteriorates the performance. Comparison of different routing algorithms on small networks designed to force dynamic routing demonstrates the superiority of automata under both normal and failure conditions. The thesis also considers the instability problem in non-hierarchical circuit-switched networks when dynamic routing is implemented. It is shown that trunk reservation prevents instability and increases the carried load at overloads. Finally a set of experiments are performed on large networks with realistic capacity and traffic matrices. Simulation and analytic results show that dynamic routing outperforms fixed routing and trunk reservation deteriorates the performance at low values of overload. At high overloads, optimization of trunk reservation is necessary for this class of networks. Comparison results show the improved performance with automata schemes under both normal and abnormal traffic conditions. The thesis concludes with a discussion of proposed further work including expected developments in Integrated Service Digital Networks.
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Fritze, Alexander. "Integration of optoelectronic devices, electronic circuitry and optical waveguides." Thesis, Heriot-Watt University, 2002. http://hdl.handle.net/10399/399.
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Killens, Jacob. "Utilizing standard CMOS process floating gate devices for analog design." Master's thesis, Mississippi State : Mississippi State University, 2001. http://library.msstate.edu/etd/show.asp?etd=etd-04092001-110957.
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Nguyen, Loc Bao. "Logic design using programmable logic devices." PDXScholar, 1988. https://pdxscholar.library.pdx.edu/open_access_etds/4103.
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The Programmable Logic Devices, PLO, have caused a major impact in logic design of digital systems in this decade. For instance, a twenty pin PLO device can replace from three hundreds to six hundreds Transistor Transistor Logic gates, which people have designed with since the 60s. Therefore, by using PLD devices, designers can squeeze more features, reduce chip counts, reduce power consumption, and enhance the reliability of the digital systems.
This thesis covers the most important aspects of logic design using PLD devices. They are Logic Minimization and State Assignment. In addition, the thesis also covers a seldomly used but very useful design style, Self-Synchronized Circuits.
The thesis introduces a new method to minimize Two-Level Boolean Functions using Graph Coloring Algorithms and the result is very encouraging. The raw speed of the coloring algorithms is as fast as the Espresso, the industry standard minimizer from Berkeley, and the solution is equally good.
The thesis also introduces a rule-based state assignment method which gives equal or better solutions than STASH (an Intel Automatic CAD tool) by as much as twenty percent.
One of the problems with Self-Synchronized circuits is that it takes many extra components to implement the circuit. The thesis shows how it can be designed using PLD devices and also suggests the idea of a Clock Chip to reduce the chip count to make the design style more attractive.
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Lewis, Elfed. "The thermal properties of an SF6 circuit breaker arc during the current zero period." Thesis, University of Liverpool, 1987. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.328394.
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High speed photographic and time and space resolved spectroscopic investigations have been undertaken to quantify the processes governing arc thermal reignition phenomena. A fixed nozzle and electrode geometry was used with SF6 as the host gas. A sonic flow of gas at the nozzle throat was sustained using an upstream vessel pressure of 7.8 psig. A 35.5mF capacitor bank was used to supply electrical energy for reduced and full power arcing tests using different circuit configurations. Sophisticated optical diagnostic instrumentation has enabled photographic and spectroscopic investigations with high time and space resolution to be made during the current zero period of both the full and reduced power arcing cases. The results of above experimental investigations are of value in determining the thermal structure and the processes governing thermal reignition of the circuit breaker arc of the present investigation. In particular, temperature profiles derived from the above investigations have been used to quantify the important terms of the dynamic current zero energy balance. Experimental investigations have thus been performed during the critical current zero period of a full power circuit breaker arc. The significance of these results has been realised in evaluating the current zero temperature profiles and subsequently the energy conservation equation terms for severe circuit breaking conditions
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Peng, Sheng-Yu. "Charge-based analog circuits for reconfigurable smart sensory systems." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/29655.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Degertekin, F.; Committee Member: Ghovanloo, Maysam; Committee Member: Minch, Bradley. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Hapka, Aneta. "The simulation of thermal transients in electronic devices and circuits with the nonlinearity taken into account : PhD thesis summary." Rozprawa doktorska, [s.n.], 2009. http://dlibra.tu.koszalin.pl/Content/1192.
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Zhou, Dafeng. "Circuit-level modelling and simulation of carbon nanotube devices." Thesis, University of Southampton, 2010. https://eprints.soton.ac.uk/301182/.
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The growing academic interest in carbon nanotubes (CNTs) as a promising novel class of electronic materials has led to significant progress in the understanding of CNT physics including ballistic and non-ballistic electron transport characteristics. Together with the increasing amount of theoretical analysis and experimental studies into the properties of CNT transistors, the need for corresponding modelling techniques has also grown rapidly. This research is focused on the electron transport characteristics of CNT transistors, with the aim to develop efficient techniques to model and simulate CNT devices for logic circuit analysis. The contributions of this research can be summarised as follows. Firstly, to accelerate the evaluation of the equations that model a CNT transistor, while maintaining high modelling accuracy, three efficient numerical techniques based on piece-wise linear, quadratic polynomial and cubic spline approximation have been developed. The numerical approximation simplifies the solution of the CNT transistor’s self-consistent voltage such that the calculation of the drain-source current is accelerated by at least two orders of magnitude. The numerical approach eliminates complicated calculations in the modelling process and facilitates the development of fast and efficient CNT transistor models for circuit simulation. Secondly, non-ballistic CNT transistors have been considered, and extended circuit-level models which can capture both ballistic and non-ballistic electron transport phenomena, including elastic scattering, phonon scattering, strain and tunnelling effects, have been developed. A salient feature of the developed models is their ability to incorporate both ballistic and non-ballistic transport mechanisms without a significant computational cost. The developed models have been extensively validated against reported transport theories of CNT transistors and experimental results. Thirdly, the proposed carbon nanotube transistor models have been implemented on several platforms. The underlying algorithms have been developed and tested in MATLAB, behaviourallevel models in VHDL-AMS, and improved circuit-level models have been implemented in two versions of the SPICE simulator. As the final contribution of this work, parameter variation analysis has been carried out in SPICE3 to study the performance of the proposed circuit-level CNT transistor models in logic circuit analysis. Typical circuits, including inverters and adders, have been analysed to determine the dependence of the circuit’s correct operation on CNT parameter variation.
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Wu, Xiaohua. "Field simulation and calibration in external electro-optic sampling /." *McMaster only, 1996.
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Lou, Lifang. "Design, characterization and compact modeling of novel silicon controlled rectifier (SCR)-based devices for electrostatic discharge (ESD) protection applications in integrated circuits." Orlando, Fla. : University of Central Florida, 2008. http://purl.fcla.edu/fcla/etd/CFE0002374.
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Sadik, Diane-Perle. "On Reliability of SiC Power Devices in Power Electronics." Doctoral thesis, KTH, Elkraftteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-207763.
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Silicon Carbide (SiC) is a wide-bandgap (WBG) semiconductor materialwhich has several advantages such as higher maximum electric field, lowerON-state resistance, higher switching speeds, and higher maximum allowablejunction operation temperature compared to Silicon (Si). In the 1.2 kV - 1.7kV voltage range, power devices in SiC are foreseen to replace Si Insulatedgatebipolar transistors (IGBTs) for applications targeting high efficiency,high operation temperatures and/or volume reductions. In particular, theSiC Metal-oxide semiconductor field-effect transistor (MOSFET) – which isvoltage controlled and normally-OFF – is the device of choice due to the easeof its implementation in designs using Si IGBTs.In this work the reliability of SiC devices, in particular that of the SiCMOSFET, has been investigated. First, the possibility of paralleling two discreteSiC MOSFETs is investigated and validated through static and dynamictests. Parallel-connection was found to be unproblematic. Secondly, drifts ofthe threshold voltage and forward voltage of the body diode of the SiC MOSFETare investigated through long-term tests. Also these reliability aspectswere found to be unproblematic. Thirdly, the impact of the package on thechip reliability is discussed through a modeling of the parasitic inductancesof a standard module and the impact of those inductances on the gate oxide.The model shows imbalances in stray inductances and parasitic elementsthat are problematic for high-speed switching. A long-term test on the impactof humidity on junction terminations of SiC MOSFETs dies and SiCSchottky dies encapsulated in the same standard package reveals early degradationfor some modules situated outdoors. Then, the short-circuit behaviorof three different types (bipolar junction transistor, junction field-effect transistor,and MOSFET) of 1.2 kV SiC switching devices is investigated throughexperiments and simulations. The necessity to turn OFF the device quicklyduring a fault is supported with a detailed electro-thermal analysis for eachdevice. Design guidelines towards a rugged and fast short-circuit protectionare derived. For each device, a short-circuit protection driver was designed,built and validated experimentally. The possibility of designing diode-lessconverters with SiC MOSFETs is investigated with focus on surge currenttests through the body diode. The discovered fault mechanism is the triggeringof the npn parasitic bipolar transistor. Finally, a life-cycle cost analysis(LCCA) has been performed revealing that the introduction of SiC MOSFETsin already existing IGBT designs is economically interesting. In fact,the initial investment is saved later on due to a higher efficiency. Moreover,the reliability is improved, which is beneficial from a risk-management pointof-view. The total investment over 20 years is approximately 30 % lower fora converter with SiC MOSFETs although the initial converter cost is 30 %higher.Kiselkarbid (SiC) är ett bredbandgapsmaterial (WBG) som har flera fördelar,såsom högre maximal elektrisk fältstyrka, lägre ON-state resitans, högreswitch-hastighet och högre maximalt tillåten arbetstemperatur jämförtmed kisel (Si). I spänningsområdet 1,2-1,7 kV förutses att effekthalvledarkomponenteri SiC kommer att ersätta Si Insulated-gate bipolar transistorer(IGBT:er) i tillämpningar där hög verkningsgrad, hög arbetstemperatur ellervolymreduktioner eftersträvas. Förstahandsvalet är en SiC Metal-oxidesemiconductor field-effect transistor (MOSFET) som är spänningsstyrd ochnormally-OFF, egenskaper som möjliggör enkel implementering i konstruktionersom använder Si IGBTer.I detta arbete undersöks tillförlitligheten av SiC komponenter, specielltSiC MOSFET:en. Först undersöks möjligheten att parallellkoppla tvådiskretaSiC MOSFET:ar genom statiska och dynamiska prov. Parallellkopplingbefanns vara oproblematisk. Sedan undersöks drift av tröskelspänning ochbody-diodens framspänning genom långtidsprov. Ocksådessa tillförlitlighetsaspekterbefanns vara oproblematiska. Därefter undersöks kapslingens inverkanpåchip:et genom modellering av parasitiska induktanser hos en standardmoduloch inverkan av dessa induktanser pågate-oxiden. Modellen påvisaren obalans mellan de parasitiska induktanserna, något som kan varaproblematiskt för snabb switchning. Ett långtidstest av inverkan från fuktpåkant-termineringar för SiC-MOSFET:ar och SiC-Schottky-dioder i sammastandardmodul avslöjar tidiga tecken pådegradering för vissa moduler somvarit utomhus. Därefter undersöks kortslutningsbeteende för tre typer (bipolärtransistor,junction-field-effect transistor och MOSFET) av 1.2 kV effekthalvledarswitchargenom experiment och simuleringar. Behovet att stänga avkomponenten snabbt stöds av detaljerade elektrotermiska simuleringar för allatre komponenter. Konstruktionsriktlinjer för ett robust och snabbt kortslutningsskyddtas fram. För var och en av komponenterna byggs en drivkrets medkortslutningsskydd som valideras experimentellt. Möjligheten att konstrueradiodlösa omvandlare med SiC MOSFET:ar undersöks med fokus påstötströmmargenom body-dioden. Den upptäckta felmekanismen är ett oönskat tillslagav den parasitiska npn-transistorn. Slutligen utförs en livscykelanalys(LCCA) som avslöjar att introduktionen av SiC MOSFET:ar i existerandeIGBT-konstruktioner är ekonomiskt intressant. Den initiala investeringensparas in senare pågrund av en högre verkningsgrad. Dessutom förbättrastillförlitligheten, vilket är fördelaktigt ur ett riskhanteringsperspektiv. Dentotala investeringen över 20 år är ungefär 30 % lägre för en omvandlare medSiC MOSFET:ar även om initialkostnaden är 30 % högre.
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Noborio, Masato. "Fundamental Study on SiC Metal-Insulator-Semiconductor Devices for High-Voltage Power Integrated Circuits." 京都大学 (Kyoto University), 2009. http://hdl.handle.net/2433/78006.
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Odame, Kofi. "Exploiting device nonlinearity in analog circuit design." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/29751.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Butera, Robert; Committee Member: Minch, Bradley; Committee Member: Taylor, David. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Chun, Carl S. P. (Shun Ping). "Investigation of GaAs MESFET amplifier topologies for optoelectronic receiver applications." Thesis, Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/14813.
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Li, Xuebin. "Epitaxial graphene films on SiC : growth, characterization, and devices /." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24670.
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Thesis (Ph.D.)--Physics, Georgia Institute of Technology, 2008.Committee Chair: de Heer, Walter; Committee Member: Chou, Mei-Yin; Committee Member: First, Phillip; Committee Member: Meindl, James; Committee Member: Orlando, Thomas
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Karisan, Yasir. "Full-wave Electromagnetic Modeling of Electronic Device Parasitics for Terahertz Applications." The Ohio State University, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=osu1419019102.
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Cheng, Michael Fong. "Experimental Study and Modeling of the GM-I Dependence of Long-Channel Mosfets." DigitalCommons@CalPoly, 2019. https://digitalcommons.calpoly.edu/theses/1965.
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This thesis describes an experimental study and modeling of the current-transconductance dependence of the ALD1106, ALD1107, and CD4007 arrays. The study tests the hypothesis that the I-gm dependence of these 7.8 µm to 10 µm MOSFETs conforms to the Advanced Compact Model (ACM). Results from performed measurements, however, do not support this expectation. Despite the relatively large length, both ALD1106 and ALD1107 show sufficiently pronounced ‘short-channel’ effects to render the ACM inadequate. As a byproduct of this effort, we confirmed the modified ACM equation. With an m factor of approximately 0.6, it captures the I-gm dependence with sub-28% maximum error and sub-10% average error. The paper also introduces several formulas and procedures for I-gm model extraction and tuning. These are not specific to the ALD transistor family and can apply to MOSFETs with different physical size and electrical performance.
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Theng, Sharon Phooi San. "Feasibility of micro-mirror laterally-emitting thin-film electroluminescent devices for an opto-electronic integrated circuit." Thesis, Nottingham Trent University, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.341286.
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Ostrander, Charles Nicholas. "Phase alignment of asynchronous external clock controllable devices to periodic master control signal using the Periodic Event Synchronization Unit." Thesis, Montana State University, 2009. http://etd.lib.montana.edu/etd/2009/ostrander/OstranderC0509.pdf.
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The Periodic Event Synchronization Unit aligns devices without the ability to be triggered by an external source. The primary function of the unit is to align the pattern trigger pulses of two pulse pattern generators which supply four inputs of a multiplexer. The pulse pattern generators lack the ability to start their code according to an external signal. When operating, the designed unit maintains a specific pattern alignment of two binary data streams of 5 gigabits per second as a multiplexer combines them into a data stream of four times the bit rate. In addition to alignment, the unit can introduce offsets of up to 50 nanoseconds to the pattern alignment which corresponds to 250 bits. The unit is designed to allow the alignment of other devices as well, requiring as input the two event signals of the same frequency which need to be aligned. In order to align the devices providing the event pulses, one of the devices must either accept an external clocking source or have the ability to frequency modulate the internal clock. In practice, the test system was able to achieve and maintain the desired signal characteristics from the output of the multiplexer. The unit's robust design is shown by providing alignment of patterns for the full operating range of the pulse pattern generators and allowing a generator pattern to be aligned to a generic event pulse. Use of multiple units allows alignment of additional devices. The development of the Periodic Event Synchronization Unit provided an inexpensive solution to creating very high bit rate signals using preexisting equipment, as no commercial products were found to accomplish the same function.
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Leon, Errol Heradio. "Design and Fabrication Techniques of Devices for Embedded Power Active Contact Lens." DigitalCommons@CalPoly, 2015. https://digitalcommons.calpoly.edu/theses/1387.
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This thesis designed and fabricated various devices that were interfaced to an IC for an active contact lens that notifies the user of an event by detection of an external wireless signal. The contact lens consisted of an embedded antenna providing communication with a 2.4GHz system, as well as inductive charging at an operating frequency of 13.56 MHz. The lens utilized a CBC005 5µAh thin film battery by Cymbet and a manufactured graphene super capacitor as a power source. The custom integrated circuit (IC) was designed using the On Semiconductor CMOS C5 0.6 µm process to manage the battery and drive the display. A transparent, flexible, single cell display was developed utilizing electrochromic ink to indicate to the user of an event. Assembly of the components, encapsulation, and molding were implemented to create the final product. The material properties of the chosen substrate were analyzed for their clearness, flexibility, and biocompatibility to determine its suitability as a contact lens material. Finally, the two different fabrication techniques (microfabrication and screen printing) that were employed to make the devices are compared to determine the favorable process for each part of the system.
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Loayza, Ramirez Jorge Miguel. "Study and characterization of electrical overstress aggressors on integrated circuits and robustness optimization of electrostatic discharge protection devices." Thesis, Lyon, 2017. http://www.theses.fr/2017LYSEI044.
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Cette thèse de doctorat s’inscrit dans la thématique de la fiabilité des circuits intégrés dans l’industrie de la microélectronique. Un circuit intégré peut être exposé à des agresseurs électriques potentiellement dangereux pendant toute sa durée de vie. Idéalement, les circuits devraient pouvoir encaisser ces excès d’énergie sans perdre leur fonctionnalité. En réalité, des défaillances peuvent être observées lors de tests de qualification ou en application finale. Il est donc dans l’intérêt des fabricants de réduire ces défaillances. Actuellement, il existe des circuits de protection sur puce conçus pour dévier l’énergie de ces agresseurs à l’écart des composants fragiles. Le terme anglophone Electrical Overstress (EOS) englobe tous les agresseurs électriques qui dépassent une limite au-delà de laquelle les composants peuvent être détruits. La définition de ce terme est traitée en détail dans la thèse. L’objectif de cette thèse est de comprendre le statut du sujet des EOS dans l’industrie. On propose ensuite une nouvelle méthodologie de caractérisation de circuits pour quantifier leur robustesse face à des formes d’onde représentatives présélectionnées. On propose également des solutions de circuits de protection sur puce que ce soit au niveau de nouveaux composants actifs ou au niveau de la conception des circuits électroniques de protection. Par exemple on propose un nouveau composant basé sur le thyristor qui a la capacité de s’éteindre même si la tension d’alimentation est présente sur l’anode. Une autre proposition est de désactiver les circuits de protection face aux décharges électrostatiques lorsque les puces sont dans un environnement où l’on est sur ou ces agresseurs ne présentent plus de danger. Finalement, des perspectives du travail de thèse sont citéesThis Ph.D. thesis concerns reliability issues in the microelectronics industry for the most advanced technology nodes. In particular, the Electrical OverStress (EOS) issue is studied. Reducing EOS failures in Integrated Circuits (ICs) is becoming more and more important. However, the EOS topic is very complex and involves many different causes, viewpoints, definitions and approaches. In this context, a complete analysis of the current status of the EOS issue is carried out. Then, the Ph.D. objectives can be defined in a clear way. In particular, robustness increase of on-chip protection structures and IC characterization against EOS-like aggressors are two of the main goals. In order to understand and quantify the behavior of ICs against these aggressors, a dedicated EOS test bench is put in place along with the definition of a characterization methodology. A full characterization and comparison is performed on two different Electro- Static Discharge (ESD) power supply clamps. After identifying the potential weaknesses of the promising Silicon-Controlled Rectifier (SCR) device, a new SCR-based device with a turn-off capability is proposed and studied thanks to 3-D Technology Computer-Aided Design (TCAD)simulation. Triggering and turn-off behaviors are studied, as well as its optimization. Finally, three different approaches are proposed for improving the robustness of the IC onchip protection circuits. They are characterized thanks to the EOS test bench which allows identifying their assets as well as their points of improvement
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Nguyen, Toai-Chi. "Design of an Ultra-Wideband Frequency-Modulated Continuous Wave Short Range Radar System for Extending Independent Living." DigitalCommons@CalPoly, 2021. https://digitalcommons.calpoly.edu/theses/2289.
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Falls in the disabled and elderly people have been a cause of concern as they can be immobilized by the fall and have no way to contact others and seek assistance. The proposed frequency modulated continuous wave (FMCW) short range radar (SRR) system, which uses ultra-wideband (UWB) signals can provide immediate assistance by monitoring and detecting fall events. The unique characteristics of this system allow for a frequency-based modulation system to carry out triangulation and sense the location of the fall through the usage of a continuous chirp signal that linearly sweeps frequency. This project focuses on the development, design and simulation of a ring oscillator that exhibits the frequency modulated signal on a single integrated circuit chip. The ring oscillator is controlled by a voltage ramp signal generator and a voltage to current (V-I) converter. The circuit is designed in Cadence using TSMC 180nm process technology and operates in the frequency range of 3.409 GHz to 5.349 GHz with a spectral bandwidth of 1.94 GHz, which meets the Federal Communications Commission’s standards for unlicensed ultra-wideband transmissions.
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Chawla, Ravi. "Power-efficient analog systems to perform signal-processing using floating-gate MOS device for portable applications." Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-01052005-144937/unrestricted/chawla%5Fravi%5F200505%5Fphd.pdf.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.Paul Hasler, Committee Member ; Joy Laskar, Committee Chair ; Phil Allen, Committee Member ; Dave Anderson, Committee Member ; Mark T. Smith, Committee Member. Includes bibliographical references.
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Koche, Rahulkumar Sadanand. "Measurement and modeling of passive surface mount devices on FR4 substrates." PDXScholar, 2012. https://pdxscholar.library.pdx.edu/open_access_etds/754.
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Passive components like resistors, capacitors and inductors are used in every electronic system. These are the very basic components which affect the system performance at higher frequencies and it is necessary to understand and model the behavior of these components in a very accurate manner. This work focuses on utilizing Printed Circuit Board (PCB) test boards, or fixtures, made of FR4 for characterizing Surface Mount Device (SMD) components. Agilent's Advanced Design System (ADS) microwave circuit simulation software was used for designing the microstrip transmission lines as well as for generating the layout for manufacturing of the PCB. SMD resistors, capacitors and inductors were soldered into the fixture and then measured using the Vector Network Analyzer (VNA). The calibration kit was developed in ADS. The measured data were calibrated using the TRL (Thru-Reflect-Line) calibration algorithm. A calibration kit consisting of through, three transmission lines of various lengths, open and short was designed and manufactured. Calibration procedures were performed using Cascade Microtech's WinCal XE software. Based on our experience, TRL calibration did not perform to its full potential due to errors in the value of the characteristic impedance of microstrip transmission line. This impedance is ideally assumed to be 50 Ohm, but our lines had characteristic impedance of around 49 Ohm. Simple models for the resistors and capacitors were developed by our collaborators at the University of Zagreb and we developed the model for the inductors. We used ADS for simulations and comparison with the measured data. Extensive optimization of these models was done so as to fit the measured and modeled data. As the frequency goes above 4 GHz models and measurements don't match due to the limitations of the PCB material, the increasing effects of the parasitics and calibration artifacts. This work shows how and when we can use inexpensive FR4 PCB for the characterization of the passive SMD components in the low GHz frequency range. It also examines the range of operating frequency of SMD components, verifies the parameters extracted from the simple model and tests the TRL calibration algorithm.
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Wang, Jue. "EM Modeling and Simulation of Microwave Electronic Components and Devices with Multi-scale and Multi-physics Effects." The Ohio State University, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=osu1440089513.
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Lee, Chris Y. "Full Custom VLSI Design of On-Line Stability Checkers." DigitalCommons@CalPoly, 2011. https://digitalcommons.calpoly.edu/theses/607.
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A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly.
A method for concurrent fault testing called On-line Stability Checking was introduced by Franco and McCluskey [10] to detect reliability failures. Reliability failures initially manifest themselves as delay faults and transient glitching, which become progressively larger over time due to the wearout of conducting metal lines, eventually leading to functional faults. Stability checkers periodically detect reliability failures by monitoring CUT output signals for unstable and late input signals over a time period after the sampling clock edge.
The checkers are tested by applying variable delayed input test patterns to emulate reliability failures. Consequently, configurable delay chains were incorporated into the system to provide variable delays on the input signal lines. The system also includes external test signal ports.
Circuit and layout designs were implemented in the Electric VLSI Design tool [12] and simulated with LTSPICE [13]. Electric provides Design Rule Checking (DRC) and Layout-versus-Schematic (LVS) utilities for verification. Each module was designed in a bottom-up, hierarchical cell-based approach. Functional simulation, DRC and LVS checks were performed at every subsequent higher cell layer in the design hierarchy. The final chip layout was taped out for fabrication on November 29, 2010 and finished parts were received on July 7, 2011 after two manufacturing delays.
Finished packaged parts were successfully verified for functionality based on SPICE simulations. The stability checkers were tested for flip-flop operation, glitch detection and late signal arrival detection. Configurable delay chains were tested to determine delay resolution and uniformity. Actual delay resolution and range measurements show a 3 to 4 times difference compared to simulated values.
The Electric design template created from this project includes basic CMOS logic gates with uniform standard cell heights. The template contains a 40-pin pad ring cell along with the individual pad ring components. EE 431 students would be able to create custom chips that are compatible for fabrication via the MOSIS MEP service. In future work, the template design library can be expanded to include more logic gate variants of various inputs and drive strengths as well as more complex functional modules.
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Mitra, Kalyan Yoti [Verfasser], Reinhard R. [Gutachter] Baumann, Reinhard R. [Akademischer Betreuer] Baumann, Senentxu [Gutachter] Lanceros-Méndez, Senentxu [Akademischer Betreuer] Lanceros-Méndez, Andreas [Gutachter] Schubert, and Andreas [Akademischer Betreuer] Schubert. "Towards Industrial Fabrication of Electronic Devices and Circuits by Inkjet Printing Technology / Kalyan Yoti Mitra ; Gutachter: Reinhard R. Baumann, Senentxu Lanceros-Méndez, Andreas Schubert ; Reinhard R. Baumann, Senentxu Lanceros-Méndez, Andreas Schubert." Chemnitz : Technische Universität Chemnitz, 2021. http://d-nb.info/1235138356/34.
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Zhang, Pengbei. "Circuit and system design for fully integrated CMOS direct-conversion multi-band OFDM ultra-wideband receivers." Columbus, Ohio : Ohio State University, 2007. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1172692934.
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Smith, Gabriel. "PARAMETERS AFFECTING THE RESISTIVITY OF LP-EBID DEPOSITED COPPER NANOWIRES." UKnowledge, 2018. https://uknowledge.uky.edu/ece_etds/114.
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Electron Beam Induced Deposition (EBID) is a direct write fabrication process with applications in circuit edit and debug, mask repair, and rapid prototyping. However, it suffers from significant drawbacks, most notably low purity. Work over the last several years has demonstrated that deposition from bulk liquid precursors, rather than organometallic gaseous precursors, results in high purity deposits of low resistivity (LPEBID). In this work, it is shown that the deposits resulting from LP-EBID are only highly conductive when deposited at line doses below 25μC/cm. When the dose exceeds this value, the resulting structure is highly porous providing a poor conductive pathway. It is also shown that beam current has no significant effect on the resistivity of the deposits. Nanowires with resistivity significantly lower than the previous best result of 67μΩ•cm were achieved, with the lowest resistivity being only 6.6μΩ•cm, only a factor of 4 higher than that bulk copper of 1.7μΩ•cm.
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Chen, Jianhao. "Investigation of CdS Nanowires and Planar Films for Enhanced Performance as Window Layers in CdS-CdTe Solar Cell Devices." UKnowledge, 2013. http://uknowledge.uky.edu/ece_etds/27.
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Cadmium sulfide (CdS) and cadmium telluride (CdTe) are two leading semiconductor materials used in the fabrication of thin film solar cells of relatively high power conversion efficiency and low manufacturing cost. In this work, CdS/CdTe solar cells with a varying set of processing parameters and device designs were fabricated and characterized for comparative evaluation. Studies were undertaken to elucidate the effects of (i) each step in fabrication and (ii) parameters like thickness, sheet resistance, light absorptivity solution concentration, inert gas pressure etc. Best results were obtained when the thickness of CdS planar film for the window layer was in the range of 150 nm to 200 nm. Also, CdS nanowires were fabricated for use as the window layer in CdS-CdTe solar cells. Their materials characteristics were studied with scanning electron microscopy (SEM) and X-ray Diffraction (XRD). Spectral absorption measurements on the planar CdS films and nanowire CdS layers were performed and results compared. It was established that the nanowire CdS design was superior because its absorption of sunlight was far less than that of planar CdS film, which would lead to enhanced performance in the CdS-CdTe solar cell through higher short circuit current density and higher open circuit voltage. Diode behavior of CdS-CdTe devices on planar CdS and nanowire CdS was analyzed and compared.
KEYWORDS: Thin Film Solar Cell, Nanowire, UV Absorption, Open-circuit Voltage, Close Space Sublimation
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Rüdiger, Jörg. "Feasability of a laterally emitting thin film electroluminescence device as an application specific integrated display." Thesis, Nottingham Trent University, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.341266.
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Lehmensiek, Robert. "Efficient adaptive sampling applied to multivariate, multiple output rational interpolation models, with applications in electromagnetics-based device modelling." Thesis, Stellenbosch : Stellenbosch University, 2001. http://hdl.handle.net/10019.1/8360.
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Thesis (PhD) -- Stellenbosch University, 2001.ENGLISH ABSTRACT: A robust and efficient adaptive sampling algorithm for multivariate, multiple output rational interpolation models, based on convergents of Thiele-type branched continued fractions, is presented. A variation of the standard branched continued fraction method is proposed that uses approximation to establish a non-rectangular grid of support points. Starting with a low order interpolant, the technique systematically increases the order by optimally choosing new support points in the areas of highest error, until the desired accuracy is achieved. In this way, accurate surrogate models are established by a small number of support points, without assuming any a priori knowledge of the microwave structure under study. The technique is illustrated and evaluated on several passive microwave structures, however it is general enough to be applied to many modelling problems.
AFRIKAANSE OPSOMMING: 'n Robuuste en effektiewe aanpasbare monsternemingsalgoritme vir multi-veranderlike, multi-uittree rasionale interpolasiemodelle, gegrond op konvergente van Thiele vertakte volgehoue breukuitbreidings, word beskryf. 'n Variasie op die konvensionele breukuitbreidingsmetode word voorgestel, wat 'n nie-reghoekige rooster van ondersteuningspunte gebruik in die funksiebenadering. Met 'n lae orde interpolant as beginpunt, verhoog die algoritme stelselmatig die orde van die interpolant deur optimaal verbeterde ondersteuningspunte te kies waar die grootste fout voorkom, totdat die gewensde akuraatheid bereik word. Hierdeur word akkurate surrogaat modelle opgebou ten spyte van min inisiele ondersteuningspunte, asook sonder voorkennis van die mikrogolfstruktuur ter sprake. Die algoritme word gedemonstreer en geevalueer op verskeie passiewe mikrogolfstrukture, maar is veelsydig genoeg om toepassing te vind in meer algemene modelleringsprobleme.
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Marusiak, David. "MOS CURRENT MODE LOGIC (MCML) ANALYSIS FOR QUIET DIGITAL CIRCUITRY AND CREATION OF A STANDARD CELL LIBRARY FOR REDUCING THE DEVELOPMENT TIME OF MIXED-SIGNAL CHIPS." DigitalCommons@CalPoly, 2014. https://digitalcommons.calpoly.edu/theses/1363.
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Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with the transitions. Creating a noiseless standard cell library with MCML allows use of circuitry that uses low voltage switching with 1.5V between logic levels in a quiet or mixed-signal environment as opposed to the full rail to rail swinging of CMOS logic. This allows cohesive implementation with analog circuitry on the same chip due to constant current and lower switching ranges not creating rail noise during digital switching. Standard cells allow for the Cadence tools to automatically generate circuits and Cadence serves as the development platform for the MCML standard cells.
The theory surrounding MCML is examined along with current and future applications well-suited for MCML are researched and explored with the goal of highlighting valid candidate circuits for MCML. Inverters and NAND gates with varying current drives are developed to meet these specialized goals and are simulated to prove viability for quiet, mixed-signal applications. Analysis and results show that MCML is a superior implementation choice compared toCMOSfor high speed and mixed signal applications due to frequency independent power dissipation and lack of generated noise during operation. Noise results show rail current deviations of 50nA to 300nA during switching over an average operating current of 20µA to 80µA respectively. The multiple order of magnitude difference between noise and signal allow the MCML cells to dissipate constant power and thus perform with no noise added to a system. Additional simulated results of a 31-stage ring oscillator result in a frequency for MCML of 1.57GHz simulated versus the 150.35MHz that MOSIS tested on a fabricated 31-stage CMOS oscillator. The layouts designed for the standard cell library conform to existing On Semiconductor ami06 technology dimensions and allow for design of any logical function to be fabricated. The I/O signals of each cell operate at the same input and output voltage swings which allow seamless integration with each other for implementation in any logical configuration.
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Guardia, Filho Luiz Eduardo. "Sistema para controle de maquinas robotizadas utilizando dispositivos logicos programaveis." [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259017.
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Orientador: Marconi Kolm MadridDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-04T17:12:57Z (GMT). No. of bitstreams: 1 GuardiaFilho_LuizEduardo_M.pdf: 2405031 bytes, checksum: b724836217b8586950a9ffabcd235f35 (MD5) Previous issue date: 2005
Resumo: Este trabalho de mestrado teve o propósito de projetar e construir um sistema de hard-ware capaz de realizar o controle de máquinas robotizadas em tempo real. Foi dada uma abordagem usando técnicas de processamento paralelo e eletrônica reconfigurável com o uso de dispositivos lógicos programáveis. Mostrou-se em função dos resultados das implementações que o sistema proposto é eficiente para ser utilizado no controle de robôs baseado em modelos matemáticos complexos como cinemático direto/inverso, dinâmico e de visão artificial. Esse mesmo sistema prevê sua utilização para os quatro níveis hierárquicos envolvidos em plantas que se utilizam de controle automático: supervisão, tarefas, trajetória e servomecanismos. O sistema possui interfaces de comunicação USE e RS-232, conversores A/D e D/A, sistema de processamento de imagens (entradas e saídas de sinais de vídeo analógico), portas E/S, chaves e leds para propósito geral. A eficiência foi comprovada através de experimentações práticas utilizando sistemas robóticos reais como: sistema de um pêndulo acionado, robô redundante de 4GDL denominado Cobra, e solução em hardware de funções importantes no sentido da resolução dos modelos matemáticos em tempo real como funções transcendentais
Abstract: This work had as purpose the project and build of a hardware system with abilities to accomplish the real time control of robotic machines. It was given an approach using tech-niques of parallel processing and programmable electronics configuration with programmable logic devices. According to the implementation results, it was shown that this proposed sys-tem is efficient to be used for controlling robots based on complex mathematical models, like direct/inverse kinematics, dynamics and artificial vision. This system foresees its use for the four hierarchical levels involved in industrial plants that use automatic control: supervision, tasks, trajectory /path and servomechanisms. The system has USE and RS-232 communica-tion interfaces, A/D and D/A converters, image processing capabilities (with input/output for analog video signals), I/O ports, and switches and leds for general purpose. Its efficiency is demonstrated through practical experimentations using real robotic systems as: a driven pendu-lum system, a redundant 4 DOF robot called "Cobra", and a hardware solution for important functions in the sense of real time mathematical models computing, like the transcendental functions
Mestrado
Automação
Mestre em Engenharia Elétrica
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Mays, Kenneth W. "A 40 GHz Power Amplifier Using a Low Cost High Volume 0.15 um Optical Lithography pHEMT Process." PDXScholar, 2013. https://pdxscholar.library.pdx.edu/open_access_etds/552.
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The demand for higher frequency applications is largely driven by bandwidth. The evolution of circuits in the microwave and millimeter frequency ranges always demands higher performance and lower cost as the technology and specification requirements evolve. Thus the development of new processes addressing higher frequencies and bandwidth requirements is essential to the growth of any semiconductor company participating in these markets. There exist processes which can perform in the higher frequency design space from a technical perspective. However, a cost effective solution must complement the technical merits for deployment. Thus a new 0.15 um optical lithography pHEMT process was developed at TriQuint Semiconductor to address this market segment. A 40 GHz power amplifier has been designed to quantify and showcase the capabilities of this new process by leveraging the existing processing knowledge and the implementation of high frequency scalable models. The three stage power amplifier was designed using the TOM4 scalable depletion mode FET model. The TriQuint TQP15 Design Kit also implements microstrip transmission line models that can be used for evaluating the interconnect lines and matching networks. The process also features substrate vias and the thin film resistor and MIM capacitor models which utilize the capabilities of the BCB process flow. During the design stage we extensively used Agilent ADS program for circuit and EM simulation in order to optimize the final design. Special attention was paid to proper sizing of devices, developing matching circuits, optimizing transmission lines and power combining. The final design exhibits good performance in the 40 GHz range using the new TQP15 process. The measured results show a gain of greater than 13 dB under 3 volt drain voltage and a linear output power of greater than 28 dBm at 40 GHz. The 40 GHz power amplifier demonstrates that the new process has successfully leveraged an existing manufacturing infrastructure and has achieved repeatability, high volume manufacturing, and low cost in the millimeter frequency range.
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Umoh, Ime J. "Graphene FET circuit-level device modelling." Thesis, University of Southampton, 2014. https://eprints.soton.ac.uk/369980/.
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This thesis presents models for a graphene based field effect transistor (GFET). The graphene material has been widely studied since its synthesis in 2004 and the material holds promise for the next generation electronic applications. Therefore, there is a need to model its device characteristics. In this respect the contributions presented here are, firstly, a SPICE-compatible model for both dual gate and single gate graphene transistors. The derivation of the carrier transport of both hole and electron conduction results in a set of analytical equations. These derivations cover the three identified regions of operation as well as the boundary voltage conditions that define the regions. The Jacobian entries are shown to be continuous across the region boundaries. Secondly, circuit levels model of a single-layer GFET and multi layer GFET suitable for a direct implementation in SPICE. In this contribution, a more accurate threshold voltage compared to other models is derived. This contribution also shows how models can be extended to as many layers the graphene channelled transistor has. Finally, the introduction of a thermionic resistance, which is modelled in parallel with the resistance due to gate induced charges, provides a model for the temperature dependent channel resistance. The contribution goes further to derive equations between the off current and the vertical electric fields. Thus, giving a good estimation of the tunable bandgap opening in graphene. The models in this contributions are validated against experimentally measured transistor characteristics which have been carried out by other research groups and the models show a good agreement in all cases validated. The thesis equally presents the use of a floating gate to optimize the transistors characteristics. To illustrate these contributions, algorithms of the models have been implemented on the following CAD tools, HSPICE, VHDL-AMS and Berkeley SPICE. During the course of this work one journal and five conference papers have been published.
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Ting, Sio Weng. "Multiple-bandgap defected ground structure and its applications to highly selective microwave bandpass filters." Thesis, University of Macau, 2008. http://umaclib3.umac.mo/record=b2182957.
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Torabi, Naseem M. "Materials Selection and Processing Techniques for Small Spacecraft Solar Cell Arrays." UKnowledge, 2013. http://uknowledge.uky.edu/ece_etds/22.
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Body mounted germanium substrate solar cell arrays form the faces of many small satellite designs to provide the primary power source on orbit. High efficiency solar cells are made affordable for university satellite programs as triangular devices trimmed from wafer scale solar cells. The smaller cells allow array designs to pack tightly around antenna mounts and payload instruments, giving the board design flexibility. One objective of this work is to investigate the reliability of solar cells attached to FR-4 printed circuit boards. FR-4 circuit boards have significantly higher thermal expansion coefficients and lower thermal conductivities than germanium. This thermal expansion coefficient mismatch between the FR-4 board and the components causes concern for the power system in terms of failures seen by the solar cells. These failures are most likely to occur with a longer orbital lifetime and an extended exposure to harsh environments. This work compares various methods of attaching solar cells to printed circuit boards, using solder paste alone and with a silicone adhesive, and considering the application of these adhesives by comparing the solder joints when printed by screen versus a stencil. An environmental test plan was used to compare the survivability and performance of the solar arrays.