Log in

Relevant bibliographies by topics / Electronic circuits Electronic circuits Electronic circuit design / Dissertations / Theses

To see the other types of publications on this topic, follow the link: Electronic circuits Electronic circuits Electronic circuit design.

Dissertations / Theses on the topic 'Electronic circuits Electronic circuits Electronic circuit design'

Author: Grafiati

Published: 4 June 2021

Last updated: 4 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 dissertations / theses for your research on the topic 'Electronic circuits Electronic circuits Electronic circuit design.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.

1

Corey, Steven D. "Automatic measurement-based characterization of off-chip interconnect circuitry using lumped elements /." Thesis, Connect to this title online; UW restricted, 1997. http://hdl.handle.net/1773/6008.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Gope, Dipanjan. "Integral equation based fast electromagnetic solvers for circuit applications /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6116.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Mallepalli, Samarsen Reddy. "Generic algorithms and NULL Convention Logic hardware implementation for unsigned and signed quad-rail multiplication." Diss., Rolla, Mo. : University of Missouri-Rolla, 2007. http://scholarsmine.umr.edu/thesis/pdf/Mallepalli_09007dcc803c4eec.pdf.

Full text

Abstract:

Thesis (M.S.)--University of Missouri--Rolla, 2007.
Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 66-67).

APA, Harvard, Vancouver, ISO, and other styles

4

Parameswaran, Nair Ravi Sankar. "Delay-insensitive ternary logic (DITL)." Diss., Rolla, Mo. : University of Missouri-Rolla, 2007. http://scholarsmine.umr.edu/thesis/pdf/Parameswaran_Nair_09007dcc803bc548.pdf.

Full text

Abstract:

Thesis (M.S.)--University of Missouri--Rolla, 2007.
Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 55-56).

APA, Harvard, Vancouver, ISO, and other styles

5

Matoglu, Erdem. "Statistical design, analysis, and diagnosis of digital systems and embedded RF circuits." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-06072004-131249/unrestricted/matoglu%5Ferdem%5F200405%5Fphd.pdf.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Chakraborty, Swagato. "Integral-equation modeling of distributed effects in penetrable objects for micro-electronic applications /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6072.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Wang, Yong. "Frequency domain coupled circuit-electromagnetic simulation /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/6071.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Cove, Stephen E. "A 10 gigabit per second limiting amplifier with 40dB gain and 7 GHz bandwidth for SONET OC-192 applications." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0009921.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Lui, Siu-hong. "Analog circuit design by nonconvex polynomial optimization two design examples /." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39557418.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Eckhardt, James P. "An investigation of high-performance logic circuitry in BiCMOS." Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/15759.

Full text

APA, Harvard, Vancouver, ISO, and other styles

11

Bhattacharya, Sambuddha. "Template-driven parasitic-aware optimization of analog/RF IC layouts /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6121.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Eben-Chaime, Moshe. "The physical design of printed circuit boards : a mathematical programming approach." Diss., Georgia Institute of Technology, 1989. http://hdl.handle.net/1853/25505.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Cheung, Wing-tai. "Geometric programming and signal flow graph assisted design of interconnect and analog circuits." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39558526.

Full text

APA, Harvard, Vancouver, ISO, and other styles

14

Varelas, Theodoros Carleton University Dissertation Engineering Electrical. "A monolithic BiCMOS power amplifier for low power digital radio transmitter." Ottawa, 1992.

Find full text

APA, Harvard, Vancouver, ISO, and other styles

15

So, Biu 1959. "THE METHODOLOGY AND IMPLEMENTATION OF RELAXATION METHOD TO INVESTIGATE ELECTRO-THERMAL INTERACTIONS IN SOLID-STATE INTEGRATED CIRCUITS." Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/276384.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

Natarajan, Ekanathan Palamadai. "KLU--a high performance sparse linear solver for circuit simulation problems." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0011721.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Patel, M. V. "An investigation into concurrent processing and its application to electronic circuit design." Thesis, University of Essex, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.356048.

Full text

APA, Harvard, Vancouver, ISO, and other styles

18

Groves, Michael Peter. "A soliton circuit design system /." Title page, contents and summary only, 1987. http://web4.library.adelaide.edu.au/theses/09PH/09phg884.pdf.

Full text

APA, Harvard, Vancouver, ISO, and other styles

19

Shina, Sammy G. "A design quality and cost model for printed circuit board assembly /." Thesis, Connect to Dissertations & Theses @ Tufts University, 1998.

Find full text

Abstract:

Thesis (Ph.D.)--Tufts University, 1998.
Adviser: Anil Saigal. Submitted to the Dept. of Mechanical Engineering. Includes bibliographical references. Access restricted to members of the Tufts University community. Also available via the World Wide Web;

APA, Harvard, Vancouver, ISO, and other styles

20

Lui, Siu-hong, and 呂小康. "Analog circuit design by nonconvex polynomial optimization: two design examples." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39557418.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Ozgun, Recep. "Design and timing analysis of wave pipelined circuits." Thesis, Wichita State University, 2006. http://hdl.handle.net/10057/383.

Full text

Abstract:

In conventional pipelined circuits there is only one data wave active in any pipeline stage at any time; therefore, the clock speed of the circuit is limited by the maximum stage delay in the circuit. In wave pipelining, the clock speed depends mostly on the difference between the longest and shortest path delays. In some circuit designs there are redundant elements to make the circuit less sensitive to noise, to provide higher signal driving capability, or other purposes. Also, some circuit designs include logic to detect the early completion of a computation, or to guarantee that the worst physical path delay does not equate to the worst computational delay. Prior tools for wave-pipelined circuits do not account for such design features. This research develops a computer-aided design tool to determine the maximum clock speed for wave pipelined circuits with redundant logic or where otherwise the internal circuit timing depends on the input signal values. Moreover, alternative design techniques are proposed to improve the performance of wave pipelined circuits.
Includes bibliographic references (leaves 39-41)
Thesis (M.S.)--Wichita State University, Dept. of Electrical and Computer Engineering.
"May 2006."
Includes bibliographic references (leaves 39-41)

APA, Harvard, Vancouver, ISO, and other styles

22

Hong, Seong-Kwan. "Performance driven analog layout compiler." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/15037.

Full text

APA, Harvard, Vancouver, ISO, and other styles

23

Hasan, Saad Ahmed. "Design of low power electronic circuits for bio-medical applications." Thesis, University of Liverpool, 2011. http://livrepository.liverpool.ac.uk/3024667/.

Full text

Abstract:

The operational transconductance amplifier, OTA is one of the basic building blocks in many analogue circuit applications. The low power consumption is an essential parameter in modem electronic designs for many areas particularly for portable devices and biomedical applications. For biomedical applications, the low- power low-voltage OTA-C filters operating at low-frequency ranges are desired. The low-power, low-voltage operation of electronic devices is very important for applications such as hearing aids, pacemakers, and EEG. The importance of such operation is due to the need to implant these electronic circuits inside the body of the patient for long times before re-charging or replacing the batteries as for pacemakers and future hearing aids. The small size lightweight wearable EEG systems are preferable for applications ranging from epilepsy diagnosis to brain-computer interfaces. The low power consumption is achieved by operation at very small levels of current. So, in such applications the operation in the nano-ampere current range is essential to ensure power consumption of nW or few uW. Such very small currents are obtained through the operation of MOS transistors in their sub-threshold regime. The design space in such applications is restricted by their specifications which in turn based on the nature of the application. In this work, the design and implementation of OTA-C filter topologies for two bio-medical applications are made and discussed. Those applications are represented by hearing aids and EEG applications. In hearing aids, the work focused on cochlear implant and specifically on its most important stage represented by the filter. Four OTA-C filter topologies are proposed and two of them are tested experimentally. For the filter in a hearing aid system, besides its low power operation, it is required to operate with a relatively high dynamic range of 60dB and above. The dynamic range is the operation space of the filter that specified by the range of signals which can process properly. It is bounded by the maximum power signal less than its distortion overhead level to the minimum power signal more than its noise floor. The maximum signal level the filter can perform properly represents its input linear range. The challenge in CMOS OTA sub-threshold operation is the very small input linear range which makes it extremely difficult to build low-power consumed OTA-C filters with a wide dynamic range, DR. In this work, an OTA with an input linear range of ±900mV for total harmonic distortion, THD<5% is proposed using MOSFET bumping and capacitor attenuation techniques, combined for the first time. The minimum signal level the filter can distinguish from noise is still relatively small with the use of appropriate OTA architecture and using the gm/ID methodology for MOSFET sizing. So, programmable CMOS OTA-C band-pass filter topologies operating in sub-threshold region with a dynamic range of 65dB for use in bionic ears were proposed. The power consumption for the proposed filters is in nano- Watt range for their frequency range of (lOO-I Ok) Hz. Also, a 4-channel OTA-C filter bank is designed and tested. The EEG signals have small amplitudes and frequency bands ranges of uV'S and (l-40) Hz respectively. The important issue is to design filters with small noise floor with white dominant. This is achieved with the proposed OTA which is of relatively simple architecture and with operation in the deep weak-inversion region using ±1.5V supply rails. The OTA-C filter has power consumption in the pico-Watt range for 0, e, and a signals and less than 3nW for B signals. Another topology is suggested for future work.

APA, Harvard, Vancouver, ISO, and other styles

24

張永泰 and Wing-tai Cheung. "Geometric programming and signal flow graph assisted design of interconnect and analog circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39558526.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Pant, Pankaj. "Automated diagnosis of path delay faults in digital integrated circuits." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13556.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

Shana'a, Osama K. "Circuit Implementation of a High-speed Continuous-time Current-mode Field Programmable Analog Array (FPAA)." PDXScholar, 1996. https://pdxscholar.library.pdx.edu/open_access_etds/5103.

Full text

Abstract:

The growing interest in programmable analog circuits has led to the development of Field Programmable Analog Arrays (FPAAs). An FPAA consists of: 1) a programmable cell that can be reconfigured to perform several analog functions. 2) an architecture that interconnects a number of copies of the programmable cell. In this thesis, the full monolithic circuit implementation of the analog part of the programmable cell is presented. Chapter I gives an introduction to the idea of FPAA and introduces the FPAA architecture and the cell block diagram. Chapter II deals with the design and verification of a differential current-mode four-quadrant multiplier. The weighting-summing circuit with the normalizing stage is discussed in Chapter III. Chapter IV presents the design of a current-mode low-voltage programmable integratorgain circuit. Programmability was achieved by changing the bias current in the designed circuits; no analog switches were used in the signal path. This shows no effect on the performance of the circuits. The presented programming method, however, relies on the availability of a programmable current source with a storage capability. The design of this current source is discussed in chapter V. Conclusions are summarized in Chapter VI. The presented designs throughout the whole thesis were supported by detailed analytical derivations with the necessary SPICE simulations to verify the performance.

APA, Harvard, Vancouver, ISO, and other styles

27

Forbes, Mark Graham. "Electronic design issues in high-bandwidth parallel optical interfaces to VLSI circuits." Thesis, Heriot-Watt University, 1999. http://hdl.handle.net/10399/598.

Full text

APA, Harvard, Vancouver, ISO, and other styles

28

Wood, Matthew. "Analysis of near fields and radiation of a printed circuit via hole." University of Western Australia. School of Electrical, Electronic and Computer Engineering, 2008. http://theses.library.uwa.edu.au/adt-WU2009.0053.

Full text

Abstract:

Electromagnetic compatibility remains an important topic in the design and manufacturing of printed circuit boards (PCBs). Compatibility of these devices with their surroundings is becoming increasingly difficult as a modern PCB can have hundreds or thousands of parts, operating on many layers, and all at high speed. One such part is a via and its clearance, or via hole, commonly required in multilayer circuits where vertical connections between layers are used. The via hole may be exposed to large electromagnetic fields within the PCB. Although electrically small, the via hole provides a pathway for the fields to excite the exterior, either directly or through coupling to adjacent structures. To quantify this process, the near fields and radiation of an excited via hole are analysed, and are the focus of this thesis. The near fields of the via hole are first decoupled into electric and magnetic fields of the 'static' type. In both cases a series solution for two regions, one outside, and one inside the layers is constructed. The coefficients of the terms of the series are chosen to best satisfy the boundary behaviour of the fields on the conducting surfaces and across the hole. The criteria for assessing quality of the solution is based on the least squares method (LSM). Linear equation systems for both models are derived, and as no numerical integration or discretisation is required, an efficient and robust implementation to find the near fields is developed. Transformation into the far field is then achieved through surface integration of relevant field quantities close to the via hole. The far fields are best viewed as that due to two dipoles, of the magnetic and electric type, with strength and orientation depending on how the via hole is excited. It is shown that the two dipole model is sufficient to find the radiation from a 1mm diameter via hole at a frequency up to 8 GHz. Of further interest is how the choice of via hole dimensions affects the dipole moments and the near fields solved earlier are a key to this understanding.

APA, Harvard, Vancouver, ISO, and other styles

29

Lee, Yim-shu, and 李棪樞. "Modelling, analysis and design of electronic DC to DC conversion circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1988. http://hub.hku.hk/bib/B31231263.

Full text

APA, Harvard, Vancouver, ISO, and other styles

30

Ozdemir, Ersin. "Evolutionary methods for the design of digital electronic circuits and systems." Thesis, Cardiff University, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.326874.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Lee, Yim-Shu. "Modelling, analysis and design of electronic DC to DC conversion circuits /." [Hong Kong : University of Hong Kong], 1988. http://sunzi.lib.hku.hk/hkuto/record.jsp?B12273028.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

Mukherjee, Souvik. "Layout-level Circuit Sizing and Design-for-manufacturability Methods for Embedded RF Passive Circuits." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/16131.

Full text

Abstract:

The emergence of multi-band communications standards, and the fast pace of the consumer electronics markets for wireless/cellular applications emphasize the need for fast design closure. In addition, there is a need for electronic product designers to collaborate with manufacturers, gain essential knowledge regarding the manufacturing facilities and the processes, and apply this knowledge during the design process. In this dissertation, efficient layout-level circuit sizing techniques, and methodologies for design-for-manufacturability have been investigated. For cost-effective fabrication of RF modules on emerging technologies, there is a clear need for design cycle time reduction of passive and active RF modules. This is important since new technologies lack extensive design libraries and layout-level electromagnetic (EM) optimization of RF circuits become the major bottleneck for reduced design time. In addition, the design of multi-band RF circuits requires precise control of design specifications that are partially satisfied due to manufacturing variations, resulting in yield loss. In this work, a broadband modeling and a layout-level sizing technique for embedded inductors/capacitors in multilayer substrate has been presented. The methodology employs artificial neural networks to develop a neuro-model for the embedded passives. Secondly, a layout-level sizing technique for RF passive circuits with quasi-lumped embedded inductors and capacitors has been demonstrated. The sizing technique is based on the circuit augmentation technique and a linear optimization framework. In addition, this dissertation presents a layout-level, multi-domain DFM methodology and yield optimization technique for RF circuits for SOP-based wireless applications. The proposed statistical analysis framework is based on layout segmentation, lumped element modeling, sensitivity analysis, and extraction of probability density functions using convolution methods. The statistical analysis takes into account the effect of thermo-mechanical stress and process variations that are incurred in batch fabrication. Yield enhancement and optimization methods based on joint probability functions and constraint-based convex programming has also been presented. The results in this work have been demonstrated to show good correlation with measurement data.

APA, Harvard, Vancouver, ISO, and other styles

33

Odame, Kofi. "Exploiting device nonlinearity in analog circuit design." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/29751.

Full text

Abstract:

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Butera, Robert; Committee Member: Minch, Bradley; Committee Member: Taylor, David. Part of the SMARTech Electronic Thesis and Dissertation Collection.

APA, Harvard, Vancouver, ISO, and other styles

34

Yang, Meng. "Algorithms in computer-aided design of VLSI circuits." Thesis, Edinburgh Napier University, 2006. http://researchrepository.napier.ac.uk/Output/6493.

Full text

Abstract:

With the increased complexity of Very Large Scale Integrated (VLSI) circuits, Computer Aided Design (CAD) plays an even more important role. Top-down design methodology and layout of VLSI are reviewed. Moreover, previously published algorithms in CAD of VLSI design are outlined. In certain applications, Reed-Muller (RM) forms when implemented with AND/XOR or OR/XNOR logic have shown some attractive advantages over the standard Boolean logic based on AND/OR logic. The RM forms implemented with OR/XNOR logic, known as Dual Forms of Reed-Muller (DFRM), is the Dual form of traditional RM implemented with AND /XOR. Map folding and transformation techniques are presented for the conversion between standard Boolean and DFRM expansions of any polarity. Bidirectional multi-segment computer based conversion algorithms are also proposed for large functions based on the concept of Boolean polarity for canonical product-of-sums Boolean functions. Furthermore, another two tabular based conversion algorithms, serial and parallel tabular techniques, are presented for the conversion of large functions between standard Boolean and DFRM expansions of any polarity. The algorithms were tested for examples of up to 25 variables using the MCNC and IWLS'93 benchmarks. Any n-variable Boolean function can be expressed by a Fixed Polarity Reed-Muller (FPRM) form. In order to have a compact Multi-level MPRM (MMPRM) expansion, a method called on-set table method is developed. The method derives MMPRM expansions directly from FPRM expansions. If searching all polarities of FPRM expansions, the MMPRM expansions with the least number of literals can be obtained. As a result, it is possible to find the best polarity expansion among 2n FPRM expansions instead of searching 2n2n - 1 MPRM expansions within reasonable time for large functions. Furthermore, it uses on-set coefficients only and hence reduces the usage of memory dramatically. Currently, XOR and XNOR gates can be implemented into Look-Up Tables (LUT) of Field Programmable Gate Arrays (FPGAs). However, FPGA placement is categorised to be NP-complete. Efficient placement algorithms are very important to CAD design tools. Two algorithms based on Genetic Algorithm (GA) and GA with Simulated Annealing (SA) are presented for the placement of symmetrical FPGA. Both of algorithms could achieve comparable results to those obtained by Versatile Placement and Routing (VPR) tools in terms of the number of routing channel tracks.

APA, Harvard, Vancouver, ISO, and other styles

35

Cooke, Bradly James. "S-parameter VLSI transmission line analysis." Diss., The University of Arizona, 1989. http://hdl.handle.net/10150/184876.

Full text

Abstract:

This dissertation investigates the implementation of S-parameter based network techniques for the analysis of multiconductor, high speed VLSI integrated circuit and packaging interconnects. The S-parameters can be derived from three categories of input parameters: (1) lossy quasi-static R,L,C and G, (2) lossy frequency dependent (dispersive) R,L,C,G and (3) the propagation constants, Γ, the characteristic impedance, Z(c) and the conductor eigencurrents, I, derived from full wave analysis. The S-parameter network techniques developed allow for: the analysis of periodic waveform excitation, the incorporation of externally measured or calculated scattering parameter data and large system analysis through macro decomposition. The inclusion of non-linear terminations has also been developed.

APA, Harvard, Vancouver, ISO, and other styles

36

Mabe, Nuala Anne. "Information system design for PCB registration process control." Diss., Online access via UMI:, 2007.

Find full text

Abstract:

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007.
Includes bibliographical references.

APA, Harvard, Vancouver, ISO, and other styles

37

Li, Xiaoyong. "Low noise design techniques for radio frequency integrated circuits /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/6013.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

Teru, Agboola Awolola. "Efficient rectenna circuits for microwave wireless power transmission." Thesis, University of Fort Hare, 2010. http://hdl.handle.net/10353/481.

Full text

Abstract:

Miniaturisation has been the holy grail of mobile technology. The ability to move around with our gadgets, especially the ones for communication and entertainment, has been what semiconductor scientists have battled over the past decades. Miniaturisation brings about reduced consumption in power and ease of mobility. However, the main impediment to untethered mobility of our gadgets has been the lack of unlimited power supply. The battery had filled this gap for some time, but due to the increased functionalities of these mobile gadgets, increasing the battery capacity would increase the weight of the device considerably that it would eventually become too heavy to carry around. Moreover, the fact that these batteries need to be recharged means we are still not completely free of power cords. The advent of low powered micro-controllers and sensors has created a huge industry for more powerful devices that consume a lot less power. These devices have encouraged hardware designers to reduce the power consumption of the gadgets. This has encouraged the idea of wireless power transmission on another level. With lots of radio frequency energy all around us, from our cordless phones to the numerous mobile cell sites there has not been a better time to delve more into research on WPT. This study looks at the feasibilities of WPT in small device applications where very low power is consumed to carry out some important functionality. The work done here compared two rectifying circuits’ efficiencies and ways to improve on the overall efficiencies. The results obtained show that the full wave rectifier would be the better option when designing a WPT system as more power can be drawn from the rectenna. The load also had a great role as this determined the amount of power drawn from the circuitry.

APA, Harvard, Vancouver, ISO, and other styles

39

Lee, Kil-Hoon. "Design of signal integrity enhancement circuits." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/37191.

Full text

Abstract:

This dissertation is aimed at examining signal integrity degradation factors and realizing signal integrity enhancement circuits for both wired and wireless communication systems. For wired communication systems, an optical coherent system employing an electrical equalization circuit is studied as a way of extending the transmission distance limited by optical fiber dispersion mechanisms. System simulation of the optical coherent receiver combined with the feed-forward equalizers is performed to determine the design specification of the equalizer circuit. The equalization circuit is designed and implemented in a 0.18 µm complementary metal-oxide semiconductor (CMOS) process and demonstrates the capability to extend the transmission reach of long-haul optical systems over single-mode fiber to 600 km. Additionally, for wireless applications, signal integrity issues found in a full-duplex wireless communication network are examined. Full-duplex wireless systems are subject to interference from their own transmitter leakage signals; thus, a transmitter leakage cancellation circuit is designed and implemented in a 0.18 µm CMOS technology. The proposed cancellation circuit is integrated with a low-noise amplifier and demonstrates over 20 dB of transmitter leakage signal suppression.

APA, Harvard, Vancouver, ISO, and other styles

40

Sykes, Robert Philip. "Definition study, design and development of a firing unit to initiate two pyrotechnic chains." Thesis, Cape Technikon, 1988. http://hdl.handle.net/20.500.11838/1086.

Full text

Abstract:

Thesis (Masters Diploma (Electrical Engineering)--Cape Technikon, Cape Town, 1988
The subject of this thesis is the development of ahighly ruggedised, reliable electronic circuit. The circuit is to be used for the initiation of fuze heads and to charge a capacitor for later use in apyrotechnic chain. This circuit and its associated packaging will be called the firing unit. The thesis can be broadly divided into the following facets. I. The definition study, which defines what is needed and proposed means of achieving the customer requirements. 11. The design of the electronic circuitry in the system. Ii!. The design of the packaging containing the electronics. Iv. Adaptation of environmental testing, to verify system design. V. Implementation of environmental testing. Vi. Reliability analysis. Vii. Failure analysis and the determination of the effect of the supposed failure. Actions vto vii were used as inputs to improve 11 and ill, so achieving optimum performance and safety. The whole system was designed with the overriding objective of reliability and safety of personnel and equipment.

APA, Harvard, Vancouver, ISO, and other styles

41

Son, Kyung-Im. "A multi-class, multi-dimensional classifier as a topology selector for analog circuit design / by Kyung-Im Son." Thesis, Connect to this title online; UW restricted, 1998. http://hdl.handle.net/1773/5919.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Thompson, Adrian. "Hardware evolution : automatic design of electronic circuits in reconfigurable hardware by artificial evolution." Thesis, University of Sussex, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.360588.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Pant, Mondira Deb. "An architectural approach to inductive noise issues in GSI circuits." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13555.

Full text

APA, Harvard, Vancouver, ISO, and other styles

44

Manzan, Junior Donato. "Sensor polimerico de umidade relativa com circuito condicionador de sinais integrado." [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/262033.

Full text

Abstract:

Orientador: Carlos Alberto dos Reis Filho
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e Computação
Made available in DSpace on 2018-08-05T22:28:31Z (GMT). No. of bitstreams: 1 ManzanJunior_Donato_M.pdf: 1716370 bytes, checksum: 70e88e04a73f17039cb0ea8597b7b0cc (MD5) Previous issue date: 2005
Resumo: Este trabalho descreve o desenvolvimento de um sensor de umidade relativa que tem como elemento sensor um polímero (poli(óxido de etileno-co-epicloridrina)84:16), cuja condutividade varia com a umidade. O polímero foi depositado por casting sobre um substrato cerâmico sobre o qual, por sua vez, foram depositados dois eletrodos em forma interdigitada aos quais é aplicada uma corrente alternada com forma de onda quadrada e amplitude DC nula. Este sinal de excitação é produzido por um circuito integrado que também realiza a leitura da tensão nos terminais do eletrodo. Além disto, o circuito contém um sensor de temperatura cuja informação é necessária para a correta leitura da umidade. Amostras do circuito integrado, cujo projeto é parte deste trabalho, foram fabricadas em tecnologia CMOS 0,35um e caracterizadas juntamente com o elemento sensor. Os resultados mais relevantes da caracterização do sensor desenvolvido são: Faixa de medição: máx 90%RH para evitar condensação; Sensibilidade do elemento sensor: 188,83W/%RH a 55%RH; Histerese: 3,4% a 55%RH; Temperatura de operação: 0 a 60oC; Tempo de resposta: +/-30s. A principal contribuição deste trabalho reside na proposição de um sensor de umidade que é composto de um elemento sensor polimérico e de um circuito integrado que realiza o condicionamento e leitura dos sinais envolvidos, constituindo deste modo uma solução robusta e de baixo custo
Abstract: This work describes the development of a relative-humidity sensor, which uses as sensing element a polymer (poly(ethylene oxide-co-epichlorohydrin)84:16) whose conductivity varies with humidity. The polymer was deposited by casting over a ceramic substrate, on which two interdigitized electrodes were previously deposited. An integrated circuit, also developed as part of the work, provides a square wave current with no DC component as excitation signal to the electrodes and reads the voltage across them. The developed integrated circuit also includes a temperature sensor, whose produced signal is used to yield the correct humidity measurement. Samples of the integrated circuit were fabricated in 0.35µm CMOS technology and were characterized together with the sensing element. The most relevant characteristics of the developed humidity sensor are: Measuring range: 90%RH max, to avoid condensing; Sensor element sensitivity: 188,83W/%RH at 55%RH; Hysteresis: 3,4% at 55%RH; Operating temperature: 0 to 60oC; Response time: +/-30s. The main contribution of this work is the proposition of a humidity sensor, which is based on a compound of a polymeric sensing element that operates in conjunction with an integrated circuit. The developed integrated circuit performs the necessary conditioning of the involved signals, in addition to include a temperature sensor. The developed humidity sensor has proven to be robust and can be produced at a relative low cost
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica

APA, Harvard, Vancouver, ISO, and other styles

45

Younus, Md Iqbal. "Circuit design for low voltage wireless receiver with improved image rejection." Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1095799190.

Full text

Abstract:

Thesis (Ph. D.)--Ohio State University, 2004.
Title from first page of PDF file. Document formatted into pages; contains xv, 133 p.; also includes graphics. Includes bibliographical references (p. 129-133).

APA, Harvard, Vancouver, ISO, and other styles

46

Li, Weiping. "Large-area, low-cost via formation and metallization in multilayer thin film interconnection on Printed Wiring Boards (PWB)." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/19641.

Full text

APA, Harvard, Vancouver, ISO, and other styles

47

Michaelides, Stylianos. "Physics-based process modeling, reliability prediction, and design guidelines for flip-chip devices." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/16028.

Full text

APA, Harvard, Vancouver, ISO, and other styles

48

Barclay, Duncan McL. "A design study for gallium arsenide operational transconductance amplifiers." Thesis, University of York, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.338625.

Full text

APA, Harvard, Vancouver, ISO, and other styles

49

Sah, Puja. "Implementing Digital Logic Design Concepts Using Paper Electronics." Thesis, University of North Texas, 2018. https://digital.library.unt.edu/ark:/67531/metadc1157633/.

Full text

Abstract:

This thesis presents the implementation of some of the basic concepts of digital logic design in a fun and creative way with the help of paper electronics. This involves circuit building on paper using conductive tape or conductive ink and circuit components as electronics craft materials. Paper electronics toolkit called circuit sticker microcontroller which is deployed by a company named Chibitronics and AT89C51 microcontroller were used for the computational functioning of the circuits built on paper. This can be used to teach the fundamentals of digital logic design to the students in their early stage of studies in an attractive way and can help them them gain a better understanding. This thesis can also be helpful in grabbing the attention of high school students and motivate them towards choosing the engineering discipline for their higher studies.

APA, Harvard, Vancouver, ISO, and other styles

50

Bell, Ian M. "Developments in testing and design for test of mixed signal electronic circuits and systems." Thesis, University of Hull, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.441756.

Full text

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!