Academic literature on the topic 'Electronic circuits - simulation'

Continuing improvements in integrated circuit technology have made possible the implementation of complex electronic systems on a single chip. This often requires both analogue and digital signal processing. It is essential to simulate such IC's during the design process to detect errors at an early stage. Unfortunately, the simulators that are currently available are not well-suited to large mixed-signal circuits. This thesis describes the design and development of a new methodology for simulating analogue and digital components in a single, integrated environment. The methodology represents components as behavioural models that are more efficient than the circuit models used in conventional simulators. The signals that flow between models are all represented as piecewise-linear (PWL) waveforms. Since models representing digital and analogue components use the same format to represent their signals, they can be directly connected together. An object-oriented approach was used to create a class hierarchy to implement the component models. This supports rapid development of new models since all models are derived from a common base class and inherit the methods and attributes defined in their parentc lassesT. he signal objectsa re implementedw ith a similar class hierarchy. The development and validation of models representing various digital, analogue and mixed-signal components are described. Comparisons are made between the accuracy and performance of the proposed methodology and several commercial simulators. The development of a Windows-based demonstrations imulation tool called POISE is also described. This permitted models to be tested independently and multiple models to be connected together to form structural models of complex circuits.

In this thesis the ANTICS analogue fault simulation software is described which provides a statistical approach to fault simulation for accurate analogue IC test evaluation. The traditional figure of fault coverage is replaced by the average probability of fault detection. This is later refined by considering the probability of fault occurrence to generate a more realistic, weighted test metric. Two techniques to reduce the fault simulation time are described, both of which show large reductions in simulation time with little loss of accuracy. The final section of the thesis presents an accurate comparison of three test techniques and an evaluation of dynamic supply current monitoring. An increase in fault detection for dynamic supply current monitoring is obtained by removing the DC component of the supply current prior to measurement.

This research project has developed a computer-assisted methodology whereby the temporal and spatial distribution of temperature in thick film circuits fabricated on ceramic substrates may be predicted. The analogy between thermal and electrical systems is used to define a thermal structure in electrical format which is then simulated using ASTEC3 electronic analysis package. Procedures have been developed whereby the three heat transfer mechanisms namely conduction, convection and radiation may be modelled. Models have also been proposed which allow the more important sections of a thermal structure to be analysed in finer detail. These procedures have been used hi the solution of some standard heat flow problems whose solutions have also been obtained by other more conventional techniques for comparison. Programs have been developed which facilitate the presentation of the results in the form of contour-maps or 3-D temperature distribution plots. Software has also been developed which can generate the electrical equivalent description of a device in ASTEC3 syntax. Estimates of the computing times required to carry out electro-thermal simulations of hybrid and VLSI devices have been made. The predicted computation times are feasible. Confirmatory experiments have been carried out in large scale using partially heated samples prepared from printed circuit boards. These were heated electrically and temperature measurements were made using an infrared thermometer. These structures were modelled and simulated using ASTEC3 for comparison. It was found that for an accurate thermal analysis there was a need for reliable data for the thermal conductivity of the glass-fibre laminate and the heat transfer coefficients of convection. Experiments were designed to measure the thermal conductivity of the laminates tangential to the plane of the boards. A standard Lees' disc apparatus was also used to measure this parameter in a direction normal to the boards. A Schlieren optics apparatus was used to study the convection plumes over the surface of the plates in a horizontal position with the heated side facing upwards which provided a significant insight into the flow regime over such surfaces. Values were subsequently determined for the convection coefficients from the boards. Using the measured thermal conductivities of FR4 boards and the estimated convection coefficients, excellent agreement was achieved between the measured and simulated results. Temperature measurements were also conducted at reduced dimensional scale on especially designed thick film resistor samples. The samples were fabricated by R.S.R.E and temperature measurements were carried out using a thermal imaging equipment manufactured by AGEMA. Again the Schlieren apparatus was used to observe the convection plumes forming over the devices which led to a better understanding of the heat transfer mechanism from such devices. These observations were then used to estimate the natural convection coefficients from the surface of horizontally positioned resistor samples which were then included in the ASTEC3 model of the devices. The subsequent ASTEC3 thermal simulation showed an excellent agreement with the measured temperature profile.