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1
Wang, Yong. "Frequency domain coupled circuit-electromagnetic simulation /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/6071.
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Taib, Soib Bin. "Simulation of power electronic circuits in modified SPICE2." Thesis, University of Bradford, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.292322.
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Na, Nanju. "Modeling and simulation of planes in electronic packages." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/14812.
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Sabzavari, Abbas Mostafavi. "Fault simulation and diagnosis in analog electronic systems." Thesis, University of Exeter, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.328233.
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Long, David Ian. "Behavioural simulation of mixed analogue/digital circuits." Thesis, Bournemouth University, 1996. http://eprints.bournemouth.ac.uk/278/.
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Continuing improvements in integrated circuit technology have made possible the implementation of complex electronic systems on a single chip. This often requires both analogue and digital signal processing. It is essential to simulate such IC's during the design process to detect errors at an early stage. Unfortunately, the simulators that are currently available are not well-suited to large mixed-signal circuits. This thesis describes the design and development of a new methodology for simulating analogue and digital components in a single, integrated environment. The methodology represents components as behavioural models that are more efficient than the circuit models used in conventional simulators. The signals that flow between models are all represented as piecewise-linear (PWL) waveforms. Since models representing digital and analogue components use the same format to represent their signals, they can be directly connected together. An object-oriented approach was used to create a class hierarchy to implement the component models. This supports rapid development of new models since all models are derived from a common base class and inherit the methods and attributes defined in their parentc lassesT. he signal objectsa re implementedw ith a similar class hierarchy. The development and validation of models representing various digital, analogue and mixed-signal components are described. Comparisons are made between the accuracy and performance of the proposed methodology and several commercial simulators. The development of a Windows-based demonstrations imulation tool called POISE is also described. This permitted models to be tested independently and multiple models to be connected together to form structural models of complex circuits.
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Hou, Junwei. "Concurrent fault simulation for mixed-signal circuits." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15735.
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Spinks, Stephen James. "Fault simulation for structural testing of analogue integrated circuits." Thesis, University of Hull, 1998. http://hydra.hull.ac.uk/resources/hull:8047.
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In this thesis the ANTICS analogue fault simulation software is described which provides a statistical approach to fault simulation for accurate analogue IC test evaluation. The traditional figure of fault coverage is replaced by the average probability of fault detection. This is later refined by considering the probability of fault occurrence to generate a more realistic, weighted test metric. Two techniques to reduce the fault simulation time are described, both of which show large reductions in simulation time with little loss of accuracy. The final section of the thesis presents an accurate comparison of three test techniques and an evaluation of dynamic supply current monitoring. An increase in fault detection for dynamic supply current monitoring is obtained by removing the DC component of the supply current prior to measurement.
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Natarajan, Ekanathan Palamadai. "KLU--a high performance sparse linear solver for circuit simulation problems." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0011721.
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Sarvar, Farhad. "Determination and simulation of the heat transfer characteristics of electronic assemblies." Thesis, University of South Wales, 1992. https://pure.southwales.ac.uk/en/studentthesis/determination-and-simulation-of-the-heat-transfer-characteristics-of-electronic-assemblies(55c0f76d-ca94-4344-a268-f8817df44ccf).html.
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This research project has developed a computer-assisted methodology whereby the temporal and spatial distribution of temperature in thick film circuits fabricated on ceramic substrates may be predicted. The analogy between thermal and electrical systems is used to define a thermal structure in electrical format which is then simulated using ASTEC3 electronic analysis package. Procedures have been developed whereby the three heat transfer mechanisms namely conduction, convection and radiation may be modelled. Models have also been proposed which allow the more important sections of a thermal structure to be analysed in finer detail. These procedures have been used hi the solution of some standard heat flow problems whose solutions have also been obtained by other more conventional techniques for comparison. Programs have been developed which facilitate the presentation of the results in the form of contour-maps or 3-D temperature distribution plots. Software has also been developed which can generate the electrical equivalent description of a device in ASTEC3 syntax. Estimates of the computing times required to carry out electro-thermal simulations of hybrid and VLSI devices have been made. The predicted computation times are feasible. Confirmatory experiments have been carried out in large scale using partially heated samples prepared from printed circuit boards. These were heated electrically and temperature measurements were made using an infrared thermometer. These structures were modelled and simulated using ASTEC3 for comparison. It was found that for an accurate thermal analysis there was a need for reliable data for the thermal conductivity of the glass-fibre laminate and the heat transfer coefficients of convection. Experiments were designed to measure the thermal conductivity of the laminates tangential to the plane of the boards. A standard Lees' disc apparatus was also used to measure this parameter in a direction normal to the boards. A Schlieren optics apparatus was used to study the convection plumes over the surface of the plates in a horizontal position with the heated side facing upwards which provided a significant insight into the flow regime over such surfaces. Values were subsequently determined for the convection coefficients from the boards. Using the measured thermal conductivities of FR4 boards and the estimated convection coefficients, excellent agreement was achieved between the measured and simulated results. Temperature measurements were also conducted at reduced dimensional scale on especially designed thick film resistor samples. The samples were fabricated by R.S.R.E and temperature measurements were carried out using a thermal imaging equipment manufactured by AGEMA. Again the Schlieren apparatus was used to observe the convection plumes forming over the devices which led to a better understanding of the heat transfer mechanism from such devices. These observations were then used to estimate the natural convection coefficients from the surface of horizontally positioned resistor samples which were then included in the ASTEC3 model of the devices. The subsequent ASTEC3 thermal simulation showed an excellent agreement with the measured temperature profile.
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Stiteler, Michael Ross. "An automated system for measuring PWB/PWBA warpage during simulation of the infrared reflow and wave soldering processes, and during operational thermal cycling." Thesis, Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/17099.
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Liao, Jen-Chyi. "Computer simulation of multiple coupled transmission lines in electronic packaging application." Diss., The University of Arizona, 1989. http://hdl.handle.net/10150/184659.
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A method for simulating the transient responses of networks containing lossless transmission lines and lumped parameter elements of circuits, both linear and nonlinear, has been developed and investigated. The method combines the technique of network analysis and that of modal decomposition of transmission lines. A prototype computer simulation program, called UANTL, based on the developed algorithm has been implemented. Several example networks have been simulated using this program. The results have been compared with those generated by the well known circuit simulator program called SPICE. UANTL has shown several advantages over SPICE in simulating the transient responses of networks containing transmission lines. A description of the prototype version of UANTL and a summary of the results of numerical experiments are included.
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Peckel, Marcos David. "A MOS delay model for switch-level simulation /." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65990.
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Lim, Boey Yean. "Fault simulation for supply current testing of bridging faults in CMOS circuits." Thesis, Virginia Tech, 1989. http://hdl.handle.net/10919/44122.
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<p>The objective of this research is to develop and implement a method for fault simulation that
considers bridging faults in CMOS circuits that are tested using supply current monitoring. The
discussion is restricted to single fault detection in CMOS combinational circuits. A CMOS circuit
is represented by a two-level hierarchy. At the higher level, the circuit is partitioned into modules
based on the circuit layout. Each module is represented at the lower level by a switch-level graph.
This representation has the advantage of structural accuracy at the lower level and efficient logic
propagation at the higher level. Based on a module's switch-level graph, an exhaustive list of
bridging faults corresponding to certain physical defects can be derived. Fault collapsing techniques
are used to optimize the exhaustive fault list. There are two major processes in this bridging fault
simulation program, logic simulation and fault sensitization at switch level. The simulation program
uses preprocessing and bit-wise parallelism to minimize computation time. At the end of fault
simulation, a fault coverage and fault matrices suitable for test grading and fault diagnosis are
produced for each test set.</p>
<p>
This research also identifies types of CMOS modules and uses them to analyze test generation
for bridging faults. The completeness and minimality of switch-level test sets are considered for
general series-parallel (GSP) modules.
Finally, several single-module circuits are simulated using gate-level, switch-level and random
test sets, and their effectiveness is compared.</p><br>Master of Science
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Peter, Geoffrey J. M. "Numerical simulation of CTE mismatch and thermal-structural stresses in the design of interconnects /." Full text open access at:, 2001. http://content.ohsu.edu/u?/etd,235.
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Zhong, Shida. "Fault modelling and accelerated simulation of integrated circuits manufacturing defects under process variation." Thesis, University of Southampton, 2013. https://eprints.soton.ac.uk/349929/.
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As silicon manufacturing process scales to and beyond the 65-nm node, process variation can no longer be ignored. The impact of process variation on integrated circuit performance and power has received significant research input. Variation-aware test, on the other hand, is a relatively new research area that is currently receiving attention worldwide. Research has shown that test without considering process variation may lead to loss of test quality. Fault modelling and simulation serve as a backbone of manufacturing test. This thesis is concerned with developing efficient fault modelling techniques and simulation methodologies that take into account the effect of process variation on manufacturing defects with particular emphasis on resistive bridges and resistive opens. The first contribution of this thesis addresses the problem of long computation time required to generate logic fault of resistive bridges under process variation by developing a fast and accurate modelling technique to model logic fault behaviour of resistive bridges.The new technique is implemented by employing two efficient voltage calculation algorithms to calculate the logic threshold voltage of driven gates and critical resistance of a fault-site to enable the computation of bridge logic faults without using SPICE. Simulation results show that the technique is fast (on average 53 times faster) and accurate (worst case is 2.64% error) when compared with HSPICE. The second contribution analyses the complexity of delay fault simulation of resistive bridges to reduce the computation time of delay fault when considering process variation. An accelerated delay fault simulation methodology of resistive bridges is developed by employing a three-step strategy to speed up the calculation of transient gate output voltage which is needed to accurately compute delay faults. Simulation results show that the methodology is on average 17.4 times faster, with 5.2% error in accuracy, when compared with HSPICE. The final contribution presents an accelerated simulation methodology of resistive opens to address the problem of long simulation time of delay fault when considering process variation. The methodology is implemented by using two efficient algorithms to accelerate the computation of transient gate output voltage and timing critical resistance of an open fault-site. Simulation results show that the methodology is on average up to 52 times faster than HSPICE, with 4.2% error in accuracy.
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Burnette, David G. "A graphical representation for VHDL models." Thesis, Virginia Tech, 1988. http://hdl.handle.net/10919/43381.
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This paper describes a graphical representation technique for models in VHDL. The graphical representation is an extension of the Process Model Graph described in [1]. The Process Model Graph has representations for concurrent processes and signals. The representation described here, referred to as the Modified Process Model Graph, adds several new constructs to handle more features of VHDL. These new constructs include: variables inside process blocks, a visual notation for sensitivity lists, and a clear visual indication of the interface to an object. A software tool, called VHDLCad* (c)* * , has been developed that uses produces VHDL source code interactively from the graphical representation. The tool allows the user to use pre-defined modules, or create new modules and place them in the library. With the benefit of a graphical representation, a menu-driven system and re-usable code, VHDLCad can improve the productivity of VHDL modelers.
*VHDLCad is a trademark of David G. Burnette.
**Copyright 1988 by David G. Burnette. All rights reserved<br>Master of Science
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Wu, Xiaohua. "Field simulation and calibration in external electro-optic sampling /." *McMaster only, 1996.
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Khordoc, Karim. "A MOS switch-level simulator with delay calculation /." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65461.
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Janczak, Teresa Krystyna. "Estimation of Jitter Effects in Oscillators and Frequency Synthesizers Due to Prototypical Perturbation Sources." Diss., Tucson, Arizona : University of Arizona, 2005. http://etd.library.arizona.edu/etd/GetFileServlet?file=file:///data1/pdf/etd/azu%5Fetd%5F1094%5F1%5Fm.pdf&type=application/pdf.
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Schneider, Eric [Verfasser], and Hans-Joachim [Akademischer Betreuer] Wunderlich. "Multi-level simulation of nano-electronic digital circuits on GPUs / Eric Schneider ; Betreuer: Hans-Joachim Wunderlich." Stuttgart : Universitätsbibliothek der Universität Stuttgart, 2019. http://d-nb.info/1192305264/34.
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Pansare, Manoj M. "Modeling and simulation of analog devices using PRECISE." Thesis, Virginia Tech, 1988. http://hdl.handle.net/10919/43263.
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The design and development of computer models to simulate analog devices and their effects on circuit applications has been investigated at length. The focus of this research is the development of theoretical and computer models for discrete devices using the popular simulator PRECISE, PRogram for Evaluating Circuits in an Interactive Simulation Environment [3], using a new method for model construction.
This new method develops a model approximating the mathematics of the simulation via perturbations and iterations [19]. The models developed by the new method in each case yield a minimum simulation accuracy of 90 percent in circuit applications. In comparison, models developed by the conventional method, which uses measured data to complete physical constructs of SPICE 2G.6 [5], offer a lower accuracy for the same circuits. Hence, the new method is more effective than the old method and also much faster, since the model generation process is now automated and does not require time-consuming manual measurements and calculations spread out over a long period of time.
With further development, a computer model can also be developed for the theoretical model presented in this thesis for the Gallium Arsenide Metal Semiconductor Field Effect Transistor (GaAs MESFET) device using the same methodology that has been used to develop the computer model for the Bipolar Junction Transistor (BUT) device. Hence this research, in addition to developing a library of a hundred and fifty odd successful models in the PRECISE and SPICE formats for the diode and BUT, can also be used to develop a new model for the GaAs MESFET, which would make both PRECISE and SPICE easier and more user friendly as circuit simulators.<br>Master of Science
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SILVA, WANDERLEI M. da. "Contribuição ao modelamento e simulação de motores com imãs permanentes e comutação eletrônica de alta rotação." reponame:Repositório Institucional do IPEN, 1998. http://repositorio.ipen.br:8080/xmlui/handle/123456789/11642.
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Schuster, Christian. "Simulation, analysis, and parameter extraction of electronic components and circuits using the finite difference time domain method /." Zürich, 1999. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=13522.
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Hamelin, Thibault. "Validation d'un nouveau logiciel de simulation tridimensionnel du Multipactor par le calcul et l'expérimentation." Thesis, Paris 11, 2015. http://www.theses.fr/2015PA112122/document.
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Le multipactor est un phénomène parasite qui se produit dans les dispositifs où l'on transmet une onde hyperfréquence sous vide tels que les tubes électroniques à vide, les cavités résonnantes pour accélérateurs de particules et les circuits micro-ondes à bord des satellites. Il consiste en une avalanche d'électrons mis en mouvement par un champ hyperfréquence. La simulation du multipactor est cruciale dans tout design de structure HF sous vide. Les géométries complexes 3D d'objets imposent de posséder des outils de simulations tridimensionnels pour prédire ce phénomène. Le premier travail de cette thèse a consisté à valider un logiciel de simulation 3D du multipactor, Musicc3D, à la fois par le calcul et l'expérimentation. Une étude théorique à une dimension ainsi qu'une simulation 2D éprouvée ont été réalisées et les résultats du logiciel Musicc3D ont été favorablement confrontés à leurs résultats. Des règles de définition du maillage 3D ont été établies pour un bon fonctionnement de la simulation 3D. Toujours pour valider la simulation, l'ensemble des cavités accélératrices construites par l'IPNO ces dernières années a été simulé et favorablement comparé aux observations de barrières de multipactor quand elles existaient. Dans le but d'exploiter les prédictions de la simulation 3D, mais aussi de la valider et enfin d'être capable de qualifier différents matériaux et/ou états de surfaces, une cavité résonnante équipée de mesures dédiées au multipactor a été construite. Les premiers résultats obtenus avec cette cavité ont été favorablement comparés à la simulation<br>Multipacting is a parasitic phenomenon and extremely detrimental in devices where there is a ultra high frequency wave transmitted in a vacuum environment such as vacuum electron tubes, resonant cavities for particle accelerators and microwave circuits on board of satellites. It consists of an avalanche of electrons put in motion by a microwave field. Multipacting simulation is crucial in any HF structure design. The complex 3D geometrics obligates to have three-dimensional simulation tools to predict this phenomenon. The first study in this thesis consisted in validating a 3D simulation software of Multipacting, Musicc3D, by calculation and experimentation. A theoretical study with one dimension and a a tested 2D simulation were carried out and the results of the software Musicc3D were favorably confronted to their results. 3D grid definition rules were established for the proper working of the 3D simulation. Also to validate the simulation, the whole of the park of accelerating cavities built by the IPNO these last years was simulated and favorably compared with the observations of barriers of Multipacting when they existed. With an aim of exploiting the predictions of the 3D simulation, but also to validate it and finally be able to qualify various materials and/or state of surfaces, a resonant cavity equipped with measurements dedicated for Multipacting was built. The first results obtained with this cavity were favorably compared to the simulation
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Mehta, Shilpa D. "A circuit model BOSS simulation of nonlinear effects in long distance fiber optic systems." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-07112009-040230/.
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Choi, Jae Young. "Modeling and simulation for signal and power integrity of electronic packages." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45885.
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The objective of this dissertation is to develop electrical modeling and co-simulation methodologies for signal and power integrity of package and board applications. The dissertation includes 1) the application of the finite element method to the optimization for decoupling capacitor selection and placement on a power delivery network (PDN), 2) the development of a PDN modeling method effective for multidimensional and multilayer geometries, 3) the analysis and modeling of return path discontinuities (RPDs), and 4) the implementation of the absorbing boundary condition for PDN modeling.
The optimization technique for selection and placement of decoupling capacitors uses a genetic algorithm (GA) and the multilayer finite element method (MFEM), a PDN modeling method using FEM. The GA is customized for the decoupling problem to enhance the convergence speed of the optimization. The mathematical modifications necessary for the incorporation of the capacitor model into MFEM is also presented.
The main contribution of this dissertation is the development of a new modeling method, the multilayer triangular element method (MTEM), for power/ground planes of a PDN. MTEM creates a surface mesh on each plane-pair using dual graphs; a non-uniform triangular mesh (Delaunay triangulation) and its orthogonal counterpart (Voronoi diagram), to which electromagnetic and equivalent circuit concepts are applied. The non-uniform triangulation is especially efficient for discretizing multidimensional and irregular geometries which are common in package and board PDNs. Moreover, MTEM generates a sparse, banded, and symmetric system matrix, which enables efficient computations. For a given plane-pair, MTEM extracts an equivalent circuit that is consistent with the physics-based planar-circuit model of a plane-pair. Thus, the values of the lumped elements can be simply calculated from the physical parameters, such as material properties and mesh geometries of each unit-cell. Consequently, the modeling of MTEM is flexible and easy to modify for further extensions, such as the incorporation of external circuits, e.g. decoupling capacitors and vertical interconnects.
Power and ground planes provide paths for the return current of signal traces. Typically, planes have discontinuities such as via holes, plane cutouts, and split planes that disturb flow of signal return currents. At the discontinuity, return currents have to detour or switch to different layers, causing signal and power integrity problems. Therefore, a separate analysis of signal interconnects will neglect the significant coupling with a PDN, and the result will not be reliable. In this dissertation, the co-simulation of the signal and power integrity is presented focusing on the modeling of RPDs created by split planes, apertures, and vias.
Plane resonance is one of the main sources of power integrity problems in package and board PDNs. A number of techniques have been developed and published in literature to reduce or prevent the resonance of a plane-pair. One of the techniques is to surround plane-pair edges with absorbing material that effectively damps the outgoing parallel-plate wave and minimizes the reflection. To model this behavior, the boundary condition of MTEM needs to be changed from its original form, the open-circuit boundary condition. In this dissertation, the application of the 1st order absorbing boundary condition to MTEM is presented.
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Roumeliotis, Emmanuel. "Multi-processor logic simulation at the chip level." Diss., Virginia Polytechnic Institute and State University, 1986. http://hdl.handle.net/10919/71180.
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This dissertation presents the design and development of a multi-processor logic simulator. After an introduction to parallel processing, the concept of distributed simulation is described as well as the possibility of deadlock in a distributed system. It is proven that the proposed system does not deadlock. Next, the modeling techniques are discussed along with the timing mechanisms used for logic simulation. A new approach, namely process oriented simulation is studied in depth. It is shown that modeling for this kind of simulation is more efficient regarding modeling ease, computer memory and simulation time, than existing simulation methods. The hardware design of the multi-processor system and the algorithms for synchronization and signal interchange between the processors are presented next. An algorithm for an efficient partitioning of the digital network to be simulated among the processors of the system is also described. Apart from the simulation of a single digital network, the simulator can also be used for fault simulation and design verification. Regarding fault simulation, the fault injection and fault detection techniques are presented. The experimental results obtained by running the multi-processor simulator are compared with the theoretical estimates as well as with results obtained by other multi-processor systems. The comparison shows that the proposed simulator exhibits the estimated performance. Finally, the design of a common bus interface is given. This interface will connect the processors of the system directly without the intervention of a hard disk which was used for the development and testing of the system.<br>Ph. D.
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Andrade, Denis Furtado de. "Otimização das câmeras astronômicas do instrumento Brazilian Tunable Filter Imager." Universidade de São Paulo, 2016. http://www.teses.usp.br/teses/disponiveis/3/3142/tde-26082016-160404/.
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Este trabalho apresenta os resultados obtidos no processo de otimização realizado nas câmeras astronômicas do instrumento BTFI (Brazilan Tunable Filter Imager) instalado no telescópio SOAR, no Chile, para reduzir o ruído nos sinais. O instrumento BTFI opera com duas câmeras astronômicas de alto desempenho que utilizam detectores de imagens denominados EMCCDs. Esses detectores são sensores de imagem baseados em dispositivos de carga acoplada (CCDs) otimizados por um estágio integrado de multiplicação de elétrons por avalanche. Essa característica permite atingir ao mesmo tempo altas taxas de leitura (10 MHz) e níveis de ruído muito baixos (<1 elétron/pixel). Detectores CCD exigem temperaturas de operação da ordem de -100oC para operar com baixo ruído, o que demanda uma série de especificações técnicas quanto ao projeto da câmera. O trabalho aqui exposto fundamentou-se na otimização de aspectos mecânicos e eletrônicos de câmeras astronômicas com o intuito de se obter a melhor relação sinal-ruído, mostrando a importância do correto desenho mecânico (do ponto de vista térmico) e sua influência no comportamento eletrônico da câmera. São expostos os resultados obtidos com as duas câmeras em laboratório, os métodos e processos de caracterização utilizados, bem como as simulações térmicas e experimentos realizados em laboratório. Com as técnicas empregadas alcançou-se níveis de ruído total menores que 0,18 elétrons/pixel/segundo para exposições de 10 segundos. Os resultados atingidos foram observados nas duas câmeras do instrumento BTFI e foram validados em laboratório, onde demonstraram estabilidade durante 71 dias consecutivos. Por fim, é mostrada uma caracterização comparativa entre as duas câmeras quanto aos níveis de ruídos, ganho, estabilidade, eficiência quântica, linearidade e relação sinal-ruído.<br>This work presents results of the optimization performed in the astronomical cameras from the Brazilian Tunable Filter Imager (BTFI), instrument for the SOAR Telescope in Chile, in order to reduce the signals noise. The BTFI instrument has two highperformance cameras equipped with detectors named EMCCDs, which are image sensors based on charge-coupled devices (CCDs) optimized by an electron multiplication integrated stage. This feature enables to achieve high readout rates (10 MHz) and very low noise levels (<1 electron/pixel) at the same time. CCD detectors demand running temperatures of about -100,sup>oC for very low noise operation, which requires a series of technical specifications for the camera design. The work shown here is based in the optimization of the mechanical and electronic aspects for the astronomical cameras, in order to obtain the best signal to noise ratio, showing the importance of the correct mechanical design (from the thermal point of view) and its influence on the camera electronic behavior. The laboratory results obtained with the two cameras, the characterization procedures, as well as the thermal simulations and laboratory ratification experiments that allowed achieve the results presented are exposed. Using such techniques it was possible to achieve total noise levels lower than 0.18 electron/pixel/second for 10 seconds of exposure time. The results achieved were observed in both BTFI cameras and were validated in laboratory showing 71 consecutive days of stability. Finally it is shown a comparative characterization between both cameras in: noise and gain levels, stability, quantum efficiency, linearity and signal to noise ratio.
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MASOTTI, PAULO H. F. "Desenvolvimento de um cartao digital para simulacao da variacao do periodo em reatores." reponame:Repositório Institucional do IPEN, 1999. http://repositorio.ipen.br:8080/xmlui/handle/123456789/10747.
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Chaudhari, Gunavant Dinkar. "Simulation and emulation of massively parallel processor for solving constraint satisfaction problems based on oracles." PDXScholar, 2011. https://pdxscholar.library.pdx.edu/open_access_etds/11.
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Most part of my thesis is devoted to efficient automated logic synthesis of oracle processors. These Oracle Processors are of interest to several modern technologies, including Scheduling and Allocation, Image Processing and Robot Vision, Computer Aided Design, Games and Puzzles, and Cellular Automata, but so far the most important practical application is to build logic circuits to solve various practical Constraint Satisfaction Problems in Intelligent Robotics. For instance, robot path planning can be reduced to Satisfiability. In short, an oracle is a circuit that has some proposition of solution on the inputs and answers yes/no to this proposition. In other language, it is a predicate or a concept-checking machine. Oracles have many applications in AI and theoretical computer science but so far they were not used much in hardware architectures. Systematic logic synthesis methodologies for oracle circuits were so far not a subject of a special research. It is not known how big advantages these processors will bring when compared to parallel processing with CUDA/GPU processors, or standard PC processing. My interest in this thesis is only in architectural and logic synthesis aspects and not in physical (technological) design aspects of these circuits. In future, these circuits will be realized using reversible, nano and some new technologies, but the interest in this thesis is not in the future realization technologies. We want just to answer the following question: Is there any speed advantage of the new oracle-based architectures, when compared with standard serial or parallel processors?
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Tang, Xinghai. "Intrinsic and extrinsic parameter fluctuation limits on gigascale integration (GSI)." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/13305.
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SILVA, WANDERLEI M. da. "Proposta de novas topologias de conversores 'C-DUMP' para o acionamento de motores e geradores de relutancia chaveados." reponame:Repositório Institucional do IPEN, 2004. http://repositorio.ipen.br:8080/xmlui/handle/123456789/11336.
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Kimoto, Daiki. "Characterization and Modeling of SiC Integrated Circuits for Harsh Environment." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-223422.
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Elektronik för extrema miljöer, som kan användas vid hög temperatur, hög strålning och omgivning med frätande gaser, har varit starkt önskvärd vid utforskning av rymden och övervakning av kärnreaktorer. Kiselkarbid (SiC) är en av kandidaterna inom material för extrema miljöer på grund av sin höga temperatur- och höga strålnings-tolerans. Syftet med denna avhandling är att karakterisera 4H-SiC MOSFETar vid hög temperatur och att konstruera SPICE modeller för 4H-SiC MOSFETar. MOSFET-transistorer karakteriserades till 500°C. Med användande av karaktäristik för en 4H-SiC NMOSFET med L/W = 10 µm / 50 µm, anpassades en SPICE LEVEL 2 kretsmodell. Modellen beskriver DC karakteristiska av 4H- SiC MOSFETar mellan 25ºC och 450ºC. Baserat på SPICE-kretsmodellen simulerades egenskaper för operationsförstärkare och digitala inverterar. Därutöver analyserades driften av pseudo-CMOS vid hög temperatur och principen för konstruktion av pseudo-CMOS föreslogs. Arean och utbytet (s.k. yield) av pseudo-CMOS integrerade kretsar uppskattades och det visar sig att SiC pseudo-CMOS integrerade kretsar kan använda mindre area än SiC CMOS integrerade kretsar.<br>Harsh environment electronics, which can be operated at high-temperature, high-radiation, and corrosive gas environment, has been strongly desired in space exploration and monitoring of nuclear reactors. Silicon Carbide (SiC) is one of the candidates of materials for harsh environment electronics because of its high-temperature and high-radiation tolerance. The objective of this thesis is to characterize 4H-SiC MOSFETs at high- temperature and to construct SPICE models of the 4H-SiC MOSFETs. The MOSFET devices were characterized up to 500ºC. Using the characteristic of a 4H-SiC NMOSFET with L/W = 10 µm/50 µm, a SPICE LEVEL 2 circuit model was constructed. This model describes the DC characteristic of the 4H-SiC MOSFETs in the range of 25 – 450ºC. Based on the SPICE circuit model, the characteristics of operational amplifiers and digital inverters were simulated. Furthermore, the operation of pseudo-CMOS at high-temperature was analyzed and the operation principle of pseudo-CMOS was suggested. The device area and yield of pseudo-CMOS integrated circuits were estimated and it is shown that SiC pseudo-CMOS integrated circuits can use less area than SiC CMOS integrated circuits.
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Ferrere, Thomas. "Assertions and measurements for mixed-signal simulation." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAM050.
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Cette thèse porte sur le monitorage des simulations de circuits en signaux mixtes. Dans le domaine de la vérification de matériel, l'utilisation de formalismes déclaratifs pour la specification, dans le cadre de la validation par simulation, s'est installée dans la pratique courante. Cependant, le manque de fonctionnalités visant à spécifier les comportements asynchrones, ou l'intégration insuffisante des résultats de la vérification, rend les language d'assertions et de mesures inopérants pour la vérification de comportements en signaux mixtes. Nous proposons des outils théoriques et pratiques pour la description et le monitorage de ces comportements, qui comportent des aspects à la fois discrets et continus. Pour cela, nous nous appuyons sur des travaux antérieurs portant sur les extensions temps-réel de la logique temporelle et des expressions régulières. Nous décrivons de nouveaux algorithmes pour calculer la distance entre une trace de simulation et une propriété en logique temporelle données. Une nouvelle procédure de diagnostic est conçue pour déboguer efficacement de telles traces. Le monitorage des comportements continus est ensuite étendu à d'autres formes d'assertions basées sur des expressions régulières. Ces expressions constituent la base de notre language de description de mesures, qui permet de définir conjointement la mesure et les intervals temporels sur lesquels cette mesure doit être prise. Nous montrons comment d'autres mesures, déjà mises en œuvre dans les simulateurs analogiques peuvent être importées dans les descriptions digitales. Ceci permet d'étendre vers le domaine en signaux mixtes les approches hiérarchiques utilisées en vérification de circuits digitaux<br>This thesis is concerned with the monitoring of mixed-signal circuit simulations. In the field of hardware verification, the use of declarative property languages in combination with simulation is now standard practice. However the lack of features to specify asynchronous behaviors, or the insufficient integration of verification results, makes existing assertion and measurement languages unable to enforce mixed-signal requirements. We propose several theoretical and practical tools for the description and automatic monitoring of such behaviors, that feature both discrete and continuous aspects. For this we build on previous work on real-time extensions of temporal logic and regular expressions. We describe new algorithms to compute the distance from some simulation trace to temporal logic specifications, whose complexity is not higher than traditional monitoring. A novel diagnostic procedure is provided in order to efficiently debug such traces. The monitoring of continuous behaviors is then extended to other forms of assertions based on regular expressions. These expressions form the basis of our measurement language, that describes conjointly a measure and the patterns over which that measure should be taken. We show how other measurements implemented in analog circuits simulators can be ported to digital descriptions, this way extending structured verification approaches used for digital designs toward mixed-signal
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Lee, Chris Y. "Full Custom VLSI Design of On-Line Stability Checkers." DigitalCommons@CalPoly, 2011. https://digitalcommons.calpoly.edu/theses/607.
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A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly.
A method for concurrent fault testing called On-line Stability Checking was introduced by Franco and McCluskey [10] to detect reliability failures. Reliability failures initially manifest themselves as delay faults and transient glitching, which become progressively larger over time due to the wearout of conducting metal lines, eventually leading to functional faults. Stability checkers periodically detect reliability failures by monitoring CUT output signals for unstable and late input signals over a time period after the sampling clock edge.
The checkers are tested by applying variable delayed input test patterns to emulate reliability failures. Consequently, configurable delay chains were incorporated into the system to provide variable delays on the input signal lines. The system also includes external test signal ports.
Circuit and layout designs were implemented in the Electric VLSI Design tool [12] and simulated with LTSPICE [13]. Electric provides Design Rule Checking (DRC) and Layout-versus-Schematic (LVS) utilities for verification. Each module was designed in a bottom-up, hierarchical cell-based approach. Functional simulation, DRC and LVS checks were performed at every subsequent higher cell layer in the design hierarchy. The final chip layout was taped out for fabrication on November 29, 2010 and finished parts were received on July 7, 2011 after two manufacturing delays.
Finished packaged parts were successfully verified for functionality based on SPICE simulations. The stability checkers were tested for flip-flop operation, glitch detection and late signal arrival detection. Configurable delay chains were tested to determine delay resolution and uniformity. Actual delay resolution and range measurements show a 3 to 4 times difference compared to simulated values.
The Electric design template created from this project includes basic CMOS logic gates with uniform standard cell heights. The template contains a 40-pin pad ring cell along with the individual pad ring components. EE 431 students would be able to create custom chips that are compatible for fabrication via the MOSIS MEP service. In future work, the template design library can be expanded to include more logic gate variants of various inputs and drive strengths as well as more complex functional modules.
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Souza, Flavilene da Silva. "Extração de energia através da técnica power harvesting baseada em vibrações mecânicas e transdutores piezelétricos." Universidade Estadual Paulista (UNESP), 2018. http://hdl.handle.net/11449/153706.
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Previous issue date: 2018-03-02<br>Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)<br>Neste trabalho foram realizados estudos, análises, simulações e implementações de um sistema de power harvesting utilizando transdutores piezelétricos, com o objetivo de extrair a máxima potência. A fim de alcançar tal objetivo, o sistema mecânico e a interface elétrica foram analisados com foco na quantidade de potência extraída. Com os resultados básicos desses estudos, tem-se que o desempenho de tais sistemas depende da interação eletromecânica, da deformação, da frequência de excitação e da carga conectada. Com exceção do último, esses parâmetros não interferem no modelo tradicional de simulação no SPICE. Para aprimorar os resultados da simulação, foi proposta uma metodologia para a modelagem do sistema mecânico com a interface elétrica, implementada e avaliada em MATLAB/Simulink e em SPICE com VHDL-AMS. Além disso, um novo circuito eletrônico, denominado Conversor Direto CA-CC com Chaveamento Sincronizado - CDCS, foi projetado para maximizar a potência média extraída e reduzir sua dependência com a frequência de excitação e com a carga conectada. Os resultados das simulações foram comparados com dados experimentais para os circuitos eletrônicos retificador em ponte e SSHI em paralelo. A modelagem desenvolvida em SPICE com VHDL-AMS apresentou melhores resultados, pois permite uma modelagem mais precisa dos componentes eletrônicos sem comprometer o domínio mecânico. Comparado com três circuitos existentes na literatura (retificador em ponte, SSHI em paralelo e SECE), o circuito proposto obteve os maiores valores de potência extraída (102 µW) e de eficiência (70 %), além de apresentar resultados satisfatórios na faixa de operação da carga (1 kΩ - 1 MΩ) e largura de banda (6,0 Hz).<br>In this work studies, analysis, simulations and the implementation of power harvesting system using piezoelectric transducer were done aiming to extract its maximum power. In order to achieve this goal, the mechanical system and electrical interface were analyzed especially focused on the amount of power that can be able to extracted. The conclusion of these studies was that the system performance depends of the electromechanical interaction, deformation, excitation frequency and the connected load. Except for the latter, these parameters does not interfered in the standard model by SPICE. To improve the simulation results, a novel methodology for modeling the mechanical system with electrical interface was proposed. It was implemented and evaluated in MATLAB/Simulink and in SPICE with VHDL-AMS. In addition, a new electronic circuit, well know as Direct AC-DC Converter with Synchronous Switch (CDSS), was designed to improve the extract power and the response at the frequency of excitation and the connected load. The simulation results were compared with experimental data for the electronic circuits: bridge rectifier and P-SSHI. The SPICE with VHDL-AMS model offered the best results, since it allows accurate model for the electrical component without compromising the mechanical system. The performance of the proposed circuit was compared with three electronic circuits (bridge rectifier, P-SSHI and SECE). The results show that the proposed circuit presented the higher power extracted (102 μW) and of efficiency (70%). In addition, both the resistance range (1 kΩ - 1 MΩ) and the bandwidth (6,0 Hz) were improved.<br>CAPES: 99999.006504/2015-09
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Fadi, Abdallah el. "Spécification comportementale temporelle dans un simulateur multi-niveaux." Grenoble INPG, 1988. http://www.theses.fr/1988INPG0039.
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Cette thèse aborde les problèmes de la validation automatique dans le domaine CAO de matériels informatiques et électroniques, en liaison avec des techniques de simulation mixte. Le but a été d'établir une méthodologie de spécification comportementale basée sur l'utilisation de primitives logiques et temporelles permettant de conditionner certaines propriétés des systèmes modélises et simulés
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Jalil, Mansoor Abdul. "Theory and simulation of single electron tunnelling circuits." Thesis, University of Cambridge, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.624258.
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Martini, Guilherme Henrique Kaehler. "Filtro digital híbrido para sistemas embarcados de alta potência." Universidade Tecnológica Federal do Paraná, 2013. http://repositorio.utfpr.edu.br/jspui/handle/1/593.
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Esta dissertação trata sobre o projeto, implementação e avaliação de um filtro híbrido para supressão de ruído em sistemas de alta potência. Seu desempenho será otimizado para reduzir a magnitude de ruídos impulsivos, que são comuns em dispositivos de alta potência, como inversores de frequência que controlam motores trifásicos. O filtro híbrido proposto é avaliado empiricamente em um inversor de frequência que é controlado por um sistema embarcado. A abordagem proposta é comparada com abordagens clássicas de filtragem digital como média móvel, filtro de resposta finita ao impulso (FIR) e filtro de resposta infinita ao impulso (IIR).<br>This work presents the project, implementation and evaluation of a hybrid filter used for noise supressing in high power switching converters. It is optimized to reduce impulsive noise that is commonly present in high power devices like frequency inverters that control three-phase motors. The hybrid filter is evaluated empirically in a frequency inverter that is controlled by an embedded system. This approach is compared to classical ones, like the moving average, the finite impulse response (FIR) and the infinite impulse response (IIR) filters.
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Zhou, Dafeng. "Circuit-level modelling and simulation of carbon nanotube devices." Thesis, University of Southampton, 2010. https://eprints.soton.ac.uk/301182/.
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The growing academic interest in carbon nanotubes (CNTs) as a promising novel class of electronic materials has led to significant progress in the understanding of CNT physics including ballistic and non-ballistic electron transport characteristics. Together with the increasing amount of theoretical analysis and experimental studies into the properties of CNT transistors, the need for corresponding modelling techniques has also grown rapidly. This research is focused on the electron transport characteristics of CNT transistors, with the aim to develop efficient techniques to model and simulate CNT devices for logic circuit analysis. The contributions of this research can be summarised as follows. Firstly, to accelerate the evaluation of the equations that model a CNT transistor, while maintaining high modelling accuracy, three efficient numerical techniques based on piece-wise linear, quadratic polynomial and cubic spline approximation have been developed. The numerical approximation simplifies the solution of the CNT transistor’s self-consistent voltage such that the calculation of the drain-source current is accelerated by at least two orders of magnitude. The numerical approach eliminates complicated calculations in the modelling process and facilitates the development of fast and efficient CNT transistor models for circuit simulation. Secondly, non-ballistic CNT transistors have been considered, and extended circuit-level models which can capture both ballistic and non-ballistic electron transport phenomena, including elastic scattering, phonon scattering, strain and tunnelling effects, have been developed. A salient feature of the developed models is their ability to incorporate both ballistic and non-ballistic transport mechanisms without a significant computational cost. The developed models have been extensively validated against reported transport theories of CNT transistors and experimental results. Thirdly, the proposed carbon nanotube transistor models have been implemented on several platforms. The underlying algorithms have been developed and tested in MATLAB, behaviourallevel models in VHDL-AMS, and improved circuit-level models have been implemented in two versions of the SPICE simulator. As the final contribution of this work, parameter variation analysis has been carried out in SPICE3 to study the performance of the proposed circuit-level CNT transistor models in logic circuit analysis. Typical circuits, including inverters and adders, have been analysed to determine the dependence of the circuit’s correct operation on CNT parameter variation.
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Choi, Seong Yeon. "Stochastic modeling in fault testing of decomposable sequential circuits through computer simulation." Thesis, University of Ottawa (Canada), 1992. http://hdl.handle.net/10393/7621.
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The increasing complexity of today's digital devices has rendered the problem of fault detection, fault analysis, and test generation extremely difficult. Test generation for sequential circuits has been a difficult task. This is due to the large search space to be considered in test pattern generation. Different approaches have been taken in the past to solve the problem of fault detection and test generation in sequential circuits. A popular approach, called the scan design, is often used where the test generation problem in sequential circuits is transformed into one of combinational circuits. Unfortunately, this approach is mostly restricted to synchronous sequential circuits free of critical races. Moreover, when a circuit is very large and complex, the test generation can be quite involved, making the ad hoc approaches ineffective. Therefore, alternative methods should be considered. In this thesis, the detection of permanent faults in sequential circuits by random testing is analyzed utilizing the circuit partitioning approach together with a continuous parameter Markov model. Given a large decomposable sequential circuit, it is partitioned into several smaller partitions using either serial or parallel decomposition. For each partition with certain stuck faults specified, the original state table and its error version are derived from an analysis of the partition under fault-free and faulty conditions, respectively. Then by simulation of these two tables on a computer, the parameters of the desired Markov model are obtained. For a specified degree of confidence, it is easy to derive the parameters of the Markov model and to calculate the required lengths of random test patterns.
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Hu, Luoan 1954. "DBDF: An implicit numerical differentiation algorithm for integrated circuit simulation." Thesis, The University of Arizona, 1991. http://hdl.handle.net/10150/277918.
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Frequently, the design of integrated circuits cannot be accomplished by purely analytical techniques. Accurate and efficient algorithms for numerical circuit simulation are important tools. Several circuit simulators, such as SPICE, have been made available for this task. Contrary to many other applications of numerical system simulation, integrated circuit problems don't lend themselves to a formulation of state-space models, since the space charge in a p-n junction is a nonlinear and noninvertible function of the voltage across the junction. Therefore, it is necessary to employ numerical differentiation instead of numerical integration in this type of simulation study. The numerical algorithms employed in today's circuit simulators are fairly primitive. SPICE, for example, offers only two very simple implementations of the trapezoidal rule and of the backwards differentiation formula. This thesis describes the design and implementation of DBDF, a specification of a numerical method in Nordsieck format for solving circuit simulation problems. A formal stability and truncation error analysis are included.
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Farsaei, Ahmadreza. "On the electronic-photonic integrated circuit design automation : modelling, design, analysis, and simulation." Thesis, University of British Columbia, 2017. http://hdl.handle.net/2429/61272.
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Photonic networks form the backbone of the data communication infrastructure. In particular, in current and future wireless communication systems, photonic networks are becoming increasingly popular for data distribution between the central office and the remote antenna units at base stations. As wireless-photonic systems become increasingly more popular, not only low-cost implementation of such systems is desirable, but also a reliable electronic-photonic design automation (EPDA) framework supporting such complex circuits and systems is crucial. This work investigates the foundation and presents implementation of various aspects of such EPDA framework.
Various building blocks of silicon-photonic systems are reviewed in the first chapter of the thesis. The review discusses an example of a 60-GHz wireless system based on photonic technology, which could be suitable for the emerging 5th-generation (5G) cellular networks, and also provides design use cases that need to be supported by the EPDA framework.
Integrated photonic circuits, which are the building blocks of wireless-photonic systems, will achieve their potential only if designers can efficiently and reliably design, model, simulate, and tune the performance of electro-optical components. The developed EPDA framework supports an integrated optical solver, INTERCONNECT, to provide optical time and frequency domain simulations so that a designer would be able to simulate electrical, optical, and electro-optical circuits using two developed and implemented methodologies: sequential electro-optical simulation and co-simulation. We propose an algorithm to enhance the performance of electronic simulation engines that can be integrated into the EPDA simulation methods such as Harmonic Balance. It will be shown that body-biasing of CMOS transistors can be used as an effective method for tuning the performance of the electronic section of an electro-optical design. This can help designers adjusting the performance of their designs after fabrication. Modelling of electro-optical components is discussed in this thesis; It is shown that some traditional passive components such as inductors, which take a large amount of space in CMOS processes, could be fabricated in the much lower cost photonic process and consequently the overall cost of silicon-photonic systems can be reduced significantly.<br>Applied Science, Faculty of<br>Electrical and Computer Engineering, Department of<br>Graduate
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Maamari, Fadi. "On the structural properties of cominational circuits and their application to fault simulation." Thesis, McGill University, 1990. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=74590.
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A new fault simulation framework is proposed for combinational circuits, supported by a detailed analysis of the complexity of each of the three fault simulation components: fault-free (logic) simulation, explicit simulation of reconvergent fanout stem faults, and critical path tracing within fanout-free regions. The complexity analysis, measured in terms of the number of required gate evaluations, is implementation independent. The new framework achieves a reduction of the complexity of each component at both the static (input vector independent) level and the dynamic (input vector dependent) level.<br>At the static level, structural properties determined by a reconvergent fanout analysis are used to reduce the explicit simulation of fanout stem faults. At the dynamic level, dependencies between fault detectabilities are identified and used to reduce both the critical path tracing and explicit simulation components. In addition, fault-free simulation is reduced by tracking areas outside of which it is not required. The dynamic analysis reduces the fault simulation even further through a selective choice of the order in which the three simulation components are performed.
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Asenov, Plamen. "Accurate statistical circuit simulation in the presence of statistical variability." Thesis, University of Glasgow, 2013. http://theses.gla.ac.uk/4996/.
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Semiconductor device performance variation due to the granular nature of charge and matter has become a key problem in the semiconductor industry. The main sources of this ‘statistical’ variability include random discrete dopants (RDD), line edge roughness (LER) and metal gate granularity (MGG). These variability sources have been studied extensively, however a methodology has not been developed to accurately represent this variability at a circuit and system level. In order to accurately represent statistical variability in real devices the GSS simulation toolchain was utilised to simulate 10,000 20/22nm n- and p-channel transistors including RDD, LER and MGG variability sources. A statistical compact modelling methodology was developed which accurately captured the behaviour of the simulated transistors, and produced compact model parameter distributions suitable for advanced compact model generation strategies like PCA and NPM. The resultant compact model libraries were then utilised to evaluate the impact of statistical variability on SRAM design, and to quantitatively evaluate the difference between accurate compact model generation using NPM with the Gaussian VT methodology. Over 5 million dynamic write simulations were performed, and showed that at advanced technology nodes, statistical variability cannot be accurately represented using Gaussian VT . The results also show that accurate modelling techniques can help reduced design margins by elimiating some of the pessimism of standard variability modelling approaches.
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Nechma, Tarek. "Parallel sparse matrix solution for direct circuit simulation on a multiple FPGA system." Thesis, University of Southampton, 2012. https://eprints.soton.ac.uk/347886/.
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SPICE, from the University of California, at Berkeley, is the de facto world standard for circuit simulation. SPICE is used to model the behaviour of electronic circuits prior to manufacturing to decrease defects and hence reduce costs. However, accurate SPICE simulations of today's sub micron circuits can often take days or weeks on conventional processors. In a nutshell, a SPICE simulation is an iterative process that consists of two phases per iteration, namely, model evaluation followed by a matrix solution. The model evaluation phase has been found to be easily parallelisable unlike the subsequent phase, which involves the solution of highly sparse and asymmetric matrices. In this thesis, we present an FPGA implementation of a sparse matrix solver hardware,geared towards matrices that arise in SPICE circuit simulations. As such, we demonstrate how we extract parallelism at di�erent granularities to accelerate the solution process. Our approach combines static pivoting with symbolic analysis to compute an accurate task ow-graph which e�ciently exploits parallelism at multiple granularities and sustains high oating-point data rates. We also present a quantitative comparison between the performance of our hardware protrotype and state-of-the-art software package running on a general purpose PC equipped with a 2.67 GHz six-core 12 thread Intel Core Xeon X5650 microprocessor and 6 GB memory. We report average speedups of 9.65�, 11.83�, 17.21� against UMFPACK, KLU, and Kundert Sparse matrix packages respectively. We also detail our approach to adapt our sparse LU hardware prototype from a single-FPGA architecture to a multi-FPGA system to achieve higher acceleration ratios up to 38� for certain circuit matrices.
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Wong, Kam Lung. "Studies on a continuous Markov model for probabilistic fault analysis in VLSI sequential circuits using computer simulation." Thesis, University of Ottawa (Canada), 1990. http://hdl.handle.net/10393/5876.
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A continuous parameter Markov model is proposed in this thesis to detect permanent stuck-at faults in sequential circuits by random testing. Given a sequential circuits with certain stuck-at faults specified, the fault-free and the faulty state tables of the circuit can be readily derived. By simulation of these two state tables on a computer, the parameters of the desired Markov model can be obtained. For a specified confidence level, it is easy to derive the model parameters and to estimate the required testing time. A complete mathematical analysis of the model is given that provides some useful insights into the nature of faults in relation to random testing and the associated confidence level.
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Aparicio, Marina. "Modélisation et Simulation du phénomène d'IR-Drop dans les circuits intégrés." Phd thesis, Université Montpellier II - Sciences et Techniques du Languedoc, 2013. http://tel.archives-ouvertes.fr/tel-00943295.
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L'évolution des technologies microélectroniques voire déca-nanoélectroniques conduit simultanément à des tensions d'alimentation toujours plus faibles et à des quantités de transistors toujours plus grandes. De ce fait, les courants d'alimentation augmentent sous une tension d'alimentation qui diminue, situation qui exacerbe la sensibilité des circuits intégrés au bruit d'alimentation. Un bruit d'alimentation excessif se traduit par une augmentation du retard des portes logiques pouvant finalement produire des fautes de retard. Un bruit d'alimentation provoqué par des courants circulant dans les résistances parasites du Réseau de Distribution d'Alimentation est communément référencé sous la dénomination d'IR-Drop. Cette thèse s'intéresse à la modélisation et à la simulation de circuits logiques avec prise en compte du phénomène d'IR-Drop. Un algorithme original est tout d'abord proposé en vue d'une simulation de type 'event-driven' (déclenchement par évènement) du bloc logique sous test, en tenant compte de l'impact de l'ensemble du circuit intégré sur l'IR-Drop du bloc considéré. Dans ce contexte, des modèles précis et efficaces sont développés pour les courants générés par les portes en commutation, pour la propagation de ces courants au travers du réseau de distribution et pour les retards des portes logiques. D'abord, une procédure de pré-caractérisation des courants dynamiques, statiques et des retards est décrite. Ensuite, une seconde procédure est proposée pour caractériser la propagation des courants au travers du réseau de distribution. Nos modèles ont été implantés dans une première version du simulateur développé par nos collègues de Passau dans le cadre d'une collaboration. Enfin, l'impact des éléments capacitifs parasites du réseau de distribution est analysé et une procédure pour caractériser la propagation des courants est envisagée.
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Chen, Amy. "Oceanographic Instrument Simulator." DigitalCommons@CalPoly, 2016. https://digitalcommons.calpoly.edu/theses/1585.
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The Monterey Bay Aquarium Research Institute (MBARI) established the Free Ocean Carbon Enrichment (FOCE) experiment to study the long-term effects of decreased ocean pH levels by developing in-situ platforms [1]. Deep FOCE (dpFOCE) was the first platform, which was deployed in 950 meters of water in Monterey Bay. After the conclusion of dpFOCE, MBARI developed an open source shallow water FOCE (swFOCE) platform located at around 250 meter of water to facilitate worldwide shallow water experiments on FOCE [1][2]. A shallow water platform can be more ubiquitous than a deep-water platform as shallow water instruments are less expensive (as it does not have to be designed to withstand the pressure at deep ocean depths) and more easily deployed (they can be deployed right along the coast).
The swFOCE experiment is an open source platform, and MBARI has made the plans available online to anyone interested in studying shallow water carbon enrichment. There is a gateway node what is connected to four sensor nodes within the swFOCE. In order to test the sensor node individually, an idea of designing an Oceanographic Instrument Simulator is purposed. The Oceanographic instrument simulator (OIS), described in this paper provides the means for MBARI engineers to test the swFOCE platform without attaching the numerous and expensive oceanographic instruments. The Oceanographic Instrument Simulator simulates the various scientific instruments that could be deployed in an actual experiment.
The Oceanographic Instrument Simulator (OIS) system includes the designed circuit board, Arduino Due and an SD Card shield. The designed circuit board will be connected to a computer through a USB cable, and be connected to MBARI’s swFOCE sensor node through a serial connection. When a query is given from the sensor node, the Arduino Due will parse the data given from the sensor node, search through the pre-installed data in the SD card and return the appropriate data back to the sensor node. A user can also manually set up the input current through a computer terminal window to control the simulated signals from the PCB.
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Kamsani, Noor 'Ain. "Statistical circuit simulations - from ‘atomistic’ compact models to statistical standard cell characterisation." Thesis, University of Glasgow, 2011. http://theses.gla.ac.uk/2720/.
Full textAbstract:
This thesis describes the development and application of statistical circuit simulation methodologies to analyse digital circuits subject to intrinsic parameter fluctuations. The specific nature of intrinsic parameter fluctuations are discussed, and we explain the crucial importance to the semiconductor industry of developing design tools which accurately account for their effects. Current work in the area is reviewed, and three important factors are made clear: any statistical circuit simulation methodology must be based on physically correct, predictive models of device variability; the statistical compact models describing device operation must be characterised for accurate transient analysis of circuits; analysis must be carried out on realistic circuit components. Improving on previous efforts in the field, we posit a statistical circuit simulation methodology which accounts for all three of these factors. The established 3-D Glasgow atomistic simulator is employed to predict electrical characteristics for devices aimed at digital circuit applications, with gate lengths from 35 nm to 13 nm. Using these electrical characteristics, extraction of BSIM4 compact models is carried out and their accuracy in performing transient analysis using SPICE is validated against well characterised mixed-mode TCAD simulation results for 35 nm devices. Static d.c. simulations are performed to test the methodology, and a useful analytic model to predict hard logic fault limitations on CMOS supply voltage scaling is derived as part of this work. Using our toolset, the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of inverters is studied in detail. As devices scaled, dynamic noise margin variation of an inverter is increased and higher output load or input slew rate improves the noise margins and its variation. Intrinsic delay variation based on CV/I delay metric is also compared using ION and IEFF definitions where the best estimate is obtained when considering ION and input transition time variations. Critical delay distribution of a path is also investigated where it is shown non-Gaussian. Finally, the impact of the cell input slew rate definition on the accuracy of the inverter cell timing characterisation in NLDM format is investigated.