Dissertations / Theses on the topic 'Electronic circuits'

Iterative electronic circuits - that is, circuits whose behaviour can be described by a mapping in which time is not explicitly present - are investigated, and particular attention is paid to those circuits which can be shown to display chaotic behaviour. Examples emanating mainly from the fields of power electronics and digital electronics are discussed. The emphasis is on the derivation of analytical results wherever this is possible, although numerical calculations have also been much relied upon. Some of these results are supported by experimental investigations. Many of the results are presented in the form of diagrams. The implications of chaotic behaviour for electronic engineers have been indicated. A brief discussion of the relation between iterative circuits and circuits that are described by non-linear differential equations is included.

Electronic circuit boards are employed in demanding environments (e.g. satellite, aerospace, marine, automobile, etc.) where the board and mounted components are exposed to vibration of varying amplitude and frequencies. Optimum mounting and component placement to reduce the effect of vibration on the equipment may prolong the service life of the system and reduce costly down time. Electronic boards are often mounted on four rigid support legs. Their vibration is a function of the location of the support legs, and board physical specifications such as length, width, weight, and placement of the components mounted on them. In this study, plate vibration analysis is employed to find the board's free vibration. With the help of nonlinear optimization methods, optimum mounting of circuit boards are investigated. Square board has a better performance than any other board shape. A table of suitable support points will be introduced outlining optimum support points for eight rectangular shapes. For each of these shapes a graph of unsuitable regions is provided to help the designer to avoid placing delicate components over those regions of the plate. Furthermore, the tabulated results can eliminate the need for optimization in non-critical circuit boards or determine a good starting point for optimization. (Abstract shortened by UMI.)

Thesis (M.S.)--University of Missouri--Rolla, 2007.
Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 55-56).

Thesis (M.S.)--University of Missouri--Rolla, 2007.
Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 66-67).

Current use of electronics has been growing rapidly. The trend is creating huge environmental impacts during manufacture of electronic goods and at the end of life. Alternative manufacturing and disposal techniques are required. Circuits in Plastic (CiP) manufacturing is designed to address these issues. Circuit components are placed in a plastic substrate, conductive tracks are screen printed and the circuit is completed by thermally bonding a cover sheet over the circuit. The circuits are disassembled by mechanical means. While the process requires much less energy and produces minimal waste, the process must be reliable. Mechanical reliability and thermal stability of electronic circuits is important in electronics. Tensile tests conducted on CiP circuits showed the electrical connection remained intact during an extension of 3%. The test was conducted at the laboratory ambient temperature of 21°C. Thermal simulation of the steady state temperature distribution of an integrated circuit for the CiP shows little temperature difference (less than 5°C) between CiP and traditional surface mounted devices. The experimental work showed CiP circuits are functional at high operating temperatures (60°C). CiP was not tested across the standard range of -55°C to 150°C. Such tests are only possible if the glass transition temperature of the plastic substrate is not exceeded.
Thesis (PhD Doctorate)
Doctor of Philosophy (PhD)
Griffith School of Engineering
Science, Environment, Engineering and Technology
Full Text

Thesis (M.S. in Electrical Engineering and M.S. in Applied Physics and Electrical Engineer) Naval Postgraduate School, December 1994.
Thesis advisor(s): Phillip E. Pace, A. W. Cooper. "December 1994." Bibliography: p. 95-99. Also available online.

COORDENAÇÃO DE APERFEIÇOAMENTO DO PESSOAL DE ENSINO SUPERIOR
Esta tese investiga a utilização de computação evolutiva aplicada à síntese de circuitos eletrônicos. A computação evolutiva compreende uma classe de algoritmos que utilizam certos aspectos da evolução natural como metáforas. Particularmente, a seleção natural, a recombinação de material genético e a mutação são os mecanismos biológicos nos quais a maior parte destes algoritmos evolutivos buscam inspiração. Embora algoritmos evolutivos tenham encontrado em problemas de otimização o seu maior potencial de aplicação, a utilização dos mesmos na síntese de circuitos eletrônicos vem sendo intensamente investigada nos últimos anos, dando início à área de pesquisa denominada de Eletrônica Evolutiva. Esta tese enfoca a área de eletrônica evolutiva sob o ponto de vista de engenharia de circuitos, e seu maior objetivo é oferecer embasamento teórico e experimental para proposta de novas ferramentas de Computer Aided Design (CAD) de circuitos eletrônicos. Nesta pesquisa, a utilização de algoritmos evolutivos não se restringiu àqueles que empregam apenas os três operadores genéticos descritos anteriormente, isto é, seleção, recombinação e mutação. Investigou-se a inclusão de novos métodos e operadores ao fluxo básico dos algoritmos evolutivos, com o propósito de melhorar seu desempenho em problemas na área de Eletrônica Evolutiva. Particularmente, estudou-se a utilização de complexidade através de sistemas com representação variável sistemas evolutivos que utilizem como metáfora o conceito biológico de especiação. Além disso, uma nova metodologia para otimização com múltiplos objetivos, baseada em conceitos de aprendizado de Redes Neurais Artificiais, for também concebida nessa tese. Realizou-se um amplo estudo de casos, abrangendo eletrônica analógica, digital e microeletrônica. Uma grande variedade de circuitos de caráter prático foi sintetizada, tais como: filtros, amplificadores, osciladores, retificadores, receptores, comparadores, multiplexadores e portas digitais básicas. Novos paradigmas de eletrônica evolutiva foram também concebidos, com o intuito de tornar os circuitos projetados competitivos com aqueles convencionalmente utilizados; estes paradigmas referem-se à forma como os circuitos são avaliados ao longo do algoritmo evolutivo. A plataforma para realização dos experimentos consistiu de simuladores de circuitos e também de circuitos integrados reconfiguráveis. Os resultados mostram que esta nova classe de ferramentas de CAD pode chegar a circuitos mais eficientes do que os obtidos por ferramentas convencionais. Além disso, circuitos eletrônicos sintetizados por computação evolutiva são em geral bastante distintos daqueles projetados convencionalmente, o que contribui para a concepção de novas metodologias de projeto.
This thesis investigates the application of evolutionary computing techniques in the synthesis of electronic circuits. Evolutionary computation encompasses a particular class of algorithm which employ some aspects of natural evolution as metaphors. Particularly, most of these algorithms borrow ideas from the natural selection, genetic material recombination and mutation biological mechanisms. Even though evolutionary algorithms have been intensively investigates recently, starting a new research area called Evolutionary Electronics. This work focuses on evolutionary electronics from a enginnering perspective and the main objective is the proposal of a new generation of a Computer Aided Design (CAD) tools. Many case studies have been analysed, covering digital and analog microelectronics. The work aimed the achievement of competitive results comparing to other CAD tools. The research has made use of evolutionary algorithms tailored to these application, by including other genetic operators besides the ones defined above. The following methods have been embedded in the evolutionary methodology: memory based genetic algorithms, use of variable length representation systems and the use of the biological speciation metaphor. Furthermore, a new multiple-objective optimization method, based on artificial neural networks learning algorithms, has also been employed in the case studies. A large number of circuits of practical interest have been sysnthesised, such as filters, amplifiers, oscillators, rectifiers, receptors, comparators refer to new approaches for circuits evaluation, particularly in the digital domain. Circuit simulators and analog the reconfigurable circuits have been used as platforms for the evolutionary process. The results show that the circuits synthesided through evolutionary computation are, in some cases, more efficient than the human designed ones. Besides, the evolved circuits are usually quite different from their human designed counterparts, which can contribute to the creation of new design methodologies. The author identified many promising ways of evolutionary algorithms application in analog and digital design, which may, in the future, overcome conventional design in terms of area, speed and power consumption.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
Includes bibliographical references (p. 191-198).
by Mohammad Ali Tassoudji.
Ph.D.

Photonic systems can operate at frequencies several orders of magnitude higher than electronics, whereas electronics offers extremely high density and easily built memories. Integrated photonic-electronic systems promise to combine advantage of both, leading to advantages in accuracy, reconfigurability and energy efficiency. This work concerns of hybrid and monolithic electronic-photonic system design. First, a high resolution voltage supply to control the thermooptic photonic chip for time-bin entanglement is described, in which the electronics system controller can be scaled with more number of power channels and the ability to daisy-chain the devices. Second, a system identification technique embedded with feedback control for wavelength stabilization and control model in silicon nitride photonic integrated circuits is proposed. Using the system, the wavelength in thermooptic device can be stabilized in dynamic environment. Third, the generation of more deterministic photon sources with temporal multiplexing established using field programmable gate arrays (FPGAs) as controller photonic device is demonstrated for the first time. The result shows an enhancement to the single photon output probability without introducing additional multi-photon noise. Fourth, multiple-input and multiple-output (MIMO) control of a silicon nitride thermooptic photonic circuits incorporating Mach Zehnder interferometers (MZIs) is demonstrated for the first time using a dual proportional integral reference tracking technique. The system exhibits improved performance in term of control accuracy by reducing wavelength peak drift due to internal and external disturbances. Finally, a monolithically integrated complementary metal oxide semiconductor (CMOS) nanophotonic segmented transmitter is characterized. With segmented design, the monolithic Mach Zehnder modulator (MZM) shows a low link sensitivity and low insertion loss with driver flexibility.

Aggressive feature-size scaling of silicon-based complementary metal-oxide semiconductor (CMOS) transistors is slowly approaching to its ultimate physical limitations. In an era where integrated circuits are supposed to be fast, reliable, and extremely power-efficient, worldwide scientists are striving to find an alternative material that could replace silicon in future electronic devices. During the past decade, graphene, a 2-D allotrope of carbon, has emerged as one of the most promising candidates. Mechanical strength and flexibility, combined with very high carrier mobility, make graphene a perfect material for the implementation of wearable devices. However, pristine graphene is a zero band-gap material, i.e., valence and conductance bands are touching each other near the Dirac points. The direct consequence is an insufficient ON/OFF current ratio that prevents graphene to implement the OFF-state. This poses severe limitations for digital applications, where a clear separation between 0- and 1-logic is fundamental. In this very historical period, most of the worldwide research on the topic is focused on finding practical methods to open the band-gap, in order to match, or at least approach, that of silicon. Available solutions like patterning, chemical doping, or combination with other materials, increase the level of disorder of graphene itself, with rather huge impact on its superlative pristine characteristics, e.g., reduced carrier mobility, in particular. Hence, the need of alternative, fine-tuned, techniques that best suite the mechanical and electrical properties of graphene, while preserving its intrinsic characteristics. The electrostatic doping principle falls in this category. It allows a fine-tuning of the Fermi Energy level in order to obtain equivalent p- or n-type graphene regions using an external electrical field applied through metal gates. Face to face regions with opposite doping profiles form an equivalent p-n junction, the key component behind any electronic circuit. The obtained graphene-based device is what we called Pass-XNOR (PX) gate, since its functionality resembles that of a transmission gate, but with an enhanced built-in logical Exclusive-NOR (XNOR) functionality. From a design-automation perspective, exploiting the expressive power of this new XNOR-based primitive sets a clear departure from classical abstraction models based on the And-Inverter representation, and manipulation, of Boolean logic functions. Therefore, new design methodologies are required to be developed. In this context, the contribution of this work is summarized as follows: (i) we propose a novel integration strategy for PX gates, called the Pass-XNOR Logic (PXL), that fruitfully exploits the built-in XNOR functionality of graphene p-n junctions in order to guarantee compact representations of rather complex Boolean logic functions; (ii) by resorting to the adiabatic charging principle, we demonstrate that PXL circuits are able to reach {\em deep-adiabatic} regimes with a performance improvement of several orders of magnitude w.r.t. silicon counterparts; (iii) we introduce a one-pass synthesis flow for PXL networks by means of a novel abstraction model, called the Pass Diagram, that allows to efficiently manipulate large Boolean networks built upon the XNOR primitive, as well as several synthesis and optimization algorithms which constitute the first CAD tool for graphene-based devices.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006.
Integrated circuits are expensive to manufacture and it is important to verify the correct operation of a circuit before fabrication. Efficient, though accurate, parameter extraction of post-layout designs are required for estimation of circuit success rates. This thesis discusses electrical netlist and fast parameter extraction techniques suited for both intraand inter-gate connections. This includes the use of extraction windows and look-up tables (LUTs) for accurate inductance and capacitance estimation. These techniques can readily be implemented in automated layout software where fast parameter extraction is required for timing analysis and gate placement.

Apresentamos cálculos de primeiros princípios da geometria atômica, energia de formação e estrutura eletrônica para as impurezas substitucionais de oxigênio e nitrogênio em GaAs (\'O IND. aS1\'\'N IND.As \'e \'N IND. Ga\'). Também estudamos a geometria atômica e estrutura eletrônica dos complexos neutros formados pelas mesmas impurezas substitucionais e átomos de hidrogênio intersticial (\'O IND. As-H\',\'N IND. As-H\',\'N IND. Ga-H\', \'N IND. As-H IND.2\' e \'N IND. Ga-H IND 2\'). Nossos resultados para os centros \'O IND. As\'e \'N IND. Ga\', em diferentes estados de carga, mostram distorções Jahn-Teller as quais induzem estados de carga não estáveis, observando-se um comportamento U-negativo para cada centro. Entretanto para o centro \'N IND. As\' não foram observadas distorções. Em todos os sistemas estudados, as impurezas introduzem níveis profundos no gap. Para os complexos O-H e N-H foram encontradas várias configurações metaestáveis, correspondentes a diferentes posições de equilíbrio do átomo de hidrogênio, as quais apresentam energias entre 0.5 e 2.5 e V relativas à configuração estável. Na configuração estável do complexo \'O IND. As-H\', oxigênio não interage diretamente com hidrogênio, ligando-se a três gálios primeiros vizinhos. Entretanto para os complexos \'N IND. As-H\' e \'N IND. Ga\'-Hg\' é observada a formação de um dímero NH ligado à rede. Para os complexos N-\'H IND. 2\' também são encontradas várias configurações metaestáveis. O complexo\'N IND. As\'-\'H IND. 2\' apresenta uma configuração estável onde um dos hidrogênios forma o dímero NH, enquanto que o segundo fica ligado a um gálio primeiro vizinho, em simetria \'C IND. 3 v\'. Para o complexo \'N IND. Ga\'-\'H IND.2\' é observada a formação de uma molécula do tipo N\'H IND.2\', a qual também se liga à rede. As propriedades passivadora e ativadora do átomo de hidrogênio, como também sua interação com os níveis no gap, são discutidas para cada complexo
We report first-principles calculations of the electronic structure, atomic geometry and formation energy for the isolated oxygen and nitrogen substitutional impurities in GaAs (OA, NA, and Naa)· Also we performed electronic structure and atomic geometry calculations for the neutra! complexes formed by the same substitutional impurities and interstitial hydrogen atoms (O A,-H,NA,-H, Naa-H, Nk,-H2 and Naa-H2). Our results for the O ko and Naa centers for different charge states show Jahn-Telier distortions which induce unstable charge states, implying in a nega tive-U behaviour for each center. The NA-< center remains on-site for ali the charge states studied. Ali the substitutional impurity give rise deep leveis in the gap. For the 0-H and N-H complexes we found severa! metastable configurations related to different hydrogen equilibrium positions, with energies ranging from 0.5 to 2.5 eV relative to the stable configuration. The stable configuration for the O A,-H complex shows a weak interaction between oxygen and hydrogen, while for the NA,-H and Naa-H complexes it shows the formation of a N H dimer which is bonded to the lattice. For the N-H2 complexes we also found severa! metastable configuration. The stable configuration for the Nk,-H2 complex shows one H atom fonning a N H dimer wit.h nitrogen, while the second one bonds with a nearestneighbour Ga atom, in C3, symmetry. For the Naa·H2 complex we observed the formation o f a N H T like molecule ais o bonded to the lattice. The passivation and activation properties related to hydrogen atom and their interaction with the gap leveis are discussed.

This dissertation focuses on the development of integrated circuits that employ InAs quantum well electronic devices. There are two InAs quantum well electronic devices studied in this work, the first being the pseudomorphic InAs/In₀.₅₃Ga₀.₄₇As/AlAs resonant tunneling diode (RTD) grown on an InP substrate, and the second being the InAs/AlSb HEMT. Because of there is no semi-insulating substrate near the InAs lattice constant of 6.06 Å this work develops monolithic and hybrid integration methods to realize integrated circuits. For the case of hybrid RTD circuits, a thin-film integration method was developed to integrate InAs/In₀.₅₃Ga₀.₄₇As/AlAs RTDs to prefabricated CMOS circuits, and this technique was employed to demonstrate a novel RTD-CMOS comparator. To achieve higher speed circuit operation, a next-generation RTD fabrication process was developed to minimize the parasitic capacitance associated with the thin-film hybridization process. This improved fabrication process is detailed and yield and uniformity analysis is included. Similar InP-based tunnel diodes can be integrated with InP-based HEMTs in monolithic RTD-HEMT integrated circuits, and in this work elementary microwave circuit components were characterized that co-integrate InP-based tunnel diodes with HEMTs. In the case of the InAs/AlSb HEMT, the monolithic approach grows the HEMT on a metamorphic buffer on a GaAs substrate. The semiconductor material and process development of the InAs/AlSb HEMT MMIC technology is described. The remarkable microwave and RF noise properties of the InAs/AlSb HEMT were characterized and analyzed, with special attention given to the strong effects of impact ionization in the narrow bandgap InAs channel. Results showed the extent to which impact ionization affects the small-signal gain and noise figure of the HEMT, and that these effects become less prevalent as the frequency of operation increases.

Emerging macro- and flexible electronic applications such as foldable displays, artificial skins, and smart textiles grow rapidly into the market. Solution-processed thin-film transistors (TFTs) based on single-walled carbon nanotubes (SWCNTs) as the semiconductor channel can offer high performance, low cost and versatility for macro- and flexible electronics. Major challenges to the development of SWCNT-based TFTs include: (i) hysteresis in their transfer characteristics (TCs), (ii) difficulties in simultaneous achievements of high on-state current Ion and large on/off current ratio Ion/Ioff, and (iii) poor uniformity and scalability resulting from the poor solution processability. This thesis aims at developing reliable and simple process techniques for fabrication of the SWCNT-based TFTs that possess the afore-stated characteristics. It presents a systematic investigation to not only explore the fundamental device physics, but also develop novel fabrication methods for enhancement of device performance. First, issues related to the measurement of gate capacitance (Cg), the determination of current scalability, and the hysteresis in randomly networked SWCNTs are properly addressed. This leads to the establishment of a comprehensive methodology for extraction of carrier mobility (μ) for the SWCNT-based TFTs. In detail, the large hysteresis is effectively suppressed by adopting a pulsed drain current-gate voltage (Id-Vg) method in which the polarity of the gate pulse was alternating during the measurement. Different from most reported methods in the literature, Cg is accurately determined in our case by performing direct capacitance-voltage measurement on the TFTs. Second, with the employment of functional composites comprising SWCNTs embedded in a semiconducting polymer, poly-9,9 dioctyl-fluorene-cobithiophene (F8T2), as the semiconducting channel via facile solution processes under ambient conditions, the fabricated TFTs exhibit outstanding electrical performance with: (i) negligible hysteresis, (ii) high μ, (iii) high Ion and large Ion/Ioff, (iv) excellent uniformity and dimensional scalability, and (v) good stability. These highly desired performance parameters are achieved owing to an ideal composite structure with metallic SWCNTs being selectively removed and the remaining semiconducting SWCNTs being well wrapped by the polymer matrix. Finally, the developed TFTs basing on the SWCNT/F8T2 composite are used as the building block to construct some logic circuits. The resultant inverters, NANDs, and NORs are found to retain the small-hysteresis characteristics, with a cut-off frequency reaching 100 kHz. The results presented in this thesis advance the state-of-art SWCNT-based macroelectronics.

PONTIFÍCIA UNIVERSIDADE CATÓLICA DO RIO DE JANEIRO
Esta dissertação investiga a utilização de técnicas de Eletrônica Evolucionária nos processos de reparo e ajuste de circuitos eletrônicos. O objetivo do trabalho foi avaliar o desempenho de algoritmos de computação evolucionária no reparo de circuitos eletrônicos efeituosos e no ajuste e melhoria de circuitos não ótimos, fornecendo desta forma, base teórica e experimental para ferramentas de reparo e ajuste automático de circuitos. A necessidade de ferramentas que efetuem reparos de circuitos eletrônicos em situações emergenciais, bem como a diversidade de defeitos encontrados nos vários tipos de circuito, motivaram esta pesquisa. O trabalho de pesquisa foi desenvolvido em 6 etapas principais: um estudo sobre algoritmos evolutivos e suas aplicações na área da Eletrônica Evolucionária; uma revisão de estratégias de múltiplos objetivos que culminou na proposta de um novo parâmetro de importância para os objetivos dos algoritmos evolutivos e na reformulação do cálculo do erro no Método de Minimização de Energia; o projeto de um protótipo de plataforma reconfigurável; a proposta de uma técnica de reparos e ajustes por evolução extrínseca; a proposta de uma técnica de reparos e ajustes por evolução intrínseca; e o estudo de casos. De acordo com o objetivo do trabalho de avaliar o desempenho do algoritmos evolutivos no reparo e ajuste de circuitos eletrônicos, primeiramente efetuou-se um estudo sobre a aplicação destes algoritmos na área da eletrônica evolucionária. Este estudo envolveu as diferentes formas de representação e avaliação, bem como os principais operadores. Também fez parte deste estudo estratégias de múltiplos objetivos e suas aplicações na otimização e síntese de circuitos, tanto por evolução extrínseca quanto intrínseca. Como resultado deste estudo preliminar, verificou-se a necessidade de reavaliar a metodologia de múltiplos objetivos baseada na minimização de energia, atribuindo valores de importância diferentes aos diferentes objetivos dos algoritmos evolutivos. Foi proposto então um parâmetro Importância do Objetivo que prioriza atender aos objetivos mais importantes desses algoritmos. Ou seja, privilegia as mais relevantes características avaliadas do circuito. Foi ainda revista a fórmula de cálculo do erro no Método de Minimização de Energia, sugerindo-se outra que baseia-se na avaliação do melhor indivíduo. Esta proposta visa direcionar o processo evolutivo para os objetivos não satisfeitos do melhor indivíduo. As técnicas de reparos e ajustes automáticos por evolução extrínseca aqui propostas são muito semelhantes às técnicas de síntese de circuitos por computação evolucionária. Foi dada especial atenção à avaliação dos circuitos e aos objetivos dos algoritmos que estão intimamente relacionados com o circuito original não defeituoso ou com o circuito ideal. Para realizar reparos e ajustes automáticos por evolução intrínseca faz-se necessário o uso de uma plataforma reconfigurável de circuitos eletrônicos. Isto implica em uma diferente forma de representação dos circuitos quando comparamos esta técnica com aquela baseada em evolução extrínseca. Além disso, técnicas de inicialização da população dos algoritmos evolutivos foram utilizadas para orientar a evolução com base na topologia do circuito falho. Para possibilitar a realização de experimentos com evolução extrínseca, foi projetado e implementado um protótipo de plataforma reconfigurável para circuitos analógicos chamada de PAMA. Foram realizados estudos de caso de modo a avaliar o desempenho destas técnicas de reparos e ajustes automáticos tanto por evolução extrínseca quanto por evolução intrínseca. Além disso foi avaliada a relevância e o desempenho do parâmetro Importância do Objetivo. Nos estudos de caso realizados foram utilizados circuitos bem conhecidos, como portas TTL
This dissertation investigates the application of Evolvable Hardware Techniques in the process of repair and adjustment of electronic circuits. The objective of this work was to evaluate the performance of evolvable techniques in the repair of defective electronic circuits and in the adjustment of non-optimum circuits, providing theoretical and experimental basis for self-adjustment and self-repair tools. The need of emergency repair tools for electronic circuits, besides the diversity of damages that can be found in various types of circuits has motivated this research. This research had 6 steps: a study on evolvable algorithms and its application in Evolvable Hardware field; a review of multi-objective strategies that motivated the proposal of the parameter Objective`s Importance and of a new formula to calculate the error in the Energy Minimization Method; the design of a prototype of reconfigurable platform; the proposal of techniques to extrinsically evolve the repair and to adjust circuits; a proposal of techniques to intrinsically repair and adjust circuits; and the case studies. According to the objective of this work of evaluating the performance of evolvable algorithms in the repair and adjustment of electronic circuits, at first a study on representation, evaluation and operators of these algorithms was done. Multi-objective strategies and its applications in extrinsic and intrinsic evolution for optimisation and synthesis of circuits was also part of this study. As result of this preliminary study, was observed that each objective has a different importance. If this importance is not assigned to the objectives, some circuits may have a good fitness but important objectives may not be satisfied while not so important ones may be. The use of a new parameter called Objective`s Importance was proposed to solve this problem. The calculus of the error in the Energy Minimization Method was also reformulated to give more importance to the best individual. The techniques of extrinsic evolvable repair and adjustment proposed here are very similar to the evolvable techniques used to synthesize circuits. The circuits` evaluation and algorithm`s objectives were studied and some changes were proposed. To intrinsically repair circuits is necessary to use a reconfigurable platform of analog circuits. This method is different from the extrinsic one. The individuals representation in this case may vary and depends on the platform used. Techniques to initialise populations were used to seed the population. To make intrinsic evolution experiments possible, a reconfigurable platform for analog circuits called PAMA was designed and implemented. Through the case studies the performance of the techniques proposed were evaluated. Tests with intrinsic and extrinsic systems were done. The relevance and performance of the Objective`s Importance parameter was also studied. Well known analog circuits like TTL gates and amplifiers were used in the experiments. The results showed the accomplishment of such class of techniques and tools, which are very useful to repair circuits, especially in emergencies. Due to the viability of using evolvable techniques and its advantages when compared to the regular methods, the plans are, in future work, to keep testing variations of these methods and testing these techniques in bigger circuits.
Esta disertación investiga la utilización de técnicas de electrónica Evolutiva en los procesos de reparación y ajuste de circuitos electrónicos. El objetivo del trabajo fue evaluar el desempeño de algoritmos de computación evolutiva en la reparación de circuitos electrónicos defectuosos y en el ajuste y mejoría de los circuitos no óptimos, ofreciendo una base teórica y experimental para herramientas de reparación y ajuste automático de circuitos. La necesidad de herramientas que efectuen reparaciones de circuitos electrónicos en situaciones de emergencia, bien como la diversidad de defectos encontrados en los varios tipos de circuito, motivaron esta investigación. El trabajo de investigación fue desarrollado en 6 etapas principales: un estudio sobre algoritmos evolutivos y sus aplicaciones en el área de la Electrónica Evolutiva; una revisión de estrategias de múltiples objetivos que culminó en la propuesta de un nueva parámetro de importancia para los objetivos de los algoritmos evolutivos y en la reformulación del cálculo del error en el Método de Minimización de Energía; el proyecto de un prototipo de plataforma reconfigurable; la propuesta de una técnica de reparaciones y ajustes por evolución extrínseca; la propuesta de una técnica de reparaciones y ajustes por evolución intrínseca; y el estudio de casos. De acuerdo con los objetivo del trabajo de evaluar el desempeño del algoritmos evolutivos en la reparación y ajuste de circuitos electrónicos, primeramente se efectuó un estudio sobre la aplicación de estos algoritmos en el área de la electrónica evolutiva. Este estudio involucró las diferentes formas de representación y evaluación, así como los principales operadores. También forma parte de este estudio las estrategias de múltiples objetivos y sus aplicaciones en la optimización y síntesis de circuitos, tanto por evolución extrínseca como intrínseca. Como resultado de este estudio preliminar, se verificó la necesidad de reevaluar la metodología de múltiples objetivos baseada en la minimización de energía atribuyendo valores de importancia diferentes a los diferentes objetivos de los algoritmos evolutivos. Se propone entonces un parámetro Importancia del objetivo que prioriza atender los objetivos más importantes de esos algoritmos. O sea, favorece las características más relevantes del circuito. Se revisó la fórmula de cálculo del error en el Método de Minimización de Energía sugiriendo otra que se basa en la evaluación del mejor individuo. Esta propuesta direcciona el proceso evolutivo para los objetivos no satisfechos del mejor individuo. Las técnicas de reparación y ajustes automáticos por evolución extrínseca que aqui se proponen son muy semejantes a las técnicas de síntesisde circuitos por computación evolucionaria. Fue dada especial atención a la evaluación de los circuitos y al os objetivos de los algoritmos que están íntimamente relacionados con el circuito original no defectuoso o con el circuito ideal. Para realizar reparaciones y ajustes automáticos por evolución intrínseca se hace necesario el uso de una plataforma reconfigurable de circuitos electrónicos. Esto trae consigo una forma diferente de representación de los circuitos cuando comparamos esta técnica con la basada en evolución extrínseca. Además, técnicas de inicialización de la populación de los algoritmos evolutivos fueron utilizadas para orientar la evolución con base en la topología del circuito fallo. Para poder realizar los experimentos con evolución extrínseca, se proyectó e implementado un protótipo de plataforma reconfigurable para circuitos analógicos llamada de PAMA. Fueron realizados estudios de caso de modo a evaluar el desempeño de estas técnicas de reparaciones y ajustes automáticos tanto por evolución extrínseca cuanto por evolución intrínseca. En los estudios de caso realizados se utilizaron circuitos bien conocidos, como puertas TTL y pré-ampli

Integrated electronic systems are increasingly used in an wide number of applications and environments, ranging from critical missions to low cost consumer products. Information processing has been thoroughly integrated into everyday objects and activities, in the so-called ubiquitous computing paradigm. This wide distribution is caused mainly by the miniaturization of semiconductor devices (transistor channel length scaling from 180 nm in 1999 to 22 nm in 2012), which allows integrating a complete system on a single chip (SoC). However, there are many difficult challenges associated with continued cost reduction, size reduction, improved performance and improved power efficiency. One of these challenges is the reliability of these electronic systems. Important research efforts are aimed at improving the reliability of semiconductors. Manufacturing processes, intrinsic aging phenomena of components and environmental stress may cause internal defects and damages during the lifetime of a system, possibly causing misbehaviours or failures. In order to guarantee product quality and consumer satisfaction, it is necessary not only to discover faults as soon as possible in the manufacturing process, but also to continuously check for their absence throughout a product lifetime. Today’s modern systems have become increasingly complex to design and build, while the demand for reliability and cost effective development continues. Reliability is one of the most important attributes in all these systems, including aerospace applications, real-time control, medical care, defence equipment, transportation, communication, entertainment products, agriculture, energy and environmental systems. Growing international competition has increased the need for all designers, managers, practitioners, scientists and engineers to ensure a high level of reliability of their product before release and during mission time, at the lowest cost. The interest in reliability has been growing in recent years and this trend will continue during the next decade and beyond. With testers being expensive pieces of equipment and the cost of transistors continuously decreasing, it make sense to use some of these low-cost transistors to replace the costly test tools, whenever possible. The first low cost approach we can think about is using the devices themselves to implement their own test. This is the underlying motivation of functional Software-Based Self-Test (SBST): a fast, powerful microprocessor, which has lots of resources, could certainty help in its testing procedure. Having the outstanding advantages of enabling at-speed testing, zero area overhead and actually testing the device’s operation, this approach also has some drawbacks. Even if SBST is essentially suitable for online testing (and sometimes it is the only possible approach), it requires some dedicated system memory for the functional testing data, which can reach very big sizes. Also some faults happen to be functionally untestable; i.e., you cannot detect them exclusively by running proper software routines. For this reason a combination of both functional and structural test approaches is common practise. A second natural approach to low cost testing is design for test (DfT). Add some extra (cheap) area on-chip specifically in charge of performing and managing tests. The DfT path started long ago, but it is still a key element in 2012 International Technology Roadmap for Semiconductors (ITRS)[1] test roadmap. Different sorts of DfT enable the use of low cost testers, contributing to the full checking of a device, and may also be reused for online testing purposes. Logic and Memory Built-In Self Test (BIST) schemas are usual practises. Analogue DfT, even if it is not as advances as digital one, is also an interesting strategy, especially when the analogue or mixed-signal device is integrated in a wider digital system like a SoC Finally, there are some fields where the use of external (and generally expensive) testers is mandatory. Diagnosis is one of the cases in which an Automatic Test Equipment (ATE) is needed to store the huge amount of retrieved data and to drive the cyclic characteristic of the diagnosis procedure. In particular, even if memories are commonly tested making use of internal BIST structures, their diagnosis demands the use of a tester. Another interesting and blooming field is that of the mixed energy-domain devices as Micro Electro Mechanical Systems (MEMS). MEMS require unique testing apparatus applying both electrical and physical stimuli: movement, pressure, magnetic fields. Additionally, they not only need to be exhaustively tested but in most of the cases also calibrated. The work described in this thesis falls in low cost testing domain. Strategies for new and/or improved SBST, DfT and ATE mechanisms are proposed, implemented and evaluated. The strategies deal mainly with memories, processor and mixed-signal devices (analogue-to-digital converters is our target device) embedded in Systems-on-a-Chip, where standard communication protocols and wrappers are used to communicate with the device under test.

Apresentamos um estudo sistemático das propriedades eletrônicas e estruturais dos elementos N, P e AS em SI e GE amorfos. Primeiramente, utilizamos o método de Monte Carlo para gerar as configurações amorfas iniciais. Nesta etapa as interações atômicas são descritas pelos potencias de Tersoff. A partir do modelo inicial para os sistemas desordenados, as propriedades eletrônicas e estruturais são determinadas usando a teoria do funcional da densidade e os pseudopotenciais de Bachelet-Hamann-Schlüter. Concluímos que as impurezas de P e AS são estáveis em sítios tricoordenados e metaestáveis em sítios tetracoordenados para os dois sistemas hospedeiros. Por outro lado a impureza de N apresenta um comportamento diferente. Este átomo é estável em sítios tricoordenados para ambos os hospedeiros, mas em sítios tetracoordenados ele é instável no a-SI e metaestável no a-GE. Discutimos a relevância de nossos resultados relacionados com a dopagem tipo-n de semicondutores amorfos hidrogenados.
The electronic and structural properties of the elements N, P and AS in amorphous SI and GE are systematically investigated. The calculation procedure is based on two approaches. First, we have used the Monte Carlo method to generate the initial amorphous configurations. A reliable description of the atomic interaction is provided by using the Tersoff potentials. Having the initial model for the amorphous structure, we analyzed the electronic and structural configurations within the framework of the density-functional theory and the Bachelet-Hamann-Schlüter pseudopotentials. We found that the P and AS impurities are stable in 3-fold coordinated sites and metastable in 4-fold coordinated sites for both host systems. On the other hand, the N impurity presents a different behavior. This atom is stable in 3-fold coordinated sites for both host systems but in 4-fold coordinated sites it is unstable in a-SI and metastable in a-GE. The relevance of these results for the n-type doping in hydrogenated amorphous semiconductors is discussed.

Thin-film transistors (TFTs) capable of low-voltage and high-frequency operation will be required to reduce the power consumption of next generation electronic devices driven by microelectronic components such as inverters, ring oscillators, and backplane circuits for mobile displays. To produce high performance TFTs, transparent oxide-semiconductors are becoming an attractive alternative to hydrogenated amorphous silicon (a-Si:H)- and organic-based materials because of their high electron mobility vlaues and low processing temperatures, making them compatible with flexible substrates and opening the potential for low production costs. Practical electronic devices are expected to use p- and n-channel TFT-based complementary inverters to operate with low power consumption, high gain values, and high and balanced noise margins. The p- and n-channel TFTs should yield comparable output characteristics despite differences in the materials used to achieve such performance. However, most oxide semiconductors are n-type, and the only high performance, oxide-based TFTs demonstrated so far are all n-channel, which prevents the realization of complementary metal-oxide-semiconductor (CMOS) technologies. On the other hand, ambipolar TFTs are very attractive microelectronic devices because, unlike unipolar transistors, they operate independently of the polarity of the gate voltage. This intrinsic property of ambipolar TFTs has the potential to lead to new paradigms in the design of analog and digital circuits. To date, ambipolar TFTs and their circuits, such as inverters, have shown very limited performance when compared with that obtained in unipolar TFTs. For instance, the electron and hole mobilities typically found in ambipolar TFTs (ATFTs) are, typically, at least an order of magnitude smaller than those found in unipolar TFTs. Furthermore, for a variety of circuits, ATFTs should provide balanced currents during p- and n-channel operations. Regardless of the selection of materials, achieving these basic transistor properties is a very challenging task with the use of current device geometries. This dissertation presents research work performed on oxide TFTs, oxide TFT-based electronic circuits, organic-inorganic hybrid complementary inverters, organic-inorganic hybrid ambipolar TFTs, and ambipolar TFT-based complementary-like inverters in an attempt to overcome some of the current issues. The research performed first was to develop low-voltage and high-performance oxide TFTs, with an emphasis on n-channel oxide TFTs, using high-k and/or thin dielectrics as gate insulators. A high mobility electron transporting semiconductor, amorphous indium gallium zinc oxide (a-IGZO), was used as the n-channel active material. Such oxide TFTs were employed to demonstrate active matrix organic light emitting diode (AMOLED) display backplane circuits operating at low voltage. Then, high-performance hybrid complementary inverters were developed using unipolar TFTs employing organic and inorganic semiconductors as p- and n-channel layers, respectively. An inorganic a-IGZO and pentacene, a widely used organic semiconductor, were used as the n- and p-channel semiconductors, respectively. By the integration of the p-channel organic and n-channel inorganic TFTs, high-gain complementary inverters with high and balanced noise margins were developed. A new approach to find the switching threshold voltage and the optimum value of the supply voltage to operate a complementary inverter was also proposed. Furthermore, we proposed a co-planar channel geometry for the realization of high-performance ambipolar TFTs. Using non-overlapping horizontal channels of pentacene and a-IGZO, we demonstrate hybrid organic-inorganic ambipolar TFTs with channels that show electrical properties comparable to those found in unipolar TFTs with the same channel aspect ratios. A key characteristic of this co-planar channel ambipolar TFT geometry is that the onset of ambipolar operation is mediated by a new operating regime where one of the channels can reach saturation while the other channel remains off. This allows these ambipolar TFTs to reach high on-off current ratios approaching 104. With the new design flexibility we demonstrated organic-inorganic hybrid ambipolar TFT-based complementary-like inverters, on rigid and flexible substrates, that show a significant improvement over the performance found in previously reported complementary-like inverters. From a materials perspective, this work shows that future breakthroughs in the performance of unipolar n-channel and p-channel semiconductors could be directly transposed into ambipolar transistors and circuits. Hence, we expect that this geometry will provide new strategies for the realization of high-performance ambipolar TFTs and novel ambipolar microelectronic circuits.

In this thesis, a variety of algorithms for synthesis and optimisation of combinational and sequential logic circuits are developed. These algorithms could be part of new commercial EGAD package for future VLSI digital designs. The results show that considerable saving in components can be achieved resulting in simpler designs that are smaller, cheaper, consume less power and easier to test. The purpose of generating different sets of coefficients related to Reed Muller (RM) is that they contain different number of terms; therefore the minimum one can be selected to design the circuits with reduced gate count. To widen the search space and achieve better synthesis tools, representations of Mixed Polarity Reed Muller (MPRM), Mixed Polarity Dual Reed Muller (MPDRM), and Pseduo Kronecker Reed Muller (PKRO RM) expansions are investigated. Efficient and fast combinatorial techniques and algorithms are developed for the following: â Bidirectional conversion between MPRM/ MPDRM form and Fixed Polarity Reed Muller forms (FPRM)/Fixed Polarity Dual Reed Muller forms (FPDRM) form respectively. The main advantages for these techniques are their simplicity and suitability for single and multi output Boolean functions. â Computing the coefficients of any polarity related to PKRO_RM class starting from FPRM coefficients or Canonical Sum of Products (CSOP). â Computing the coefficients of any polarity related to MPRM/or MPDRM directly from standard form of CSOP/Canonical Product of sums (CPOS) Boolean functions, respectively. The proposed algorithms are efficient in terms of CPU time and can be used for large functions. For optimisation of combinational circuits, new techniques and algorithms based on algebraic techniques are developed which can be used to generate reduced RM expressions to design circuits in RM/DRM domain starting from FPRM/FPDRM, respectively. The outcome for these techniques is expansion in Reed Muller domain with minimal terms. The search space is 3`" Exclusive OR Sum of Product (ESOP)/or Exclusive NOR Product of Sums (ENPOS) expansions. Genetic Algorithms (GAs) are also developed to optimise combinational circuits to find optimal MPRM/MPDRM among 3° different polarities without the need to do exhaustive search. These algorithms are developed for completely and incompletely specified Boolean functions. The experimental results show that GA can find optimum solutions in a short time compared with long time required running exhaustive search in all the benchmarks tested. Multi Objective Genetic Algorithm (MOGA) is developed and implemented to determine the optimal state assignment which results in less area and power dissipation for completely and incompletely specified sequential circuits. The goal is to find the best assignments which reduce the component count and switching activity simultaneously. The experimental results show that saving in components and switching activity are achieved in most of the benchmarks tested compared with recently published research. All algorithms are implemented in C++.

In conventional pipelined circuits there is only one data wave active in any pipeline stage at any time; therefore, the clock speed of the circuit is limited by the maximum stage delay in the circuit. In wave pipelining, the clock speed depends mostly on the difference between the longest and shortest path delays. In some circuit designs there are redundant elements to make the circuit less sensitive to noise, to provide higher signal driving capability, or other purposes. Also, some circuit designs include logic to detect the early completion of a computation, or to guarantee that the worst physical path delay does not equate to the worst computational delay. Prior tools for wave-pipelined circuits do not account for such design features. This research develops a computer-aided design tool to determine the maximum clock speed for wave pipelined circuits with redundant logic or where otherwise the internal circuit timing depends on the input signal values. Moreover, alternative design techniques are proposed to improve the performance of wave pipelined circuits.
Includes bibliographic references (leaves 39-41)
Thesis (M.S.)--Wichita State University, Dept. of Electrical and Computer Engineering.
"May 2006."
Includes bibliographic references (leaves 39-41)

Over the last decades, Organic Electronics has been emerging as a multidisciplinary and innovative way to generate electronic devices and systems. It is intended to provide a platform for low-cost, large-area, and low-frequency Printable Electronics on a variety of substrates, including flexible plastic substrates. Just as the first information revolution caused by integrated silicon circuits, PE is expected to cause another revolution characterized by the distribution of information systems in all aspects of life. Although the integrated circuits, based on Organic Thin Film Transistors (OTFT), are not meant to compete with the silicon-based high-end industry, their performance have already reached to a level enabling the use of organic technology to an ever-increasing number of emerging applications, such as flexible optical displays, sensors, and low-end microelectronics. Currently, most of the digital integrated circuits are yet designed by specifying the layout of each individual transistor and their interconnections. Full-custom design is extremely labor-intensive, time consuming for complex circuits and it requires advanced computer software in the design process, and several expensive mask sets in the fabrication process. Besides, taking the soft and hard faults at transistor level into account, the yield at system level is expected to be very low, since failure of one transistor causes the entire circuit to fail. This is more important for technologies based in non-crystalline materials (such as silicon) in which deposition and layer formation is more irregular. On the other side, organic electronics is more complex than Printed Circuit Boards (PCB) in the sense that these do not include active devices and do not reach high integration level. Furthermore, similar to any new-born technology, the performance of organic electronic circuits is degraded due to some limitations in technological and materials sides. That being said, the question arises as to whether circuit design techniques can be employed to compensate these bottlenecks so as to meet yield and performance requirements. The work presented in this thesis contributes to overcome the above-mentioned issues by proposing the novel concept of Inkjet-configurable Gate Array (IGA) as a designmanufacturing method for the direct mapping of digital functions on top of new prefabricated structures. IGA brings together the advantages of semi-custom gate array methodology, field-configurability, and fault-tolerance, and adopt it to Application Specific Printed Electronic Circuit (ASPEC), which is the equivalent term to Application Specific Integrated Circuit (ASIC), but for PE. This alternative has two main advantages. Firstly, it allows implementing individual circuit personalization at a very low cost through the best use of additive mask-less digital printing techniques (e.g. Inkjet, Superfine Jet, and etc.) "in the field", thus avoiding the need for One Time Programmable ROM-like (or E2PROM) devices. Secondly, fault tolerance technique allows the adoption of a failure map to use only working transistors for circuit implementation, thus, it helps to obtain high yield circuits out of mid-yield foils.