Academic literature on the topic 'Electroplating. Indium. Indium sulphate'

In hybrid pixel detector fabrication, high-density interconnection between focal plane array and the read-out integrated circuit is important. Bump bonding is the preferable assembly method, it is small in size, low cost, high performance and flexible I/O. Flip-chip bonding is a vertical connection technique of focal plane array and top substrate with solder bumps. In this paper, Flip-chip bonding by electroplated indium bumps is described. There are advantages of using indium as the solder material. It is relatively inexpensive, it has good thermal and electrical conductivity, it is ductile, and it is cryogenically stable. Indium bumps with a diameter of 30 µm are successfully prepared by an electroplating method, however removing indium conductive layer after electrodeposition is challenging. The corresponding electroplating indium bump process is also discussed. Electrical measurement was applied to detect the connection integrity of the flip-chip assemblies.

Microelectronics integration continuously follows the trend of miniaturisation for which the technologies enabling fine pitch interconnection are in high demand. The recent advancement in the assembly of Hybrid Pixel Detectors, a high resolution detecting and imaging device, is an example of where novel materials and processes can be applied for ultra-fine pitch interconnections. For this application, indium is often used for the fine pitch bump bonding process due to its unique properties that make it especially suitable, in particular in a cryogenic environment where some types of detector have to serve. Indium bumps are typically fabricated through vacuum evaporation at the wafer level; however, this thesis investigates an alternative low cost manufacturing process at the wafer scale for the deposition of indium micro-bumps through electroplating. The work has placed its emphasis on the requirements of future technologies which will enable a low temperature (<150oC), high density interconnection (> 40,000 IOs/cm2) with a high throughput and high production yield. This research is a systematic investigation of the wafer-scale indium bumping process through electrodeposition using indium sulphamate solution. An intensive experimental study of micro-bump formation has been carried out to elaborate the effects of two of the main electroplating factors that can significantly influence the quality of bumps in the course of electrodeposition, namely the current distribution and mass transport. To adjust the current density distribution, various waveforms of current input, including direct current (DC), unipolar pulse current and bipolar pulse reverse current, were employed in the experiments. To assist mass transportation prior to or during electroplating, acoustic agitation including ultrasonic agitation at 30 kHz frequency as well as megasonic agitation at 1 MHz, were utilised. The electrochemical properties of the indium sulphamate solution were first investigated using non-patterned plain substrates prior to indium bumping trials. This provided understanding of the microstructural characteristics of indium deposits produced by electroplating and, through cathodic polarisation measurements, the highest current density suitable for electrodeposition was achieved as approximately 30 mA/cm2 when electroplating was carried out at room temperature and with no agitation applied. The typical surface morphology of DC electroplated indium contained a granular structure with a surface feature size as large as 10 µm. Pulse and pulse reverse electroplating significantly altered the surface morphology of the deposits and the surface became much smoother. By introducing acoustic agitation, the current density range suitable for electrodeposition could be significantly expanded due to the greater mass transfer, which led to a higher speed of deposition with high current efficiency. Wafer-scale indium bumping (15 µm to 25 µm diameter) at a minimum pitch size of 25 µm was successfully developed through electroplating trials with 3 inch test wafers and subsequently applied onto the standard 4 inch wafers. The results demonstrate the capability of electroplating to generate high quality indium bumps with ultrafine pitch at a high consistency and yield. To maximise the yield, pre-wetting of the ultrafine pitch photoresist patterns by both ultrasonic or megasonic agitation is essential leading to a bumping yield up to 99.9% on the wafer scale. The bump profiles and their uniformity at both the wafer and pattern scale were measured and the effects of electrodeposition regimes on the bump formation evaluated. The bump uniformity and microstructure at the feature scale were also investigated by cross-sectioning the electroplated bumps from different locations on the wafers. The growth mechanism of indium bumps were proposed on the basis of experimental observation. It was found that the use of a conductive current thief ring can homogenise the directional bump uniformity when the electrical contact is made asymmetrically, and improve the overall uniformity when the electrical contact is made symmetrically around the periphery of the wafer. Both unipolar pulse electroplating and bipolar pulse reverse electroplating improved the uniformity of the bump height at the wafer scale and pattern scale, and the feature scale uniformity could be significantly improved by pulse reverse electroplating. The best uniformity of 13.6% for a 4 inch wafer was achieved by using pulse reverse electroplating. The effect of ultrasonic agitation on the process was examined, but found to cause damage to the photoresist patterns if used for extended periods and therefore not suitable for use throughout indium bumping. Megasonic agitation enabled high speed bumping without sacrifice of current efficiency and with little damage to the photoresist patterns. However, megasonic agitation tended to degrade some aspects of wafer scale uniformity and should therefore be properly coupled with other electroplating parameters to assist the electroplating process.

The author presents the successful development of an on-chip, monolithic, integrated rubidium vapor-cell. These vapor-cells integrate ridge waveguide techniques with hollow-core waveguiding technology known as Anti-Resonant Reflecting Optical Waveguides (ARROWs). These devices are manufactured on-site in BYU's Integrated Microelectronic Laboratory (IML) using common silicon wafer microfabrication techniques. The ARROW platform fabrication is outlined, but the bulk of the dissertation focuses on novel packaging techniques that allow for the successful introduction and sealing of rubidium vapor into these micro-sized vapor-cells. The unique geometries and materials utilized in the ARROW platform render common vapor-cell sealing techniques unusable. The development of three generations of successful vapor-cells is chronicled. The sealing techniques represented in these three generations of vapor-cells include high-temperature epoxy seals, cold-weld copper crimping, variable pressure vacuum capabilities, indium solder seals, and electroplated passivation coatings. The performance of these seals are quantified using accelerated lifetime tests combined with optical spectroscopy. Finally, the successful probing of the rubidium absorption spectrum, electromagnetically induced transparency, and slow light on the ARROW-based vapor-cell platform is reported.

This thesis presents rubidium packaging methods for integration using anti-resonant reflecting optical waveguides (ARROWs) on a planar chip. The atomic vapor ARROW confines light through rubidium vapor, increases the light-vapor interaction length, decreases the size of the atomic cell to chip scales, and opens up possibilities for waveguide systems on chips for additional optoelectronic devices. Rubidium vapor packaging for long-life times are essential for realizing feasibly useful devices. Considerations of outgassing, leaking and chemical compatibilities of materials in rubidium vapor cells lead to an all-metal design. The effect of these characteristics on the rubidium D2 line spectra is considered.

碩士<br>國立成功大學<br>微電子工程研究所碩博士班<br>96<br>With the development of solid-state lighting, the chief bottlenecks of replacing traditional lamps with light emitting diodes (LEDs) were enhancements in luminance and effective thermal management. In this paper, we increase light extraction efficiency with micro-textured indium tin oxide by wet etching, instead of surface-roughening treatment by ICP. Applying this technique to traditional GaN LEDs, we get improvements in optical and electrical characteristics. As for thermal management, generally speaking, for GaN LEDs, laser lift-off technique is the most common process for improving heat dissipation, hereafter, no matter the fabrication of metal substrate is wafer bonding or electroplating, the thermal conductivity of metal will be much better than that of original sapphire substrate. The vertical GaN LEDs will be discussed in this paper, combining with micro-textured indium tin oxide above mentioned to improve the optical and electrical properties of vertical GaN LEDs. Before lifting off sapphire substrates of GaN LEDs by KrF excimer laser, we employ the electroplating technique to deposit thick copper layer on the other side of sapphire substrate, and finally, the vertical GaN LEDs with copper substrates were fabricated successfully. To avoid dicing problems of copper substrates, separating each chip by defining thick photoresist on pitch between chips before rack copper electroplating is the better process in our experiments at present.