Dissertations / Theses on the topic 'Electrostatic discharge'

Thesis (Ph. D.) -- University of Maryland, College Park, 2005.<br>Thesis research directed by: Mechanical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

In this thesis, a system to locate an electrostatic discharge (ESD) event within an electronic device has been developed. ESD can cause a device to fail legally required radiated emissions limits as well as disrupt intended operation. The system used a fast oscilloscope with four channels, each channel attached to a high frequency near-field antenna. These antennas were placed at known locations in three dimensional space to measure the fields radiated from the ESD event. A Time-Difference-of-Arrival technique was used to calculate the location of the ESD event. Quick determination of the ESD event location provides developers with a tool that saves them time and money by eliminating the time-consuming and tedious method of general ESD mitigation within a product.

This thesis presents an experimental and theoretical investigation of electrical failure in MOS structures, with a particular emphasis on short-pulse and ESD failure. It begins with an extensive survey of MOS technology, its failure mechanisms and protection schemes. A program of experimental research on MOS breakdown is then reported, the results of which are used to develop a model of breakdown across a wide spectrum of time scales. This model, in which bulk-oxide electron trapping/emission plays a major role, prohibits the direct use of causal theory over short time-scales, invalidating earlier theories on the subject. The work is extended to ESD stress of both polarities. Negative polarity ESD breakdownis found to be primarily oxide-voltage activated, with no significant dependence on temperature of luminosity. Positive polarity breakdown depends on the rate of surface inversion, dictated by the Si avalanche threshold and/or the generation speed of light-induced carriers. An analytical model, based upon the above theory is developed to predict ESD breakdown over a wide range of conditions. The thesis ends with an experimental and theoretical investigation of the effects of ESD breakdown on device and circuit performance. Breakdown sites are modelled as resistive paths in the oxide, and their distorting effects upon transistor performance are studied. The degradation of a damaged transistor under working stress is observed, giving a deeper insight into the latent hazards of ESD damage.

Electrostatic discharges have been identified as the most likely cause in a number of incidents of fire and explosion with unexplained ignitions. The lack of data and suitable models for this ignition mechanism creates a void in the analysis to quantify the importance of static electricity as a credible ignition mechanism. Quantifiable hazard analysis of the risk of ignition by static discharge cannot, therefore, be entirely carried out with our current understanding of this phenomenon. The study of electrostatics has been ongoing for a long time. However, it was not until the wide spread use of electronics that research was developed for the protection of electronics from electrostatic discharges. Current experimental models for electrostatic discharge developed for intrinsic safety with electronics are inadequate for ignition analysis and typically are not supported by theoretical analysis. A preliminary simulation and experiment with low voltage was designed to investigate the characteristics of energy dissipation and provided a basis for a high voltage investigation. It was seen that for a low voltage the discharge energy represents about 10% of the initial capacitive energy available and that the energy dissipation was within 10 ns of the initial discharge. The potential difference is greatest at the initial break down when the largest amount of the energy is dissipated. The discharge pathway is then established and minimal energy is dissipated as energy dissipation becomes greatly influenced by other components and stray resistance in the discharge circuit. From the initial low voltage simulation work, the importance of the energy dissipation and the characteristic of the discharge were determined. After the preliminary low voltage work was completed, a high voltage discharge experiment was designed and fabricated. Voltage and current measurement were recorded on the discharge circuit allowing the discharge characteristic to be recorded and energy dissipation in the discharge circuit calculated. Discharge energy calculations show consistency with the low voltage work relating to discharge energy with about 30-40% of the total initial capacitive energy being discharged in the resulting high voltage arc. After the system was characterised and operation validated, high voltage ignition energy measurements were conducted on a solution of n-Pentane evaporating in a 250 cm3 chamber. A series of ignition experiments were conducted to determine the minimum ignition energy of n-Pentane. The data from the ignition work was analysed with standard statistical regression methods for tests that return binary (yes/no) data and found to be in agreement with recent publications. The research demonstrates that energy dissipation is heavily dependent on the circuit configuration and most especially by the discharge circuit's capacitance and resistance. The analysis established a discharge profile for the discharges studied and validates the application of this methodology for further research into different materials and atmospheres; by systematically looking at discharge profiles of test materials with various parameters (e.g., capacitance, inductance, and resistance). Systematic experiments looking at the discharge characteristics of the spark will also help understand the way energy is dissipated in an electrostatic discharge enabling a better understanding of the ignition characteristics of materials in terms of energy and the dissipation of that energy in an electrostatic discharge.

Electrical insulation under high voltage can eventually fail, causing critical damage to electronics. Such electrostatic discharge (ESD) is the primary source of anomalies or failures on spacecraft due to charged particles from the Sun or planetary radiation belts accumulating in spacecraft insulators. Highvoltage direct current power distribution is another example of a growing industry that needs to estimate the operational lifetime of electrical insulation. My research compares laboratory tests of ESD events in common insulating materials to a physics-based model of breakdown. This model of breakdown is based on the approximation that there are two primary types of defects in structurally amorphous insulators. One of the two defect modes can switch on and off depending on the material temperature. This dual-defect model can be used to explain both ESD and less-destructive transient partial discharges. I show that the results of ESD tests agree reasonably well with the dual defect model. I also show that transient partial discharges, which are usually ignored during ESD tests, are closely related to the probability of catastrophic ESD occurring. Since many partial discharges are typically seen during one ESD test, this relationship suggests that the measurements of partial discharges could accelerate the testing needed to characterize the likelihood of ESD in insulating materials.

Corona discharge is one of the crucial problems related with high-voltage equipment. This paper focuses on the physical and numerical modelling of corona discharge in an Electrostatic precipitator (ESP). The model is based on Maxwells equations and the Finite element method (FEM) and is implemented with the COMSOL Multiphysics software.The simulation allows studying the electric charge distribution and the behaviour of the electric field inside the ESP. The work is focused primarily on time-dependent studies of the corona discharge.

Another issue with SCR devices is its deep snapback or lower holding voltage, which normally will lead to the latch-up happen. To make SCR devices be immunity with latch-up, it is required to elevate its holding voltage to be larger than the circuits operational voltage, which can be several tens volts in modern power electronic circuits. Two possible solutions have been proposed to resolve this issue. One solution is accomplished by using a segmented emitter topology based on the concept that the holding voltage can be increased by reducing the emitter injection efficiency. Experimental data show that the new SCR can posses a holding voltage that is larger than 40V and a failure current It2 that is higher than 28mA/um. The other solution is accomplished by stacking several low triggering voltage high holding voltage SCR cells together. The TLP measurement results show that this novel SCR stacking structure has an extremely high holding voltage, very small snapback, and acceptable failure current. The High Holding Voltage Figure of Merit (HHVFOM) has been proposed to be a criterion for different high holding voltage solutions. The HHVFOM comparison of our proposed structures and the existing high holding voltage solutions also show the advantages of our work.; Electrostatic Discharge (ESD) phenomenon happens everywhere in our daily life. And it can occurs through the whole lifespan of an Integrated Circuit (IC), from the early wafer fabrication process, extending to assembly operation, and finally ending at the user's site. It has been reported that up to 35% of total IC field failures are ESD-induced, with estimated annual costs to the IC industry running to several billion dollars. The most straightforward way to avoid the ICs suffering from the threatening of ESD damages is to develop on-chip ESD protection circuits which can afford a robust, low-impedance bypassing path to divert the ESD current to the ground. There are three different types of popular ESD protection devices widely used in the industry, and they are diodes or diodes string, Grounded-gate NMOS (GGNMOS) and Silicon Controlled Rectifier (SCR). Among these different protection solutions, SCR devices have the highest ESD current conduction capability due to the conductivity modulation effect. But SCR devices also have several shortcomings such as the higher triggering point, the lower clamping voltage etc, which will become obstacles for SCR to be widely used as an ESD protection solutions in most of the industry IC products. At first, in some applications with pin voltage goes below ground or above the VDD, dual directional protection between each two pins are desired. The traditional dual-directional SCR structures will consume a larger silicon area or lead to big leakage current issue due to the happening of punch-through effect. A new and improved SCR structure for low-triggering ESD applications has been proposed in this dissertation and successfully realized in a BiCMOS process. Such a structure possesses the desirable characteristics of a dual-polarity conduction, low trigger voltage, small leakage current, large failing current, adjustable holding voltage, and compact size.<br>ID: 029094215; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2010.; Includes bibliographical references (p. 72-78).<br>Ph.D.<br>Doctorate<br>School of Electrical Engineering and Computer Science<br>Engineering and Computer Science

Electrostatic discharge is of great concern to the electronics industry. It degrades and destroys large numbers of integrated circuits at every step from fabrication through packaging and testing. The goal of this research effort was the development of a device that can be used to obtain quantitative information on electrostatic discharge (ESD) in the integrated-circuit workplace. The device that was developed can be utilized in two different modes. (1) It can be used to form ESD test wafers or test chips. (2) It can be incorporated on product chips to give the ESD history of devices or monitor the process line. The technology that was examined in this work was that for floating-gate PROMS. A simple analytical model for obtaining a parameter called the ESD factor was developed. The prototype detector was designed, fabricated and tested in the Semiconductor Processing Facility of the University of Arizona. Evidence will be presented that the FLOTOX type of EEPROM functions well in its application as an ESD detector.

A MEMS-based micro-electro-discharge machining technique that is enabled by the actuation of micromachined planar electrodes defined on the surfaces of the workpiece is developed that eliminates the need of numerical control machines. First, the planar electrodes actuated by hydrodynamic force is developed. The electrode structures are defined by patterning l8-µm-thick copper foil laminated on the stainless steel workpiece through an intermediate photoresist layer and released by sacrificial etching of the resist layer. The planer electrodes are constructed to be single layer structures without particular features underneath. All the patterning and sacrificial etching steps are performed using dry-film photoresists towards achieving high scalability of the machining technique to large-area applications. A DC voltage of 80-140 V is applied between the electrode and the workpiece through a resistance-capacitance circuit that controls the pulse energy and timing of spark discharges. The parasitic capacitance of the electrode structure is used to form a resistance capacitance circuit for the generation of pulsed spark discharge between the electrode and the workpiece. The suspended electrodes are actuated towards the workpiece using the downflow of dielectric machining fluid, initiating and sustaining the machining process. Micromachining of stainless steel is experimentally demonstrated with the machining voltage of 90V and continuous flow of the fluid at the velocity of 3.4-3.9 m/s, providing removal depth of 20 µm. The experimental results of the electrode actuation match well with the theoretical estimations. Second, the planar electrodes are electrostatically actuated towards workpiece for machining. In addition to the single-layer, this effort uses double-layer structures defined on the bottom surface of the electrode to create custom designed patterns on the workpiece material. The suspended electrode is electrostatically actuated towards the wafer based on the pull-in, resulting in a breakdown, or spark discharge. This instantly lowers the gap voltage, releasing the electrode, and the gap value recovers as the capacitor is charged up through the resistor. Sequential pulses are produced through the self-regulated discharging-charging cycle. Micromachining of the stainless-steel wafer is demonstrated using the electrodes with single-layer and double-layer structures. The experimental results of the dynamic built-capacitance and mechanical behavior of the electrode devices are also analyzed.

Electrostatic Discharge (ESD) is a significant hazard to electronic components and systems. Based on a specific processing technology, a given circuit application requires a customized ESD consideration that includes the devices' operating voltage, leakage current, breakdown constraints, and footprint. As new technology nodes mature every 3-5 years, design of effective ESD protection solutions has become more and more challenging due to the narrowed design window, elevated electric field and current density, as well as new failure mechanisms that are not well understood. The endeavor of this research is to develop novel, effective and robust ESD protection solutions for both emerging technologies and modern complementary metal–oxide–semiconductor (CMOS) technologies. The Si nanowire field-effect transistors are projected by the International Technology Roadmap for Semiconductors as promising next-generation CMOS devices due to their superior DC and RF performances, as well as ease of fabrication in existing Silicon processing. Aiming at proposing ESD protection solutions for nanowire based circuits, the dimension parameters, fabrication process, and layout dependency of such devices under Human Body Mode (HBM) ESD stresses are studied experimentally in company with failure analysis revealing the failure mechanism induced by ESD. The findings, including design methodologies, failure mechanism, and technology comparisons should provide practical knowhow of the development of ESD protection schemes for the nanowire based integrated circuits. Organic thin-film transistors (OTFTs) are the basic elements for the emerging flexible, printable, large-area, and low-cost organic electronic circuits. Although there are plentiful studies focusing on the DC stress induced reliability degradation, the operation mechanism of OTFTs subject to ESD is not yet available in the literature and are urgently needed before the organic technology can be pushed into consumer market. In this work, the ESD operation mechanism of OTFT depending on gate biasing condition and dimension parameters are investigated by extensive characterization and thorough evaluation. The device degradation evolution and failure mechanism under ESD are also investigated by specially designed experiments. In addition to the exploration of ESD protection solutions in emerging technologies, efforts have also been placed in the design and analysis of a major ESD protection device, diode-triggered-silicon-controlled-rectifier (DTSCR), in modern CMOS technology (90nm bulk). On the one hand, a new type DTSCR having bi-directional conduction capability, optimized design window, high HBM robustness and low parasitic capacitance are developed utilizing the combination of a bi-directional silicon-controlled-rectifier and bi-directional diode strings. On the other hand, the HBM and Charged Device Mode (CDM) ESD robustness of DTSCRs using four typical layout topologies are compared and analyzed in terms of trigger voltage, holding voltage, failure current density, turn-on time, and overshoot voltage. The advantages and drawbacks of each layout are summarized and those offering the best overall performance are suggested at the end.<br>Ph.D.<br>Doctorate<br>Electrical Engineering and Computer Science<br>Engineering and Computer Science<br>Electrical Engineering

Electro-Static Discharge (ESD) problems in the semiconductor industry are exacerbated by the lack of information about the magnitudes of these events and their locations. This thesis describes an integrated device, similar in structure to an EEP-ROM cell, capable of measuring the magnitudes and polarities of electrostatic discharges. A quantitative formulation of the transfer characteristic of the device as a function of the design parameters and the subsequent layout, manufacturing and evaluation of this detector was obtained. A chip was fabricated which included experiments to test the presented mathematical model and its extensive range of sensitivity, as well as several structures to evaluate the use of this detector in industrial environments. Extensive use of computers helped in the process design and in the simulation of the non-linear model for the operation.

Electrostatic discharge (ESD) is defined as the transfer of charge between bodies at different potentials. The electrostatic discharge induced integrated circuit damages occur throughout the whole life of a product from the manufacturing, testing, shipping, handing, to end user operating stages. This is particularly true as microelectronics technology continues shrink to nano-metric dimensions. The ESD related failures is a major IC reliability concern and results in a loss of millions dollars to the semiconductor industry each year. Several ESD stress models and test methods have been developed to reproduce the real world ESD discharge events and quantify the sensitivity of ESD protection structures. The basic ESD models are: Human body model (HBM), Machine model (MM), and Charged device model (CDM). To avoid or reduce the IC failure due to ESD, the on-chip ESD protection structures and schemes have been implemented to discharge ESD current and clamp overstress voltage under different ESD stress events. Because of its simple structure and good performance, the junction diode is widely used in on-chip ESD protection applications. This is particularly true for ESD protection of low-voltage ICs where a relatively low trigger voltage for the ESD protection device is required. However, when the diode operates under the ESD stress, its current density and temperature are far beyond the normal conditions and the device is in danger of being damaged. For the design of effective ESD protection solution, the ESD robustness and low parasitic capacitance are two major concerns. The ESD robustness is usually defined after the failure current It2 and on-state resistance Ron. The transmission line pulsing (TLP) measurement is a very effective tool for evaluating the ESD robustness of a circuit or single element. This is particularly helpful in characterizing the effect of HBM stress where the ESD-induced damages are more likely due to thermal failures.; The recent industry data indicates the charged device model (CDM) ESD event becomes increasingly important in today's manufacturing environment and packaging technology. This event generates highly destructive pulses with a very short rise time and very small duration. TLP has been modified to probe CDM ESD protection effectiveness. The pulse width was reduced to the range of 1-10 ns to mimic the very fast transient of the CDM pulses. Such a very fast TLP (VFTLP) testing has been used frequently for CDM ESD characterization. The overshoot voltage and turn-on time are two key considerations for designing the CDM ESD protection devices. A relatively high overshoot voltage can cause failure of the protection devices as well as the protected devices, and a relatively long turn-on time may not switch on the protection device fast enough to effectively protect the core circuit against the CDM stress. The overshoot voltage and turn-on time of an ESD protection device can be observed and extracted from the voltage versus time waveforms measured from the VFTLP testing. Transient behaviors of polysilicon-bound diodes subject to pulses generated by the VFTLP tester are characterized for fast ESD events such as the charged device model. The effects of changing devices' dimension parameters on the transient behaviors and on the overshoot voltage and turn-on time are studied. The correlation between the diode failure and poly-gate configuration under the VFTLP stress is also investigated. Silicon-controlled rectifier (SCR) is another widely used ESD device for protecting the I/O pins and power supply rails of integrated circuits. Multiple fingers are often needed to achieve optimal ESD protection performance, but the uniformity of finger triggering and current flow is always a concern for multi-finger SCR devices operating under the post-snapback region.; Two types of diodes with different anode/cathode isolation technologies will be investigated for their ESD performance: one with a LOCOS (Local Oxidation of Silicon) oxide isolation called the LOCOS-bound diode, the other with a polysilicon gate isolation called the polysilicon-bound diode. We first examine the ESD performance of the LOCOS-bound diode. The effects of different diode geometries, metal connection patterns, dimensions and junction configurations on the ESD robustness and parasitic capacitance are investigated experimentally. The devices considered are N+/P-well junction LOCOS-bound diodes having different device widths, lengths and finger numbers, but the approach applies generally to the P+/N-well junction diode as well. The results provide useful insights into optimizing the diode for robust HBM ESD protection applications. Then, the current carrying and voltage clamping capabilities of LOCOS- and polysilicon-bound diodes are compared and investigated based on both TCAD simulation and experimental results. Comparison of these capabilities leads to the conclusion that the polysilicon-bound diode is more suited for ESD protection applications due to its higher performance. The effects of polysilicon-bound diode's design parameters, including the device width, anode/cathode length, finger number, poly-gate length, terminal connection and metal topology, on the ESD robustness are studied. Two figures of merits, FOM_It2 and FOM_Ron, are developed to better assess the effects of different parameters on polysilicon-bound diode's overall ESD performance. As latest generation package styles such as mBGAs, SOTs, SC70s, and CSPs are going to the millimeter-range dimensions, they are often effectively too small for people to handle with fingers.; Without a proper understanding of the finger turn-on mechanism, design and realization of robust SCRs for ESD protection applications are not possible. Two two-finger SCRs with different combinations of anode/cathode regions are considered, and their finger turn-on uniformities are analyzed based on the I-V characteristics obtained from the transmission line pulsing (TLP) tester. The dV/dt effect of pulses with different rise times on the finger turn-on behavior of the SCRs are also investigated experimentally. In this work, unless noted otherwise, all the measurements are conducted using the Barth 4002 transmission line pulsing (TLP) and Barth 4012 very-fast transmission line pulsing (VFTLP) testers.<br>ID: 029050342; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2010.; Includes bibliographical references (p. 92-100).<br>Ph.D.<br>Doctorate<br>Department of Electrical Engineering and Computer Science<br>Engineering and Computer Science

The contious reduction in size and work voltage of the new generation integrated circuits (ICs) requires the reducction of the thickness of the different layers that make up (especially the gate oxides and levels of isolation between conductors), in order to increase its density and speed of integration, reducing its energy consumption. However, these improvements involve an increase in their sensitivity to external perturbations such as fluctuations in the electricity network, capacitive coupling or electrostatic discharge (ESD). <br/>Although there is a wide range of electronic devices designed to protect ICs from such disturbances avoiding destruction (Zener diodes, thyristors, etc.), The continuous reduction of voltage operation and increasing the frequency of work has required a major research effort to adapt the protective devices to the new conditions of operation. <br/>The main features that should satisfy any device designed to protect an electronic system are: fast response, low parasitic capacity, driving in low resistance, high absorption capacity of current, low leakage current in reverse, minimum size, low cost, should not interfere in the normal mode of operation of the system that protects and must maintain unchanged its electrical characteristics over time. <br/>In high voltage applications, Zener diodes and thyristors are the most used, both in format as a discreet way to the monolithic IC, for protection against ESD phenomena. However, new generations of ICs for mobile applications (portable computers, telecommunications, remote control systems, etc.) Require devices capable of working at low voltage and low energy consumption (in order to maximize the life of batteries ). Under these conditions, the protection of traditional elements are not optimal, so that further protection devices with low voltage and low shooting leakage current in his block state. <br/>In this situation, the use of new protective structures based on a process of rupture by emptying (punch-through) improves the characteristics of those based on a break by avalanche (base of the traditional components). Thus, this study aims to analyze, optimize, design and produce new elements of protection by breaking with punch-through, known as Transient Voltage Suppressors (TVS), which improve the performance of Zener diodes in applications from low tension (less than 3 V). <br/>Thus, Chapter 1 describes the main electric perturbation and sources that originated, along with a description of its effect on the CIs. It also provides a description of the different existing devices suppressors, with special emphasis on TVS, the main topic for this work. <br/>In Chapter 2 presents a study of the vertical TVS based in the punch-through effect, which analyzes the electrical characteristics of its two configurations (TVS 3 layers, TVS 4 layers). It also presents the theoretical model of rupture developed for this type of structures as well as the verification of it through numerical simulations and experimental data. <br/>Chapter 3 deals with the design, fabrication and characterization of vertical TVS. We show the technological processes done and the improvements are detailed, demonstrating the superiority of TVS 4 layers respect to the TVS 3 layers and Zener diodes. <br/>Chapter 4 presents the first study published on lateral punch-through TVS devices intended to be integrated with the circuitry to protect. The study was conducted for different configurations proposed in technology Bulk Silicon, compared among themselves and choose the configuration that shows better characteristics. This chapter also presents a novel way of using the field plate to reduce the breakdown voltage into the lateral TVS. Finally, and as a line of the future, assessing the feasibility of integrating lateral TVS devices in SOI (Silicon-On-Insulator) substrates. <br/>Finally, Chapter 5 shows the manufacturing of lateral TVS. Details the technological process, the design of masks, clean room manufacturing in the characterization and finally, whether technological, using techniques of Reverse Engineering, as electric.

Cette thèse de doctorat s’inscrit dans la thématique de la fiabilité des circuits intégrés dans l’industrie de la microélectronique. Un circuit intégré peut être exposé à des agresseurs électriques potentiellement dangereux pendant toute sa durée de vie. Idéalement, les circuits devraient pouvoir encaisser ces excès d’énergie sans perdre leur fonctionnalité. En réalité, des défaillances peuvent être observées lors de tests de qualification ou en application finale. Il est donc dans l’intérêt des fabricants de réduire ces défaillances. Actuellement, il existe des circuits de protection sur puce conçus pour dévier l’énergie de ces agresseurs à l’écart des composants fragiles. Le terme anglophone Electrical Overstress (EOS) englobe tous les agresseurs électriques qui dépassent une limite au-delà de laquelle les composants peuvent être détruits. La définition de ce terme est traitée en détail dans la thèse. L’objectif de cette thèse est de comprendre le statut du sujet des EOS dans l’industrie. On propose ensuite une nouvelle méthodologie de caractérisation de circuits pour quantifier leur robustesse face à des formes d’onde représentatives présélectionnées. On propose également des solutions de circuits de protection sur puce que ce soit au niveau de nouveaux composants actifs ou au niveau de la conception des circuits électroniques de protection. Par exemple on propose un nouveau composant basé sur le thyristor qui a la capacité de s’éteindre même si la tension d’alimentation est présente sur l’anode. Une autre proposition est de désactiver les circuits de protection face aux décharges électrostatiques lorsque les puces sont dans un environnement où l’on est sur ou ces agresseurs ne présentent plus de danger. Finalement, des perspectives du travail de thèse sont citées<br>This Ph.D. thesis concerns reliability issues in the microelectronics industry for the most advanced technology nodes. In particular, the Electrical OverStress (EOS) issue is studied. Reducing EOS failures in Integrated Circuits (ICs) is becoming more and more important. However, the EOS topic is very complex and involves many different causes, viewpoints, definitions and approaches. In this context, a complete analysis of the current status of the EOS issue is carried out. Then, the Ph.D. objectives can be defined in a clear way. In particular, robustness increase of on-chip protection structures and IC characterization against EOS-like aggressors are two of the main goals. In order to understand and quantify the behavior of ICs against these aggressors, a dedicated EOS test bench is put in place along with the definition of a characterization methodology. A full characterization and comparison is performed on two different Electro- Static Discharge (ESD) power supply clamps. After identifying the potential weaknesses of the promising Silicon-Controlled Rectifier (SCR) device, a new SCR-based device with a turn-off capability is proposed and studied thanks to 3-D Technology Computer-Aided Design (TCAD)simulation. Triggering and turn-off behaviors are studied, as well as its optimization. Finally, three different approaches are proposed for improving the robustness of the IC onchip protection circuits. They are characterized thanks to the EOS test bench which allows identifying their assets as well as their points of improvement

Thesis (Ph. D.)--Missouri University of Science and Technology, 2008.<br>Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed August 21, 2008) Includes bibliographical references.

Electrostatic Discharge (ESD), an event of a sudden transfer of electrons between two bodies at different potentials, happens commonly throughout nature. When such even occurs on integrated circuits (ICs), ICs will be damaged and failures result. As the evolution of semiconductor technologies, increasing usage of automated equipments and the emerging of more and more complex circuit applications, ICs are more sensitive to ESD strikes. Main ESD events occurring in semiconductor industry have been standardized as human body model (HBM), machine model (MM), charged device model (CDM) and international electrotechnical commission model (IEC) for control, monitor and test. In additional to the environmental control of ESD events during manufacturing, shipping and assembly, incorporating on-chip ESD protection circuits inside ICs is another effective solution to reduce the ESD-induced damage. This dissertation presents design, characterization, integration and compact modeling of novel silicon controlled rectifier (SCR)-based devices for on-chip ESD protection. The SCR-based device with a snapback characteristic has long been used to form a VSS-based protection scheme for on-chip ESD protection over a broad rang of technologies because of its low on-resistance, high failure current and the best area efficiency. The ESD design window of the snapback device is defined by the maximum power supply voltage as the low edge and the minimum internal circuitry breakdown voltage as the high edge. The downscaling of semiconductor technology keeps on squeezing the design window of on-chip ESD protection. For the submicron process and below, the turn-on voltage and sustain voltage of ESD protection cell should be lower than 10 V and higher than 5 V, respectively, to avoid core circuit damages and latch-up issue. This presents a big challenge to device/circuit engineers. Meanwhile, the high voltage technologies push the design window to another tough range whose sustain voltage, 45 V for instance, is hard for most snapback ESD devices to reach. Based on the in-depth elaborating on the principle of SCR-based devices, this dissertation first presents a novel unassisted, low trigger- and high holding-voltage SCR (uSCR) which can fit into the aforesaid ESD design window without involving any extra assistant circuitry to realize an area-efficient on-chip ESD protection for low voltage applications. The on-chip integration case is studied to verify the protection effectiveness of the design. Subsequently, this dissertation illustrate the development of a new high holding current SCR (HHC-SCR) device for high voltage ESD protection with increasing the sustain current, not the sustain voltage, of the SCR device to the latchup-immune level to avoid sacrificing the ESD protection robustness of the device. The ESD protection cells have been designed either by using technology computer aided design (TCAD) tools or through trial-and-error iterations, which is cost- or time-consuming or both. Also, the interaction of ESD protection cells and core circuits need to be identified and minimized at pre-silicon stage. It is highly desired to design and evaluate the ESD protection cell using simulation program with integrated circuit emphasis (SPICE)-like circuit simulation by employing compact models in circuit simulators. And the compact model also need to predict the response of ESD protection cells to very fast transient ESD events such as CDM event since it is a major ESD failure mode. The compact model for SCR-based device is not widely available. This dissertation develops a macromodeling approach to build a comprehensive SCR compact model for CDM ESD simulation of complete I/O circuit. This modeling approach offers simplicity, wide availability and compatibility with most commercial simulators by taking advantage of using the advanced BJT model, Vertical Bipolar Inter-Company (VBIC) model. SPICE Gummel-Poon (SGP) model has served the ICs industry well for over 20 years while it is not sufficiently accurate when using SGP model to build a compact model for ESD protection SCR. This dissertation seeks to compare the difference of SCR compact model built by using VBIC and conventional SGP in order to point out the important features of VBIC model for building an accurate and easy-CAD implement SCR model and explain why from device physics and model theory perspectives.<br>Ph.D.<br>School of Electrical Engineering and Computer Science<br>Engineering and Computer Science<br>Electrical Engineering PhD

The presented diploma thesis deals with the design of an electrostatic precipitator for a domestic automatic wood fuel boiler. The individual chapters describe the products of the combustion process, the principles of charging dust particles, describe existing patents related to electrostatic precipitators, commercial electrostatic precipitators and the last part of the work calculates a mathematical model, according to which previously designed and evaluated separator variants were designed and evaluated. Based on the results, the optimal variant of the electrostatic precipitator designed for a domestic boiler is then selected.

La protection contre les décharges électrostatiques (ESD) est un fait necessaire dans chaque circuit intégré. Elle se fait par le déploiement sur la puce d'un réseau de dispositifs spéciaux, à côtés des éléments fonctionnels. La demande pour des améliorations en continu dans la conception et la simulation de l'ESD apporte le besoin de modèles nouveaux et plus précises. La SCR (" Silicon Controlled Rectifier ") est l'un des dispositifs les plus efficaces de protection contre l'ESD. Un nouveau modèle électrique, qui peut être utilisé pour évaluer les structures de protection complexe dont il fait partie, a été développé au cours de cette thèse. Construit avec une forte relation entre les phénomènes physiques et ses équations, il a été parametrisé geometriquement, offrant la possibilité d'adapter et d'optimiser le dispositif selon le niveau de protection nécessaire. Par ailleurs, une étude à haute fréquence sur le SCR et la diode de protection ESD a été réalisé, conduisant à un modèle capable de prédire l'impact de ces dispositifs ont sur le circuit protégé.

La miniaturisation des circuits intégrés se poursuit de nos jours avec le développement de technologies toujours plus fines et denses. Elle permet une intégration des circuits toujours plus massive, avec des performances plus élevées et une réduction des coûts de production. La réduction de taille des circuits s'accompagne aussi d'une augmentation de leur sensibilité électrique. L'électronique automobile est un acteur majeur dans la nouvelle tendance des véhicules autonomes. Ce type d'application a besoin d'analyser des données et d'appliquer des actions sur le véhicule en temps réel. L'objectif à terme est d'améliorer la sécurité des usagers. Il est donc vital de garantir que ces modules électroniques pourront effectuer leurs tâches correctement malgré toutes les perturbations auxquelles ils seront exposés. Néanmoins, l'environnement automobile est particulièrement sévère pour l'électronique. Parmi tous les stress rencontrés, les décharges électrostatiques (ESD - Electrostatic Discharge) sont une importante source d'agression électrique. Ce type d'évènement très bref est suffisamment violent pour détruire des composants électroniques ou les perturber pendant leur fonctionnement. Les recherches présentées ici se concentrent sur l'analyse des défaillances fonctionnelles. À cause des ESD, des fonctions électroniques peuvent cesser temporairement d'être opérantes. Des méthodes d'analyse et de prédiction sont requises au niveau-circuit intégré afin de détecter des points de faiblesses susceptibles de générer des fautes fonctionnelles pendant l'exposition à un stress électrostatique. Différentes approches ont été proposées dans ce but. Une méthode hiérarchique de modélisation a été mise au point afin d'être capable de reproduire la forme d'onde ESD jusqu'à l'entrée du circuit intégré. Avec cette approche, chaque élément du système est modélisé individuellement puis son modèle ajouté au schéma complet. Un cas d'étude réaliste de défaillance fonctionnelle d'un circuit intégré a été analysé à l'aide d'outils de simulation. Afin d'obtenir plus de données sur cette faute, une puce de test a été développée, contenant des structures de surveillance et de mesure directement intégrées dans la puce. La dernière partie de ce travail de recherche est concentrée sur le développement de méthodes d'analyse dans le but d'identifier efficacement des fautes par simulation. Une des techniques développées consiste à modéliser chaque bloc d'une fonction individuellement puis permet de chaîner ces modèles afin de déterminer la robustesse de la fonction complète. La deuxième méthode tente de construire un modèle équivalent dit boite-noire d'une fonction de haut-niveau d'un circuit intégré. Ces travaux de recherche ont mené à la mise au point de prototypes matériels et logiciels et à la mise en évidence de points bloquants qui pourront constituer une base pour de futurs travaux<br>Miniaturization of electronic circuits continues nowadays with the more recent technology nodes being applied to diverse fields of application such as automotive. Very dense and small integrated circuits are interesting for economic reasons, because they are cheaper to manufacture in mass and can pack more functionalities with elevated performances. The counterpart of size reduction is integrated circuits becoming more fragile electrically. In the automotive world, the new trend of fully autonomous driving is seeing tremendous progress recently. Autonomous vehicles must take decisions and perform critical actions such as braking or steering the wheel. Those decisions are taken by electronic modules, that have now very high responsibilities with regards of our safety. It is important to ensure that those modules will operate no matter the kind of disturbances they can be exposed to. The automotive world is a quite harsh environment for electronic systems. A major source of electrical stress is called the Electrostatic Discharge (ESD). It is a very sudden flow of electricity of large amplitude capable of destroying electronic components, or disturb them during their normal operation. This research focuses on functional failures where functionality can be temporarily lost after an ESD with various impact on the vehicle. To guarantee before manufacturing that a module and its components will perform their duty correctly, new analysis and prediction methods are required against soft-failures caused by electrostatic discharges. In this research, different approaches have been explored and proposed towards that goal. First, a modelling method for reproducing the ESD waveforms from the test generator up to the integrated circuit input is presented. It is based on a hierarchical approach where each element of the system is modelled individually, then added to the complete setup model. A practical case of functional failure at silicon-level is analyzed using simulation tools. To acquire more data on this fault, a testchip has been designed. It contains on-chip monitoring structures to measure voltage and current, and monitor function behavior directly at silicon-level. The last part of this research details different analysis methods developed for identifying efficiently functional weaknesses. The methods rely heavily on simulation tools, and prototypes have been implemented to prove the initial concepts. The first method models each function inside the chip individually, using behavioral models, then enables to connect the models together to deduce the full function's robustness. It enables hierarchical analysis of complex integrated circuit designs, to identify potential weak spots inside the circuit that could require more shielding or protection. The second method is focused on constructing equivalent electrical black box models of integrated circuit functions. The goal is to model the IC with a behavioral, black-box model capable of reproducing waveforms in powered conditions during the ESD. In summary, this research work has led to the development of several hardware and software prototypes. It has also highlighted important modelling challenges to solve in future works to achieve better functional robustness against electrostatic discharges

High Electron Mobility Transistors (HEMTs) are finding wide applications in many areas, including microwave power amplifiers, radars, communication and conversion fields. The high mobility, due to the reduction of scattering phenomena, and the high carrier density, due to the confinement of electrons in the so called 2DEG, allowed the achievement of a high current density and low channel resistance, thus making these devices very suitable for high frequency applications. HEMTs are usually based on III-V materials, especially GaAs and GaN technology, as a consequence of their electrical properties. In the last years gallium nitride has become one of the most interesting and suitable material. The high direct energy gap led to better performances especially in optoelectronic devices such as Light emitting diodes, lasers and detectors. Furthermore, the high carrier saturation velocity and the high mobility demonstrated high performances in devices aimed at high frequency, such as HEMTs. Finally the high electric field breakdown and Johnson’s figure of merit suggest its use for devices with high power requirements, thus overcoming in many areas gallium arsenide technology. For many applications, such as MMIC (monolithic microwave integrated circuits) structures, gallium arsenide is preferable, mainly as a consequence of excellent charge transport properties and low loss at microwave and millimetre-wave frequencies. Furthermore, especially for commercial purposes, gallium arsenide is more used due to the well-established technology. Although the significant intrinsic properties, both gallium arsenide and gallium nitride HEMT technology are still affected by reliability issues which limit their performances in common applications. The purpose of this thesis is to study reliability topics which limit HEMT technology on the basis of materials used, namely GaAs, GaN, InAlN, in order to define corresponding limits and performances. With the aim of providing for a more complete perspective the analysis will focus not only on discrete transistors but it will be extended also on complete structures such as power amplifiers. Within this work we present a detailed study of two main degradation mechanisms which still affect GaAs technology and limit its performances both in discrete pHEMTs and in commercial complete structures: thermal degradation and electrostatic discharge failure. Thermal degradation analysis has been firstly studied on discrete structures, namely pseudomorphic HEMTs. A first purpose is to define main failure mechanisms and modes by means of a long term thermal stress with no bias applied. Several analysis (DC, pulsed, end resistances and barrier height evaluation) has been proposed to monitor devices behaviour. Degradation appears to be non-monotonic, i.e. drain current first decreases, then increases again, following the corresponding shifts in the threshold voltage. Although the initial decrease of drain current could be attributed to gate metal interdiffusion, or "gate sinking", leading to a positive shift of threshold voltage, it is accompanied by a variation of the maximum value of transconductance and an increase of end resistances, that suggest a concurrent degradation of ohmic contacts. A third mechanism, represented by the Schottky barrier height, counteracts the effect of gate interdiffusion and eventually prevails, leading to an opposite shift of the threshold voltage. Devices used for high power applications can reach high junction temperatures as a consequence of the power dissipation, demonstrating the importance of accurately defining the thermal resistance, i.e. the channel temperature variation as a function of power dissipated. A second purpose of this chapter is to provide for a detailed description of different techniques (namely DC, pulsed and infrared thermal camera) to estimate channel temperature of HEMTs and to present a critical comparison among them. Differently from DC and pulsed evaluation, analysis with IR thermal camera strongly underestimates the results. With the aim of understanding the impact of inaccuracies on a high frequency application the analysis has been extended to a four stage MMIC power amplifier. The strong underestimation of IR method has been confirmed; furthermore the thermal interaction among different stages and its impact on the structure has been studied. By means of a deep analysis of thermal resistance a HTOL test has been proposed on power amplifiers, submitting the devices both to an electrical and thermal stress and confirming that no significant effect is noticed if a junction temperature lower or equal to 250°C is reached. Comparison between VTH shift in HTOL and thermal stress suggests that the junction temperature has been slightly underestimated. Electrostatic discharge robustness has been studied on a four stage MMIC power amplifier based on GaAs pHEMT technology used in commercial point to point microwave systems. The structure is characterized by a ESD protection circuit mainly defined by Schottky diodes protection structures at the gate terminals and resonant circuit protection structure at the RF input and output pads. Robustness has been analysed with a 100ns TDR-TLP. Results have been confirmed with HBM and MM tests. No failures are observed in the RF-IN, RF-OUT and Drain connections vs. GND up to ±2 kV and ±200 V HBM and MM respectively. RF pads failed with TLP analysis at about 6.5-7A, resulting in an open circuit at the inductor and a short at the capacitor of the resonant structure. Gate connections fail in correspondence of the negative HBM pre-charge value starting from -1.0 kV; MM stresses lead to the failure of the Gate connections from -50 V. Failures are due to the damage of anti-parallel Schottky diodes acting as ESD protection structures. The auxiliary connections reveal to be the most sensitive I/Os of the entire PA, failing at 250 V and 25 V, respectively HBM and MM, due to the failure of integrated resistors. A second part of the thesis mainly focuses on AlGaN/GaN devices. One of the main aspects which limit devices RF and power performances is the so-called current collapse and trapping effects. Therefore a detailed analysis has been proposed on devices characterized by a different iron doping in the buffer layer aimed at preventing parasitic effects and punch through phenomenon. The aim is to define a correlation between the trapping behaviour and iron doping in the buffer layer. A further purpose is to study the correlation between several degradation phenomena when a reliability stress is imposed, both in terms of DC characterization, trapping effects and light emission analysis. A comparison of the correlation between different degradation phenomena in devices with several iron doping quantities is finally proposed. Results are consistent with further investigations reported in literature which correlate the use of iron doping to a trap level with activation energy of 0.57-0.7eV. The analysis firstly demonstrates that iron doping determines a measurable current collapse, which is related to the presence of a trap (T1) located in the buffer with time constant of 3.2ms at T=40°C. Trapping location is consistent with the amplitude significant increase with Fe-concentration in the buffer. Furthermore trap T1 reveals a lower activation energy in devices with no iron doping. The amplitude of trap T1 in devices with different structures and comparison with works reported in literature suggest that the trap is due to an intrinsic defect in the buffer layer characteristic of GaN, although its concentration strongly depends on buffer doping quantity. Results of current transients with different filling pulses applied suggest that trapping is due to line defects or point defects clustering around dislocations. A second trap, T2, is detected. According to comparison of devices with different iron doping and comparison with gm(f) analysis we can suppose that T2, characterized by a time constant of 0.25s at T=40°C, is probably located in the AlGaN layer. Results of an electrical stress applied to the gate terminal of Fe doped devices indicate that the main consequences of the stress experiments are (i) an increase in the leakage gate current, which is strongly correlated to light emission and – beyond the critical voltage – to an increase in the current collapse and (ii) the increase in the transient signal associated with the pre-existing trap levels, without the generation of new traps. Discussion about different results related to the Fe doping buffer layer demonstrates that, when submitted to step-stress, all the devices show a significant and permanent increase in gate leakage current. Furthermore stress induces also an increase in current collapse, which is not correlated to the generation of new trap levels but originates from the increase in the signal associated with the pre-existing trap levels T1 and T2. The change in the signal of T2 (which is supposed to be located in the AlGaN barrier) may be due to an increase in the concentration of a defect (T2); the change of T1, (probably located in the buffer layer) can be explained by the generation of defect-related conductive paths between the gate and the channel which enhance transfer electrons toward the trap states. In the last part new materials to improve GaN technology performances are studied. InAlN/GaN structures are becoming very important as a consequence of the higher carrier density in the 2DEG and the possible achievement of a lattice matched structure, thus significantly improving device electrical and thermal stability. Further improvements, especially at the contacts, will be presented within this thesis. A first analysis consists of the use of a different material for the Schottky gate contact. A comparison of InAlN/GaN HEMTs with analogous structure but different gate, namely Mo/Au and Ni/Pt/Au, is studied. Despite no significant variation is noticed during DC analysis, pulsed evaluation demonstrates that the use of a Mo/Au gate contact leads to an improvement of trapping characteristics, mainly due to the process used for contact deposition. By means of a three terminals step stress it is finally proved that Mo/Au does not significantly affect device stability. A second analysis consists of the definition of a recess before the deposition of ohmic contacts to reduce parasitic resistances. The comparison is proposed for two different wafer, characterized by a similar but not analogous structure and different Carbon doping quantity to avoid parasitic leakage current. DC analysis shows that a significant variation is noticed in IDSS value, showing that a lower value corresponds to structures with recess at the ohmic contacts. This aspect is mainly due to the fact that a lower on resistance measured in linear zone is not obtained. Pulsed analysis states a high current collapse value with no significant correlation with device structure or presence of recess at the ohmic contacts. Drain current transient reveals two main traps, labelled T1 and T2. Activation energy, differently from the cross section value, is not influenced by device structure or by recess at the ohmic contacs. On the basis of drain current transients, gm(f) analysis and previous works reported in literature we can speculate that trap T2 is located in the buffer layer, differently from trap T1 which is probably in the AlGaN layer. Filling time measurements indicate that both the traps are mainly due to line defects.<br>High Electron Mobility Transistors (HEMTs) sono utilizzati in molte applicazioni, tra le quali microwave power amplifiers, radars, applicazioni per telecomunicazioni e potenza. L’alta mobilità, dettata dalla riduzione dei fenomeni di scattering, e l’alta densità di portatori, dettata dal confinamento degli elettroni in una buca quantica triangolare (2DEG), hanno permesso il raggiungimento sia di un’alta densità di corrente, sia di una bassa resistenza di canale, rendendo questi dispositivi particolarmente indicati per applicazioni che richiedono alta frequenza. Gli HEMT sono in genere composti da materiali III-V, nello specifico arseniuro di gallio (GaAs) e in nitruro di gallio (GaN), come conseguenza delle loro proprietà a livello elettrico. Negli ultimi anni il nitruro di gallio è diventato uno tra i materiali più interessanti e utilizzati. L’alto energy gap diretto permette di raggiungere prestazioni molto migliori in particolare nei dispositivi optoelettronici, come Light emitting diodes, lasers and detectors. Inoltre l’alta velocità di saturazione dei portatori e l’alta mobilità hanno condotto ad alte prestazioni anche in dispositivi che lavorano ad alte frequenze, come gli HEMT. Infine, l’alto valore di campo elettrico di breakdown e la Johnson’s figure of merit ne permettono l’utilizzo in dispositivi per applicazioni di potenza, superando dunque in molti ambiti l’arseniuro di gallio. Tuttavia, per molte applicazioni, quali ad esempio strutture MMIC (monolithic microwave integrated circuits), si preferisce ricorrere all’arseniuro di gallio, principalmente per le eccellenti proprietà di trasporto di carica e le perdite minori a frequenze corrispondenti alle microonde. Inoltre, in particolare per scopi commerciali, l’arseniuro di gallio rimane un’ottima soluzione in quanto tecnologia molto stabile in termini di affidabilità. Nonostante le significative proprietà intrinseche, gli HEMT sia in arseniuro di gallio sia in nitruro di gallio sono ancora caratterizzati da numerosi problemi in termini di affidabilità che limitano in modo significativo le loro prestazioni nella maggior parte delle applicazioni. Lo scopo di questa tesi è dunque di studiare alcuni aspetti peculiari che limitano la tecnologia HEMT. Si è voluto proporre un approccio basato sui materiali utilizzati, principalmente GaAs, GaN, InAlN, per poter definire limiti e prestazioni corrispondenti prestando particolare attenzione al materiale considerato. La scelta di voler proporre una prospettiva maggiormente completa ha condotto a non focalizzare l’analisi solo su transistor HEMT discreti ma anche su strutture complete come amplificatori di potenza. In questo lavoro si presenta uno studio dettagliato di due meccanismi di degrado che influenzano ancora la tecnologia in arseniuro di gallio, limitandone le prestazioni sia in dispositivi discreti che in strutture complete commerciali: degrado termico e guasti per scariche elettrostatiche. Il degrado termico è stato innanzitutto studiato su strutture discrete, ovvero su HEMT pseudomorfici. Un primo obiettivo consiste nel definire i principali meccanismi e modi di degrado in seguito ad uno stress termico accelerato senza polarizzazione. Per monitorare il comportamento dei dispositivi numerose analisi sono state proposte, ovvero caratterizzazione DC, impulsata, misura delle end resistances e calcolo dell’altezza di barriera. Durante lo stress il degrado sembra essere non monotono, in quanto la corrente di drain inizialmente cala per poi crescere nuovamente, in modo coerente con gli spostamenti corrispondenti della tensione di soglia. Nonostante la variazione iniziale di corrente si possa attribuire a interdiffusione metallurgica (gate sinking), dimostrata anche da uno shift positivo della tensione di soglia, tale fenomeno è accompagnato anche da un degrado ai contatti ohmici, come dimostrato dalla variazione del picco della transconduttanza e dall’aumento delle corrispondenti resistenze parassite (end resistances). Un terzo meccanismo, descritto dalla diminuzione dell’altezza di barriera del diodo schottky, produce un effetto opposto all’interdiffusione metallurgica, in taluni casi anche prevalendo e comportando uno shift negativo della tensione di soglia. I dispositivi usati per applicazioni che richiedono alta potenza possono raggiungere significative temperature di giunzione come conseguenza della dissipazione in potenza, definendo così l’importanza di una corretta definizione della resistenza termica, i.e. la variazione della temperatura di giunzione in funzione della potenza dissipata. Il secondo obiettivo è dunque quello di fornire una descrizione dettagliata di diverse tecniche (DC, impulsata, infrarossi) per stimare la temperatura di canale in un HEMT e proporre, di conseguenza, un confronto tra di esse esplicitando anche i corrispondenti vantaggi e svantaggi. A differenza dell’analisi con misure DC o impulsate, l’analisi con camera a infrarossi sottostima i risultati. Per riuscire a comprendere l’effetto delle imprecisioni in un’applicazione ad alta frequenza l’analisi è stata estesa ad un amplificatore di potenza sviluppato con struttura MMIC. Si conferma la significativa sottostima del metodo infrarossi. È inoltre possibile definire il fenomeno d’interazione termica tra diversi stadi e la sua influenza nella struttura analizzata. Attraverso un’analisi dettagliata della resistenza termica è stato condotto un test HTOL sugli amplificatori di potenza, sottoponendo questi ultimi sia ad uno stress di tipo elettrico che di tipo termico e confermando il non significativo degrado quando una temperatura di giunzione inferiore a 250°C è imposta. Il confronto della variazione di tensione di soglia nel test HTOL e nel test puramente termico suggerisce che i valori di resistenza termica siano stati leggermente sottostimati. La robustezza verso le scariche elettrostatiche è stata studiata in un amplificatore di potenza con struttura MMIC basato su una tecnologia in HEMT pseudomorfici in arseniuro di gallio, usato a livello commerciale per sistemi microonde point to point. La struttura è caratterizzata da un circuito di protezione ESD principalmente costituito da diodi Schottky in corrispondenza dei terminali di gate e circuiti risonanti agli ingressi RF. La robustezza è stata analizzata con un impulso TDR-TLP di 100ns. I risultati sono stati confermati sia da test HBM che da test MM. Non sono stati riportati guasti nelle connessioni RF e in corrispondenza dei terminali di drain fino ad una tensione di ±2 kV e ±200 V misurata rispettivamente in HBM e MM. I pad RF si rompono in corrispondenza di una corrente misurata con il TLP di 6.5-7A, risultando in un lato aperto in corrispondenza dell’induttore e in un corto circuito in corrispondenza del condensatore, entrambi appartenenti al circuito risonante di protezione. Le connessioni di gate degradano quando una tensione HBM negativa di precarica di -1kV è applicata; risultati coerenti sono riportati dalla misura MM, dimostrando degrado ad una tensione negativa di precarica pari a -75V. Il guasto è riscontrato in corrispondenza dei diodi Schottky posti in anti parallelo come struttura di protezione ESD. Le connessioni ausiliarie per incrementare le prestazioni del dynamic range risultano essere le più sensibili, con una tensione di rottura pari a ±500V e ±50V misurate rispettivamente in HBM e MM, in seguito alla rottura di resistori integrati. La seconda parte della tesi discute i meccanismi di trapping in dispositivi AlGaN/GaN. I fenomeni di trapping, e il conseguente current collapse, risultano essere tra gli aspetti che maggiormente limitano le prestazioni RF e di potenza nei dispositivi HEMT. L’analisi è stata effettuata su dispositivi con un differente drogaggio intenzionale di Ferro nel buffer layer. Tale drogaggio è in genere utilizzato per limitare i fenomeni parassiti e di punch through. Lo scopo primo dell’analisi è definire una correlazione tra i meccanismi di trapping e l’entità di drograggio nel buffer layer. In secondo luogo si è voluto studiare e proporre una correlazione tra differenti fenomeni di degrado nel momento in cui il dispositivo è sottoposto ad uno stress di affidabilità, in termini di caratterizzazione DC, effetti di trapping e analisi di elettroluminescenza. Un confronto di tale correlazione in dispositivi con differente quantità di ferro nel buffer layer è infine proposta. I risultati ottenuti sono coerenti con studi proposti in letteratura, che correlano l’uso di drogaggio in Ferro con una trappola con energia di attivazione pari a 0.57-0.7eV. L’analisi dimostra innanzitutto che il drogaggio in ferro determina un significativo current collapse, correlato con la presenza di una trappola (T1) presumibilmente localizzata nel buffer layer e caratterizzata da una costante di tempo pari a 3.2ms a T=40°C. La posizione della trappola è coerente con l’aumento dell’ampiezza corrispondente al variare della concentrazione di ferro nel buffer. Inoltre la trappola T1 mostra un’attivazione termica molto inferiore (0.2eV) nei dispositivi senza buffer drogato. L’ampiezza della trappola T1 in dispositivi con diversa struttura e il confronto con lavoro precedentemente esposti in letteratura suggerisce che la trappola sia dovuta ad un difetto intrinseco nel buffer layer tipico del GaN; tuttavia la sua concentrazione varia significativamente con la presenza di ferro. L’analisi dei transienti di corrente al variare del tempo di intrappolamento ci permette di ipotizzare che l’intrappolamento non sia dovuto a difetti puntuali o comunque sia dovuta a difetti puntuali ammassati vicino alle dislocazioni. Una seconda trappola, T2, è evidenziata. L’analisi delle trappola in dispositivi con differente drogaggio e il confronto con analisi gm(f) ci permette di supporre che tale trappola, con una costante di tempo di 0.25s a T=40°C, sia situata nello strato AlGaN. I risultati ottenuti da uno stress elettrico imposto al terminale di gate in dispositivi drogati con ferro ne definiscono gli effetti principali: (i) aumento della corrente di leakage, fortemente correlato con l’aumento di hot spot nell’elettroluminescenza e, superata la tensione critica, con un aumento del current collapse. (ii) aumento del segnale associato a segnali preesistenti senza generazione di nuovi stati trappola. L’analisi, estesa a dispositivi con differente o nullo drogaggio in ferro dimostra che, se sottomessi a uno stress di affidabilità, tutti i dispositivi mostrano una variazione della corrente di leakage. Lo stress comporta inoltre un aumento del current collaspe, non correlato alla generazione di nuovi stati trappola bensì all’aumento del segnale associato alle trappole preesistenti, chiamate T1 e T2. La variazione dell’ampiezza di segnale in T2, che si presume essere nell’AlGaN, può essere connessa ad un aumento della concentrazione del difetto; la variazione di T1, che al contrario si presume essere nel buffer layer, può essere chiarita con la generazione di difetti connessi a cammini parassiti conduttivi tra il gate e il canale, generati a causa dello stress, che favoriscono il trasferimento di elettroni verso gli stati trappola. Nell’ultima sezione si studiano nuovi materiali per migliorare le prestazioni della tecnologia GaN. Le strutture InAlN/GaN stanno diventando importanti grazie all’alta densità di portatori nel 2DEG e alla possibilità di ottenere una struttura lattice matched, migliorandone dunque la stabilità elettrica e termica. In questa tesi nuove strutture, in particolare ai contatti, sono discusse. Una prima analisi consiste nell’uso di un differente materiale per il contatto Schottky. Si propone un confronto tra HEMT InAlN/GaN con struttura identica ma differente gate, nello specifico Mo/Au e Ni/Pt/Au. Nonostante non si noti alcuna variazione significativa nell’analisi DC, la valutazione dei fenomeni di trapping mostra che l’uso di un contatto in Mo/Au mostra un miglioramento significativo nelle caratteristiche di trapping, principalmente dettata dal processo usato per la deposizione dei contatti. L’uso di un contatto in Mo/Au, come dimostrato dai risultati di uno stress in OFF state, non influenza la stabilità del dispositivo. Una seconda analisi presenta una struttura in cui è effettuato un recesso prima della deposizione dei contatti ohmici per ridurre le resistenze parassite. Si propone un confronto tra due wafer, caratterizzati da una struttura simile e diversa quantità di drogaggio in carbonio al loro interno per limitare il fenomeno del punch through. L’analisi DC mostra una significativa variazione nel valore , mostrando che un valore minore di IDSS corrisponde a strutture con recesso ai contatti ohmici. Questo effetto è dovuto al non raggiungimento di una resistenza in zona lineare minore. L’analisi impulsata dimostra un alto valore di current collapse senza correlazione con struttura del dispositivo o presenza di recesso ai contatti ohmici. I transienti di corrente mostrano due trappole principali, T1 e T2. L’energia di attivazione, a differenza della sezione di cattura, non è influenzato dalla struttura del dispositivo o dal recesso ai contatti ohmici. I transienti di corrente, le misure gm(f) e lavori precedentemente proposti in letteratura ci permettono di ipotizzare che la trappola T1 sia situata nel buffer layer, a differenza della trappola T1 che è probabilmente sita nello strato AlGaN. Misure al variare del tempo di trapping confermano che entrambe le trappole non sono definite da difetti puntuali.

碩士<br>逢甲大學<br>通訊工程所<br>100<br>The problem of electrostatic discharge (ESD) has always been there. And today&apos;&apos;s 3C products require frivolous shortness; speed of central processing unit (CPU) becomes faster and faster or more and more power saving, so the ability of ESD protection is weaker than before. Although ESD protection circuits will be added in important components such as integrated circuit (IC) when manufacturers design them, making the components do ESD test can pass standards. Usually single components are all right, but whole assemble together cannot pass ESD test, the combination with the body is very important. This paper discusses about ESD protection design of printed circuit board (PCB) layer under the contact discharge condition of standard IEC 61000-4-2. First, the actual case of mobile phone with capacitive touch screen will be discussed. Discussing about its ESD problems and how to solve them finally, we can know the ESD problems which products may met in this case. At last, to design an experiment, importing concepts of ESD protection into PCB layout, making the IC-PIC12F629 has IEC 61000-4-2 Level 4 this ESD protection level, and discuss the importance effect of ESD ground to ESD protection design.

碩士<br>國立臺北科技大學<br>管理學院EMBA華南專班<br>106<br>This study mainly discusses how to improve the electrostatic discharge caused by the Thin Film Transistor Liquid Crystal Display (TFT-LCD) production equipment, so as to reduce the bad rate of product production by reducing the damage caused by TFT-LCD. The process of panel manufacturing is an automatic operating machine. During the process, the automatic transmission system of contact separation between the glass substrate and the granite platform is coated. When contact and friction are produced, the electrostatic discharge will directly affect the pixels in the panel display area and the abnormal reduction of the products yield. So to date, the ESD prevention is prevented. Care has an effect that can not be ignored. Electrostatic grounding, electrostatic discharge / dissipation, conductive / dissipative contact and ionization are embodied. The methods and measures of electrostatic protection are studied and some ideas are discussed to reduce the occurrence of electrostatic damage through Laser laser technology to produce high quality and high quality products.

碩士<br>元智大學<br>化學工程與材料科學學系<br>99<br>ZnO can be applied as a varistor because its resistivity would vary at different applying voltages. Its outstanding current-voltage non-ohmic characteristics makes it good surge absorbing and electrostatic discharge sustaining ability. These ZnO varistors can be called as surge absorber. Generally speaking, varistor in electric product provides the voltage stabilizing and ESD sustaining and this effect can be applied in communication equipment, semiconductor protecting, electric transiting system, controlling system, and so on. This study investigates the effect of SiO2 doping on ESD sustaining ability via doping SiO2 in commercial composition. First, for commercial composition and SiO2-doped composition, the relation between sintering temperature and ESD sustaining ability is discussed, separately. For SiO2-doped composition, an external calcination is involved to investigate its effect on sintering temperature and ESD sustaining ability. The grain and grain boundary structure in microstructure is observed by FE-SEM; crystal structure and average grain size is analyzed by XRD; and the ESD sustaining ability is measured by ESD meter. The experiment result shows that the ESD sustaining ability for both commercial and SiO2-doped composition are decreasing as sintering temperature increasing. The optimal ESD sustaining ability appears at sintering temperature of 1050℃ for two systems, the commercial composition is △Vb about -27.4 % and SiO2-doped composition is △Vb about -29.7 %. Furthrmore, the ESD sustaining ability can be promoted to △Vb about -9.3 % as an external calcination process is applying to SiO2-doped composition.

碩士<br>長庚大學<br>電子工程研究所<br>95<br>At present, all light emitting diode (LED) related studies focus on the improvement of their luminance efficiency and the total output power of the white light applications. In respect to improving the correspondent luminance efficiency and anti electrostatic discharge (ESD) capability, we propose this research to meet the goals mentioned above for a large area high power LED. This article discusses three aspects of Flip-Chip LED (FCLED); I. Flip chip technology for the LEDs. II. Electricity and luminance characteristics of various sub-mount of FCLEDs. III. The ESD capability of the FCLEDs. Firstly, we deposited multi-metal layers of Ti / Au / Sn and Ti / Au / In, on top of the correspondent sub-mounts as the under ball metalized (UBM) pads. In the meanwhile, we also planted gold balls on the p-pad and n-pad of the LED. We then heated the sub-mounts, and gave it sufficient pressure to achieve the Flip-Chip bonding. Secondly, we measured the electrical and optical properties of these bonded FCLEDs. We wanted to find out whether they could or could not enhance the light output efficiency by the fabricated processes and why. Thirdly, we characterized the ESD capabilities of these FCLEDs with different sub-mounts. Details can be found in the text.

In modern integrated circuits, electrostatic discharge (ESD) is a major problem that influences the reliability of operation, yield and cost of fabrication. ESD discharge events can generate static voltages beyond a few kilo volts. If these voltages are dissipated in the chip, high electric field and high current are generated and will destroy the gate oxide material or melt the metal interconnects. In order to protect the chip from these unexpected ESD events, special protection devices are designed and connect to each pin of the IC for this purpose. With the scaling of nano-metric processing technologies, the ESD design window has become more critical. That leaves little room for designers to maneuver. A good ESD protection device must have superior current sinking ability and also does not affect the normal operation of the IC. The two main categories of ESD devices are snapback and non-snapback ones. Non-snapback designs usually consist of forward biased diode strings with properties, such as low heat and power, high current carrying ability. Snapback devices use MOSFET and silicon controlled rectifier (SCR). They exploit avalanche breakdown to conduct current. In order to investigate the properties of various devices, they need to be modeled in device simulators. That process begins with realizing a technology specific NMOS and PMOS in the device simulators. The MOSFET process parameters are exported to build ESD structures. Then, by inserting ESD devices into different simulation test-benches, such as human-body model or charged-device model, their performance is evaluated through a series of figures of merit, which include peak current, voltage overshoot, capacitance, latch-up immunity and current dissipation time. A successful design can sink a large amount of current within an extremely short duration, while it should demonstrate a low voltage overshoot and capacitance. In this research work, an inter-weaving diode and SCR hybrid device demonstrated its effectiveness against tight ESD test standards is shown.

碩士<br>國立臺北科技大學<br>電子工程系碩士班（碩士在職專班）<br>104<br>The electronic products always cause some damage due to the electrostatic effect. For example, electrostatic discharge is a kind of electrostatic effect and bringing some unstable problems such as system malfunction. Sometimes, electronic products could not sustain the voltage and current which is produced by electrostatic. To ensure the function of electronic products, some factories just asked to be verified over the international verification of IES 61000-4-2. In the past, it uses manpower to test every point in product durability testing. It always casues some problems, including the difference of position.Therefor, the accuracy of testing work is decreased. Therefore, this work proposes the detection way through the robot arm operation. In test process, we preinstall the test points and using automatically control to execute every work to modify the position problems. The experimental results show that the inaccuracy on testing position of proposed method is 0.504cm on average. The proposed method can reduce 50% working time than using manual.

碩士<br>逢甲大學<br>資訊電機工程碩士在職專班<br>94<br>The current electrostatic discharge (ESD) testing workstation, method and its testing standards for the liquid crystal modules (LCM’s) of the human body model (HBM), machine model (MM) and charged device model (CDM) can only applied for static operation without LCM’s practical display. Therefore, the ability again the ESD when the LCM is during operation cannot be determined. This thesis intends to provide a novel dynamic ESD testing workstation for the LCM’s. We will first introduce some fundamental models for the ESD testing, including HBM, MM, CDM, the air discharge model, and the contact discharge model. In addition, a testing circuit, consisting of a microprocessor and its surrounding circuits, is used with the isolated elements to connect and to control the pre-testing liquid crystal display modules. Though the actual testing circuit isn’t directly connected to the pre-testing systemic circuit, the ESD is initiated by using an electrostatic gun on the pre-testing LCM. The applied bias of the electrostatic gun is increased until the pre-testing LCM is found malfunction. Because the testing system is isolated from the LCM, the electrostatic charge can then all discharged through the LCM itself without passing to the instruments to improve its testing accuracy. To precisely simulate the dynamic ESD testing environment, the air level and the contact mode in the testing system have been used to set up a standard to provide the practical testing information for the circuit designers how to improve ESD protection capability to prevent from the ESD damage. The dynamic testing standards derived from this thesis are promisingly to become well recognized testing references in the future. In the end, some specific designs by applying layout or adding external components for the LCM protection from the ESD damage will be discussed to further improve the LCM defects under the ESD testing. We will discuss about the design of TFT protecting from the ESD to set up the design rule for the TFT array layout and the LCM protection from the ESD.

博士<br>國立成功大學<br>微電子工程研究所碩博士班<br>95<br>In this dissertation, the growth and characterization of GaN-based light emitting diodes have been studied by metalorganic chemical vapor phase deposition (MOVPE). Nitride-based light emitting diodes (LEDs) with multiple GaN/SiN nucleation layers were prepared. It was found that we could reduce defect density and thus improve crystal quality of the GaN-based LEDs by using multiple GaN/SiN nucleation layers. Nitride-based light emitting diodes (LEDs) with n--GaN current spreading layers were proposed and fabricated. With a 0.1-�慆-thick n--GaN current spreading layer, it was found that we could increase the output power by 35% without increasing the 20 mA operation voltage of the LEDs. It was also found that the n--GaN current spreading layer could significantly improve electrostatic discharge (ESD) characteristics of nitride-based LEDs. Nitride-based LEDs with MQW active regions grown by different temperature profiles were prepared by MOVPE. Compared with conventional samples, the reduced reverse leakage current and improved ESD characteristics of the LEDs are achievable using both temperature ramping and temperature cycling methods. Nitride-based LED with dual-stage MQW structure is proposed and fabricated. It was found that we could reduce number of pinhole and improve crystal quality by inserting the electron emitter MQW structure. It was also found that we could achieve smaller reverse leakage current and forward operation voltage from the dual-stage MQW LEDs. Furthermore, it was found that ESD characteristics of the dual-stage MQW LED are also better. GaN-based LEDs with p-cap layers grown at various temperatures were fabricated. It was found that there exist a large number of V-shape defects in LEDs with 900oC-grown p-cap layers. These V-shape defects will result in a degraded ESD performance. It was also found that we could significantly improve the ESD characteristics of GaN-based LEDs by raising the p-cap growth temperature to 1040oC.

碩士<br>國立中央大學<br>電機工程研究所碩士在職專班<br>100<br>TFT-LCD ( Thin Film Transistor Liquid Crystal Display ) has generally used in electrical products in our life, monitors in LCD TV, Notebook and cell phone are popular application. For mobile products, thick and higher resolution monitor, saving battery energy are getting more and more important. Therefore, LED ( Light-Emitting-Diode ) backlight become the key product in the future. ESD (Electrostatic Discharge ) caused by triboelectric charging and induction, or contact another charged object, it will make electrical products malfunction or failure, and it can change the electrical characteristics of a semiconductor device, degrading or destroying it, become reliability issue. So besides function, ESD is become more and more important, not only function guarantee, but also reduce reliability issue, saving cost. In panel assembly process, it might suffer ESD damage and product function become abnormal, Through studying on Electrostatic Discharge paths in LED backlight module, we can realize the ESD paths and find out the weak point, and knowing how to improve the system level ESD, finally reduce system function fail or reliability case .

ESD, the discharge of electrostatically generated charges into an IC, is one of the most important reliability problems for ultra-scaled devices. This electrostatic charge can generate voltages of up to tens of kilovolts. These very high voltages can generate very high electric fields and currents across semiconductor devices, which may result in dielectric damage or melting of semiconductors and contacts. It has been reported that up to 70% of IC failures are caused by ESD. Therefore, it’s necessary to design a protection circuit for each pin that discharges the ESD energy to the ground. As the devices are continuously scaling down, while ESD energy remains the same, they become more vulnerable to ESD stress. This higher susceptibility to ESD damage is due to thinner gate oxides and shallower junctions. Furthermore, higher operating frequency of the scaled technologies enforces lower parasitic capacitance of the ESD protection circuits. As a result, increasing the robustness of the ESD protection circuits with minimum additional parasitic capacitance is the main challenge in state of the art CMOS processes. Providing a complete ESD immunity for any circuit involves the design of proper protection circuits for I/O pins in addition to an ESD clamp between power supply pins. In this research both of these aspects are investigated and optimized solutions for them are reported. As Silicon Controlled Rectifier (SCR) has the highest ESD protection level per unit area, ESD protection for I/O pins is provided by optimizing the first breakdown voltage and latch-up immunity of SCR family devices. The triggering voltage of SCR is reduced by a new implementation of gate-substrate triggering technique. Furthermore, a new device based on SCR with internal darlington pair is introduced that can provide ESD protection with very small parasitic capacitance. Besides reducing triggering voltage, latch-up immunity of SCR devices is improved using two novel techniques to increase the holding voltage and the holding current. ESD protection between power rails is provided with transient clamps in which the triggering circuit keeps the clamp “on” during the ESD event. In this research, two new clamps are reported that enhance the triggering circuit of the clamp. The first method uses a CMOS thyristor element to provide enough delay time while the second method uses a flip flop to latch the clamp into “on” state at the ESD event. Moreover, the stability of transient clamps is analyzed and it’s been shown that the two proposed clamps have the highest stability compared to other state of the art ESD clamps. Finally, in order to investigate the impact of ESD protection circuits on high speed applications a current mode logic (CML) driver is designed in 0.13μm CMOS technology. The protection for this driver is provided using both MOS-based and SCR-based protection methods. Measurement results show that, compared to MOS-based protection, SCR-based protection has less impact on the driver performance due to its lower parasitic capacitance.

碩士<br>國立臺灣科技大學<br>電子工程系<br>88<br>As ULSI technology advances, the operation of IC speed, chip size andcircuit density increase. This leads us to believe that future ULSIs willrequire very low-voltage and low-power technology. Meanwhile for a low-voltage IC, the gate oxide thickness is rather thin, its gate oxide breakdown voltage reduces. Therefore it is important to develop a low-voltage trigger electrostatic discharge (ESD) protection circuits. In this thesis we provide an understanding of the basic knowledge and issues related to ESD and propose several novel ESD protection circuits. These circuits were designed by computer-aided IC layout software and fabricated through National Science Council Chip-Implementation-Center, consisted of discrete componets, or simulated by computer-aided IC simulation software. In these designs we use an SCR structure as main circuit element because of its high current conducting ability and low holding voltage. The excellent ESD protection capability of the circuits was also verified by experimental data. In addition, we develop new techniques to tune the trigger voltage without breakdown mechanism. With these circuits, we can effectively control the characteristics of ESD protection device with high ESD robustness to solve the serious ESD stress problem for future generations of ICs.

碩士<br>國立臺灣科技大學<br>電子工程系<br>87<br>In this thesis, comprehensive studies on Electrostatic Discharge protection circuit design and whole-chip ESD protection methodology have been made. Several novel ESD protection devices have been proposed. These circuits were designed by computer-aided IC layout software and fabricated through NSC. ESD protection ability in IC chip degraded due to the thinner gate oxide, shorter channel length, shallower drain/source junction, lightly-doped drain structure, polycide and silicided diffusion. We improve recent published ESD protection devices and propose new whole protection circuits to enhance the ESD robustness in modern IC chip. In these CKT designs, we used an SCR structure as main circuit element because of its high current conducting ability and low holding voltage. The excellent ESD protection capability of the circuits was also verified by experimental data. Besides, we developed novel ESD protection circuit with designable trigger voltage. With these circuits, we can effectively controll the caracteristics of ESD protection device with high ESD robustness to solve the serious ESD stress problem in VLSI/ULSI. 1.1 Introduction 2 ESD phenomena in CMOS VLSI and whole-chip ESD protection circuit design methodology 2.1 Introduction 2.2 Whole-chip ESD protection testing models 2.3 Whole-chip ESD protection 3 Modified-LVTSCR Circuit with CDL theory and LVDTSCR device for ESD protection in CMOS VLSI Technology 3.1 Introduction 3.2 Circuit Configuration 3.3 Device structure 3.4 Circuit Operating Principle 3.5 Experimental Results 3.6 Conclusion 4 Gate-Coupled LVTSCR circuit and DCTSCR device for on-chip CMOS VLSI ESD protection 4.1 Introduction 4.2 Circuit Configuration 4.3 Device structure 4.4 Circuit Operating Principle 4.5 Experimental Results 4.6 Conclusion 5 Conclusion 5.1 Conclusion

碩士<br>國立交通大學<br>電子研究所<br>84<br>Two-dimensional mixed-mode circuit and device simulation taking into account the lattice temperature as well as the photogeneration has extensively been performed to examine the two concerned issues in submicronCMOS: ESD (electrostatic discharge) and alpha particle upset. First, the transient and thermal behaviors of an SCR (Silicon Controlled Rectifier) ESD protection structure has been created in terms of the discharging current waveform, the anode voltage waveform, the paek temperature versus the time, and the power versus the time. These simulated results can provide more clear understanding of the origin causing the failure and have judged the anode-to- cathode spacing as the key factor determining the failure threshold. On the other hand, the effect of the effect of the alpha particle hit on a cylindrical p-n junction, a MOSFET, and a DRAM cell has been extensively simulated under different hit energies and angles, different biases, and different doping concentrations. Also demonstrated are the internal potential distributions showing clearing the funneling effetct. An analytic model has successfully reproduced the simulated current waveformsin a cylindrical p-n junction all at different hit energgies and differentdoping concentrations.

碩士<br>國立交通大學<br>光電系統研究所<br>103<br>High voltage integrated circuits are emerging in a wide variety of application nowadays. LDMOS (Lateral Double-Diffused MOSFET) is usually the driver component in these circuits, thanks to its planar structure. First, we will engage in the characteristics of LDMOS, including the I-V curve discussion, the breakdown mechanism, and some of the key specific parameters related to breakdown voltage. According to the above discussion, we propose some advices to optimize the Safe-Operating-Area (SOA) of LDMOS by minimizing the Kirk effect. It is verified in 0.8 m 40V HV technology. Another part of our study is the investigation of ESD protection designs of LDMOS. The LDMOS devices in HV technologies are known to have poor ESD robustness. In this thesis, the root causes of the high voltage (HV) LDMOS failed at the low voltage electrostatic-discharge (ESD) zap is found. One is caused by the bulk layout and one is caused by the intrinsic characteristic of the device. From the findings, a new structure is proposed to improve the ESD robustness by eliminating the root causes in Chapter 3 and 4. The proposed layout on high-voltage LDMOS has been successfully verified in a 0.25 m 20V BCD process without using additional process modification. Experimental results have shown significantly improved ESD robustness of LDMOS.

碩士<br>亞洲大學<br>資訊工程學系碩士班<br>101<br>In this thesis, we have simulated and analyzed the effect of fingers, device-width and main power supply (Vdd) on gate feedback charge (Qgd) and switching time of LDMOS (Lateral Diffused Metal Oxide Semiconductor) by gate charge test circuit simulation. Gate feedback charge is the charge which is required to fill the gate-drain capacitance. Smaller area will have smaller charge and switching time. It has been seen in our simulation that gate feedback charge (Qgd) and switching time increased with device width, no. of fingers, and main power supply (Vdd). Electrostatic Discharge (ESD) sequential zapping of a Lateral Diffused Metal Oxide Semiconductor (LDMOS) structures with P+ insertion at drain region were investigated to study the enhancement of ESD robustness. ESD sequential zapping test methodology has been used in this work based on standard specification of ESD HBM JEDEC Standard test. Aluminum melting point has become our failure criteria. Furthermore, by using P+ insertion at drain region, it can improve the ESD robustness due to excellent discharge ability to overcome ESD high current flow through the device. Our results show that LDMOS with P+ insertion at drain region, with 300um device-width, and 100ms waiting time can pass until 8 kV ESD zapping voltage, due to the low temperature and high current density.