Relevant bibliographies by topics / Embedded multiprocessor systems

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Academic literature on the topic 'Embedded multiprocessor systems'

Author: Grafiati
Published: 4 June 2021
Last updated: 18 February 2022

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Journal articles on the topic "Embedded multiprocessor systems"

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Wang, Shupeng, Kai Huang, Tianyi Xie, and Xiaolang Yan. "Hybrid Model: An Efficient Symmetric Multiprocessor Reference Model." Journal of Electrical and Computer Engineering 2015 (2015): 1–10. http://dx.doi.org/10.1155/2015/915409.

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Functional verification has become one of the main bottlenecks in the cost-effective design of embedded systems, particularly for symmetric multiprocessors. It is estimated that verification in its entirety accounts for up to 60% of design resources, including duration, computer resources, and total personnel. Simulation-based verification is a long-standing approach used to locate design errors in the symmetric multiprocessor verification. The greatest challenge of simulation-based verification is the creation of the reference model of the symmetric multiprocessor. In this paper, we propose an efficient symmetric multiprocessor reference model, Hybrid Model, written with SystemC. SystemC can provide a high-level simulation environment and is faster than the traditional hardware description languages. Hybrid Model has been implemented in an efficient 32-bit symmetric multiprocessor verification. Experimental results show our proposed model is a fast, accurate, and efficient symmetric multiprocessor reference model and it is able to help designers to locate design errors easily and accurately.
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Mignolet, Jean-Yves, and Roel Wuyts. "Embedded Multiprocessor Systems-on-Chip Programming." IEEE Software 26, no. 3 (May 2009): 34–41. http://dx.doi.org/10.1109/ms.2009.64.

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Wang, Rui, and Zhan Huai Li. "A Multiprocessor RTOS Design of uC/OS." Advanced Materials Research 756-759 (September 2013): 814–19. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.814.

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In many safety-critical missions, more and more Multiprocessor Embedded Systems are used to provide the ability of fault tolerance. Using Operating System can easy software design and make software development more efficient. Because of the limited resource in Embedded Systems, many advanced technologies used in common desktop multiprocessor environment have not been used in Embedded RTOS yet. In this paper, we introduce the technologies of Virtual CPU Pool and Multiprocessor Processor Communication Interface to solve task distributing and communication between deferent CPUs. After using and mending uC/OS, I finally realize and test an Operating System in a kind of SMP multiprocessor hardware module successfully.
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Ancona, M., T. Bottino, A. Clematis, G. Dodero, V. Gianuzzi, L. Pareto, M. Pronzato, and A. Repetti. "LINDA: An allocator for embedded multiprocessor systems." Microprocessing and Microprogramming 24, no. 1-5 (August 1988): 85–92. http://dx.doi.org/10.1016/0165-6074(88)90034-8.

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Wu, Peng, and Minsoo Ryu. "EDZL Scheduling and Schedulability Analysis for Performance Asymmetric Multiprocessors." International Journal of Foundations of Computer Science 27, no. 01 (January 2016): 1–14. http://dx.doi.org/10.1142/s0129054116500015.

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Heterogeneous multiprocessor architectures allow embedded real-time systems to better match computing resources to each application's needs and dynamic workload requirements, thereby providing many opportunities for improved performance with reduced power consumption. Unfortunately, guaranteeing real-time requirements on heterogeneous multiprocessors remains a critical problem due to the lack of appropriate scheduling algorithms and analysis methods. In this paper, we consider EDZL (Earliest Deadline First until Zero-Laxity) for performance asymmetric multiprocessor scheduling. EDZL has been shown to outperform other scheduling policies such as global EDF on identical multiprocessors. We show that EDZL is still effective on performance asymmetric multi-processors, and present an efficient EDZL schedulability test. Experimental results show that EDZL scheduling is able to schedule up to 20% more task sets than global EDF and that our new EDZL schedulability test can accept up to 30% more schedulable task sets than a presently exiting one.
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SUGIHARA, Makoto. "On Synthesizing a Reliable Multiprocessor for Embedded Systems." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E93-A, no. 12 (2010): 2560–69. http://dx.doi.org/10.1587/transfun.e93.a.2560.

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Dorta, Taho, Jaime Jiménez, José Luis Martín, Unai Bidarte, and Armando Astarloa. "Reconfigurable Multiprocessor Systems: A Review." International Journal of Reconfigurable Computing 2010 (2010): 1–10. http://dx.doi.org/10.1155/2010/570279.

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Modern digital systems demand increasing electronic resources, so the multiprocessor platforms are a suitable solution for them. This approach provides better results in terms of area, speed, and power consumption compared to traditional uniprocessor digital systems. Reconfigurable multiprocessor systems are a particular type of embedded system, implemented using reconfigurable hardware. This paper presents a review of this emerging research area. A number of state-of-the-art systems published in this field are presented and classified. Design methods and challenges are also discussed. Advances in FPGA technology are leading to more powerful systems in terms of processing and flexibility. Flexibility is one of the strong points of this kind of system, and multiprocessor systems can even be reconfigured at run time, allowing hardware to be adjusted to the demands of the application.
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Bokhari, Tayyaba, Sajjad Haider Shami, and Farhan Haseeb. "Thermal Analysis of Fair Scheduling in Real-time Embedded Systems." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 1 (May 30, 2018): 48. http://dx.doi.org/10.11591/ijres.v7.i1.pp48-56.

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Over the past few decades, increased demand of highly sophisticated real-time applications with complex functionalities has directly led to exponentially increased power consumption and significantly elevated system temperatures. These elevated temperature and thermal variations present formidable challenges towards system reliability, performance, cooling cost and leakages. This article explores the thermal management strength of two fairness based algorithms, namely Proportional Fair (PFair) and Deadline Partitioning Fair (DP-Fair). In related literature, the introduction of fairness is often considered as a tool to achieve optimality in multiprocessor scheduling algorithms. This work shows that these algorithms bring about better thermal profile when compared with the commonly used Earliest Deadline First (EDF) algorithm in similar conditions both in uniprocessor and multiprocessor environments. A simulation is conducted for periodic task set model. The obtained results are encouraging and show that use of fairness based algorithms reduces the operating temperature, peak temperature, and thermal variations.
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Salcic, Zoran, Dong Hui, Partha S. Roop, and Morteza Biglari-Abhari. "HiDRA—A reactive multiprocessor architecture for heterogeneous embedded systems." Microprocessors and Microsystems 30, no. 2 (March 2006): 72–85. http://dx.doi.org/10.1016/j.micpro.2005.05.001.

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Cho, Hyeonjoong, Binoy Ravindran, and E. Douglas Jensen. "Utility accrual real-time scheduling for multiprocessor embedded systems." Journal of Parallel and Distributed Computing 70, no. 2 (February 2010): 101–10. http://dx.doi.org/10.1016/j.jpdc.2009.10.003.

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Dissertations / Theses on the topic "Embedded multiprocessor systems"

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Al-Hasawi, Waleed Isa. "Multiprocessor design for real-time embedded systems." Thesis, Loughborough University, 1987. https://dspace.lboro.ac.uk/2134/7474.

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Valente, Frederico Miguel Goulão. "Static analysis on embedded heterogeneous multiprocessor systems." Master's thesis, Universidade de Aveiro, 2008. http://hdl.handle.net/10773/2180.

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Gong, Shaojie, and Zhongping Deng. "Benchmarks for Embedded Multi-processors." Thesis, Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-660.

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During the recent years, computer performance has increased dramatically. To measure

the performance of computers, benchmarks are ideal tools. Benchmarks exist in many

areas and point to different applications. For instance, in a normal PC, benchmarks can be

used to test the performance of the whole system which includes the CPU, graphic card,

memory system, etc. For multiprocessor systems, there also exist open source benchmark

programs. In our project, we gathered information about some open benchmark programs

and investigated their applicability for evaluating embedded multiprocessor systems

intended for radar signal processing. During our investigation, parallel cluster systems

and embedded multiprocessor systems were studied. Two benchmark programs, HPL and

NAS Parallel Benchmark were identified as particularly relevant for the application field.

The benchmark testing was done on a parallel cluster system which has an architecture

that is similar to the architecture of embedded multiprocessor systems, used for radar

signal processing.

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Khan, Jehangir. "Embedded multiprocessor architectures for automative driver assistance systems." Valenciennes, 2009. http://ged.univ-valenciennes.fr/nuxeo/site/esupversions/d494f35c-ba4b-4230-bb99-881df0742ab6.

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Automotive crashes are responsible for the highest number of accidental deaths all over the world. Researchers, automotive manufacturers and government authorities around the world are continuously looking for solutions to this problem. Research has shown that half of the accidents can be avoided if a driver is alerted to an impending collision a fraction of a second in advance. A mechanism for warning the driver of an approaching danger is called a Driver Assistance System (DAS). Accident statistics show that a great majority of the vehicle crashes result from front-end collisions. Hence minimizing frontal collisions would significantly decrease road accidents. To predict a front-end collision sufficiently in advance, the obstacle must be detected from a distance. Moreover, for the DAS to be really effective, an imminent collision must be sensed in all circumstances, especially in poor weather where the DAS is needed most. A radar sensor fulfils both the prerequisites of long range obstacle detection and all-weather operation. However, only detecting obstacles can be useful to a certain extent. To establish whether an obstacle is on a collision course with the host vehicle, its trajectory must be foreseen before it comes close to the host vehicle. Determining the trajectory of a moving object requires its dynamic behavior to be monitored over a period of time. In a real traffic scenario more than one obstacle can pose danger to the host vehicle, hence trajectories of multiple objects have to be monitored simultaneously. An apparatus which is capable of performing such functions is called a Multiple Target Tracking (MTT) system. In this thesis we propose a DAS using the principles of Multiple Target Tracking to monitor the dynamics of obstacles hundreds of meters ahead and to avoid a collision of the host vehicle with them. While theoretically such a system offers one of the best answers to the road accident problem, its practical implementation is not a trivial task. It involves complex computations and consequently, needs a long processing time. However, to alert a driver to an approaching danger in real time, the computations must be performed very rapidly. We use multiple processors in our system to share the computation load and thereby reduce the processing time. Multiple processors running in parallel not only speed up the computation but also address the power consumption issues of the embedded systems. We use FPGA (Field Programmable Gate Array) as the implementation platform for our multiprocessor system. FPGAs offer the flexibility needed for the ever evolving embedded systems and they are very cost effective. A multiprocessor system implemented in an FPGA makes its architecture flexible and reconfigurable while the processors can be reprogrammed when needed. Thus FPGA based multiprocessor systems guarantee flexibility in hardware as well as in software therefore they scale very easily. We optimize the system architecture to minimize its hardware size while still meeting the realtime deadlines of the application. Minimized hardware not only leads to reducing energy consumption of the system but also enables us to fit the system in a smaller FPGA which plays an important role in reducing the cost of the system
Les accidents de véhicules automobiles sont responsables du plus grand nombre de décès dans le monde. Les chercheurs, les constructeurs automobiles et les autorités gouvernementales internationales sont continuellement à la recherche de solutions pour résoudre ce problème. La recherche a montré que la moitié des accidents peut être évitée si le conducteur est alerté d'une collision imminente une fraction de seconde à l'avance. Un mécanisme d'alerte d'un danger proche est appelé Driver Assistance Systems (DAS). Les statistiques montrent qu'une grande majorité des accidents de véhicules se passent à la suite d'une collision frontale. Minimiser les collisions frontales devrait donc diminuer considérablement les accidents de la route. Pour prévoir une collision frontale suffisamment à l'avance, l'obstacle doit être détecté à distance. En outre, pour que le système d’aide à la conduite soit réellement efficace, une collision imminente doit être prévue en tenant compte de toutes les circonstances : par exemple plus il fait mauvais, plus ce système est nécessaire. Un capteur radar remplit les conditions préalables de détection d'obstacles à longue portée en tenant compte des conditions météorologiques. Pour déterminer si un obstacle se trouve sur une trajectoire de collision avec le véhicule équipé, sa trajectoire doit être prévue avant qu'il n’arrive près du véhicule concerné. La détermination de la trajectoire d'un objet en mouvement exige que son comportement dynamique soit suivi sur une période de temps. Dans un scénario de trafic réel, plus d'un obstacle peut être considéré comme un danger, c’est pourquoi les trajectoires d'objets multiples doivent être surveillées simultanément. Un appareil capable d'assurer de telles fonctions est appelé un système de suivi d’obstacles multiples (Multiple Target Tracking : MTT). Dans cette thèse nous proposons un système d’aide à la conduite original utilisant les principes du MTT pour suivre la dynamique d’obstacles situés à plus d’une centaine de mètres et pour éviter une collision avec le véhicule équipé. En théorie, un tel système offre une des meilleures réponses au problème des accidents de la route, mais sa mise en œuvre reste difficile à réaliser. Elle implique des calculs complexes et, par conséquent, les besoins de traitement prennent du temps. Cependant, pour aviser le conducteur d'un danger imminent en temps réel, les calculs doivent être effectués très rapidement. Nous avons alors opté pour une solution optimale utilisant des processeurs afin de partager la charge de calcul et de réduire ainsi le temps de traitement. Les processeurs multiples fonctionnant en parallèle permettent non seulement d'accélérer le calcul, mais aussi d’optimiser la consommation d’énergie du système embarqué. Nous utilisons des FPGA (Field Programmable Gate Array) comme plateforme de mise en œuvre de notre système multiprocesseur. Les FPGA offrent la souplesse nécessaire pour les systèmes embarqués en constante évolution et sont très rentables. Un système multiprocesseur réalisé dans un FPGA rend son architecture flexible et reconfigurable et les processeurs peuvent être reprogrammés si nécessaire. Ainsi les systèmes multiprocesseurs à base de FPGA garantissent une souplesse du matériel ainsi que des logiciels, et par conséquent ces systèmes deviennent facilement évolutifs (scalables). Nous optimisons l'architecture du système afin de minimiser la taille du matériel tout en respectant les délais en temps réel de l’application. La minimisation du matériel ne conduit pas seulement à réduire la consommation d'énergie du système, mais nous permet aussi d'adapter le système dans un FPGA plus réduit, ce qui joue un rôle important dans la réduction du coût du système
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Nélis, Vincent. "Energy-aware real-time scheduling in embedded multiprocessor systems." Doctoral thesis, Universite Libre de Bruxelles, 2010. http://hdl.handle.net/2013/ULB-DIPOT:oai:dipot.ulb.ac.be:2013/210058.

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Nowadays, computer systems are everywhere. From simple portable devices such as watches and MP3 players to large stationary installations that control nuclear power plants, computer systems are now present in all aspects of our modern and every-day life. In about only 70 years, they have completely perturbed our way of life and they reached a so high degree of sophistication that they will be soon capable of driving our cars and cleaning our houses without any human intervention. As computer systems gain in responsibilities, it becomes essential that they provide both safety and reliability. Indeed, a failure in systems such as the anti-lock braking system (ABS) in cars could threaten human lives and generate catastrophic and irreversible consequences. Hence, for many years, researchers have addressed these emerging problems of system safety and reliability which come along with this fulgurant evolution.

This thesis provides a general overview of embedded real-time computer systems, i.e. a particular kind of computer system whose number grows daily. We provide the reader with some preliminary knowledge and a good understanding of the concepts that underlie this emerging technology. We focus especially on the theoretical problems related to the real-time issue and briefly summarizes the main solutions, together with their advantages and drawbacks. This brings the reader through all the conceptual layers constituting a computer system, from the software level---the logical part---that specifies both the system behavior and requirements to the hardware level---the physical part---that actually performs the expected treatments and reacts to the environment. In the meanwhile, we introduce the theoretical models that allow researchers for theoretical analyses which ensure that all the system requirements are fulfilled. Finally, we address the energy consumption problem in embedded systems. We describe the various factors of power dissipation in modern technologies and we introduce different solutions to reduce this consumption./Cette thèse se focalise sur un type de systèmes informatiques bien précis appelés “systèmes embarqués temps réel”. Un système est dit “embarqué” lorsqu’il est développé afin de servir un but bien précis. Un téléphone portable est un parfait exemple de système embarqué étant donné que toutes ses fonctionnalités sont rigoureusement définies avant même sa conception. Au contraire, un ordinateur personnel n’est généralement pas considéré comme un système embarqué, les concepteurs ne sachant pas à l’avance à quelles fins il sera utilisé. Une grande partie de ces systèmes embarqués ont des contraintes temporelles très fortes, ce qui les distingue encore plus des ordinateurs grand public. A titre d’exemple, lorsqu’un conducteur de voiture freine brusquement, l’ordinateur de bord déclenche l’application ABS et il est primordial que cette application soit traitée endéans une courte échéance. Autrement dit, cette fonctionnalité ABS doit être traitée prioritairement par rapport aux autres fonctionnalités du véhicule. Ce type de système embarqué est alors dit “temps réel”, dû à ces notions de temps et de priorités entre les applications. La problèmatique posée par les systèmes temps réel est la suivante. Comment déterminer, à tout moment, un ordre d’exécution des différentes fonctionnalités de telle sorte qu’elles soient toutes exécutées entièrement endéans leur échéance ?De plus, avec l’apparition récente des systèmes multiprocesseurs, cette problématique s’est fortement complexifiée, vu que le système doit à présent déterminer quelle fonctionnalité s’exécute à quel moment sur quel processeur afin que toutes les contraintes temporelles soient respectées. Pour finir, ces systèmes embarqués temp réel multiprocesseurs se sont rapidement retrouvés confrontés à un problème de consommation d’énergie. Leur demande en terme de performance (et donc en terme d’énergie) à évolué beaucoup plus rapidement que la capacité des batteries qui les alimentent. Ce problème est actuellement rencontré par de nombreux systèmes, tels que les téléphones portables par exemple. L’objectif de cette thèse est de parcourir les différents composants de tels système embarqués et de proposer des solutions afin de réduire leur consommation d’énergie.
Doctorat en Sciences
info:eu-repo/semantics/nonPublished

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Liang, Yuchen, and Syed Muhammad Zeeshan Iqbal. "OpenMPBench : An Open-Source Benchmark for Multiprocessor Based Embedded Systems." Thesis, Blekinge Tekniska Högskola, Sektionen för datavetenskap och kommunikation, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-4556.

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It is a new and open-source benchmark for multiprocessor based embedded system. It comprises a set of parallel implementations for seven classical algorithms that cover different computing features of general-purpose processor. The performance data including tables and figures is provided for guiding the potential users to evaluate the design of multiprocessor based embedded system. The parallel implementations for seven applications that cover four categories are shown according to the category: Automation and Industry Control * Bitcount * SUSAN * BASICMATH Network * Patricia * Dijkstra Office * Stringsearch Security * SHA Among them, Bitcount and Dijkstra involve more than one parallel application implemented for different functions or using different strategies. Bitcount consists three parallel applications, parallel Bitcnt_1, parallel Bitstring and parallel Bitcnts, that implemented bit counting with different strategy. Three parallel applications implemented for Dijkstra. One is for all-pairs shortest paths problem. Another two are for solving single-source shortest paths problem using single queue strategy and multiple queue strategy respectively. Stringsearch consists of Pratt-Boyer-Moore, Case-sensitive Boyer-Moore-Horspool, Case-Insensitive Boyer-Moore-Horspool, and Boyer-Moore-Horspool (Case-insensitive with accented character translation) implementations. Source code of sequential versions of these applications download from Mibench as well as the standard output based on x86-linux. For OpenMPBench, all parallel applications have been implemented in ANCI C language using POSIX threads. All libraries related to implementations are based on GNU standard library. Development environment is in UBUNTU 9.04 with 2.6.28-generic Linux kernel, GCC 4.2.4 compiler, and Emacs 22.1 editor. On the basis of current hardware condition, a workstation with 8 processors, shipped with UBUNTU 4.2.4, is selected for experiment environment. UBUNTU is a free GNU Linux version that offers all GNU standard library and GCC has been installed by default. In conclusion, we consider this experiment environment is available to simulate the multiprocessor based on embedded systems.
Det är en ny och öppen källkod riktmärke för multiprocessor baserade inbyggda system. Det innehåller en rad parallella implementationer i sju klassiska algoritmer som täcker olika datorer funktioner i allmänt bruk processor. Uppgifter om prestanda inklusive tabeller och siffror ges för att styra potentiella användare att utvärdera utformningen av multiprocessor baserade inbyggda system. De parallella implementeringar för sju ansökningar som omfattar fyra kategorier visas beroende på vilken kategori: Automation och industri Control * Bitcount * SUSAN * BASICMATH Nätverk * Patricia * Dijkstra Office * Stringsearch Säkerhet * SHA Bland dem, Bitcount och Dijkstra omfattar mer än en parallell ansökan genomförs för olika funktioner eller med hjälp av olika strategier. Bitcount består tre parallella program, parallell Bitcnt_1, parallell Bitstring och parallella Bitcnts, som genomförs bit räknar med olika strategi. Tre parallella ansökningar genomförs för Dijkstra. Den ena är för all-par kortaste stigar problem. Ytterligare två är för att lösa enda källa kortaste stigar problemet, använder en kö strategi och flera kö strategi respektive. Stringsearch består av Pratt-Boyer-Moore, skiftlägeskänslig Boyer-Moore-Horspool, skiftlägesokänslig Boyer-Moore-Horspool, och Boyer-Moore-Horspool (små bokstäver med accenttecken översättning) implementationer. Källkod sekventiell versioner av dessa program att hämta från Mibench liksom standard produktion baserad på x86-linux. För OpenMPBench har alla parallella ansökningar har genomförts i ANCI C-språk med POSIX trådar. Alla bibliotek i samband med implementationer är baserat på GNU standard bibliotek. Utvecklingsmiljö i Ubuntu 9.04 med 2.6.28-generic Linuxkärnan, GCC 4.2.4 kompilator och Emacs 22,1 redaktör. På grundval av nuvarande hårdvara skick, en arbetsstation med 8 processorer, som levereras med Ubuntu 4.2.4, har valts för experiment miljön. Ubuntu är ett gratis GNU Linux-version som kan erbjuda alla GNU Standard bibliotek och GCC har installerats som standard. Sammanfattningsvis anser vi att detta experiment miljön är tillgänglig för att simulera multiprocessor baserade på inbyggda system.
Yuchen Liang: phone no: 8641182120823 6-3-1, No. 44, Huabei Road Ganduan, Ganjingzi District, Dalian City, 116023, Liaoning Province, P. R. China Syed Muhammad Zeeshan Iqbal: phone no: 92415510275 Muhallah Gurunanak Pura, Street No: 7, House No:211, Faisalabad, Pakistan
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Shalan, Mohamed A. "Dynamic memory management for embedded real-time multiprocessor system-on-a-chip." Diss., Available online, Georgia Institute of Technology, 2003:, 2003. http://etd.gatech.edu/theses/available/etd-11252003-131621/unrestricted/shalanmohameda200312.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2004.
Vincent Mooney, Committee Chair; John Barry, Committee Member; James Hamblen, Committee Member; Karsten Schwan, Committee Member; Linda Wills, Committee Member. Includes bibliography.
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Erbaş, Çaǧkan. "System-level modeling and design space exploration for multiprocessor embedded system-on-chip architectures." Amsterdam : Amsterdam : Vossiuspers ; Universiteit van Amsterdam [Host], 2006. http://dare.uva.nl/document/38007.

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Rosén, Jakob. "Predictable Real-Time Applications on Multiprocessor Systems-on-Chip." Licentiate thesis, Linköpings universitet, ESLAB - Laboratoriet för inbyggda system, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-70138.

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Being predictable with respect to time is, by definition, a fundamental requirement for any real-time system. Modern multiprocessor systems impose a challenge in this context, due to resource sharing conflicts causing memory transfers to become unpredictable. In this thesis, we present a framework for achieving predictability for real-time applications running on multiprocessor system-on-chip platforms. Using a TDMA bus, worst-case execution time analysis and scheduling are done simultaneously. Since the worst-case execution times are directly dependent on the bus schedule, bus access design is of special importance. Therefore, we provide an efficient algorithm for generating bus schedules, resulting in a minimized worst-case global delay. We also present a new approach considering the average-case execution time in a predictable context. Optimization techniques for improving the average-case execution time of tasks, for which predictability with respect to time is not required, have been investigated for a long time in many different contexts. However, this has traditionally been done without paying attention to the worst-case execution time. For predictable real-time applications, on the other hand, the focus has been solely on worst-case execution time optimization, ignoring how this affects the execution time in the average case. In this thesis, we show that having a good average-case global delay can be important also for real-time applications, for which predictability is required. Furthermore, for real-time applications running on multiprocessor systems-on-chip, we present a technique for optimizing for the average case and the worst case simultaneously, allowing for a good average case execution time while still keeping the worst case as small as possible. The proposed solutions in this thesis have been validated by extensive experiments. The results demonstrate the efficiency and importance of the presented techniques.
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Tucci, Primiano <1986&gt. "Hardware/Software Design of Dynamic Real-Time Schedulers for Embedded Multiprocessor Systems." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2013. http://amsdottorato.unibo.it/5594/.

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The new generation of multicore processors opens new perspectives for the design of embedded systems. Multiprocessing, however, poses new challenges to the scheduling of real-time applications, in which the ever-increasing computational demands are constantly flanked by the need of meeting critical time constraints. Many research works have contributed to this field introducing new advanced scheduling algorithms. However, despite many of these works have solidly demonstrated their effectiveness, the actual support for multiprocessor real-time scheduling offered by current operating systems is still very limited. This dissertation deals with implementative aspects of real-time schedulers in modern embedded multiprocessor systems. The first contribution is represented by an open-source scheduling framework, which is capable of realizing complex multiprocessor scheduling policies, such as G-EDF, on conventional operating systems exploiting only their native scheduler from user-space. A set of experimental evaluations compare the proposed solution to other research projects that pursue the same goals by means of kernel modifications, highlighting comparable scheduling performances. The principles that underpin the operation of the framework, originally designed for symmetric multiprocessors, have been further extended first to asymmetric ones, which are subjected to major restrictions such as the lack of support for task migrations, and later to re-programmable hardware architectures (FPGAs). In the latter case, this work introduces a scheduling accelerator, which offloads most of the scheduling operations to the hardware and exhibits extremely low scheduling jitter. The realization of a portable scheduling framework presented many interesting software challenges. One of these has been represented by timekeeping. In this regard, a further contribution is represented by a novel data structure, called addressable binary heap (ABH). Such ABH, which is conceptually a pointer-based implementation of a binary heap, shows very interesting average and worst-case performances when addressing the problem of tick-less timekeeping of high-resolution timers.
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Books on the topic "Embedded multiprocessor systems"

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Gerd, Ascheid, Leupers Rainer, and SpringerLink (Online service), eds. Multiprocessor Systems on Chip: Design Space Exploration. New York, NY: Springer Science+Business Media, LLC, 2011.

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Popovici, Katalin. Embedded software design and programming of multiprocessor system-on-chip: Simulink and SystemC case studies. New York: Springer, 2010.

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Inc, ebrary, ed. System-level modelling and design space exploration for multiprocessor embedded system-on-chip architectures. Amsterdam: Amsterdam University Press, 2006.

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Sriram, Sundararajan. Embedded multiprocessors: Scheduling and synchronization. 2nd ed. Boca Raton: Taylor & Francis, 2009.

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1968-, Bhattacharyya Shuvra S., ed. Embedded multiprocessors: Scheduling and synchronization. New York: Marcel Dekker, 2000.

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1968-, Bhattacharyya Shuvra S., ed. Embedded multiprocessors: Scheduling and synchronization. Boca Raton: Taylor & Francis, 2009.

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Kornaros, Georgios. Multi-core embedded systems. Boca Raton: Taylor & Francis, 2010.

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Popovici, Katalin, Frédéric Rousseau, Ahmed A. Jerraya, and Marilyn Wolf. Embedded Software Design and Programming of Multiprocessor System-on-Chip. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-5567-8.

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Software development for embedded multi-core systems: A practical guide using embedded Intel architecture. Burlington, MA: Elsevier, 2008.

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Multi-objective design space exploration of multiporcessor SoC architectures: The MULTICUBE approach. New York: Springer, 2011.

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Book chapters on the topic "Embedded multiprocessor systems"

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Kumar, Akash, Henk Corporaal, Bart Mesman, and Yajun Ha. "Multiprocessor System Design and Synthesis." In Embedded Systems, 111–27. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-0083-3_5.

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Kianzad, Vida, and Shuvra S. Bhattacharyya. "Multiprocessor Clustering for Embedded Systems." In Euro-Par 2001 Parallel Processing, 697–701. Berlin, Heidelberg: Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-44681-8_99.

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Bekooij, Marco, Orlando Moreira, Peter Poplavko, Bart Mesman, Milan Pastrnak, and Jef van Meerbergen. "Predictable Embedded Multiprocessor System Design." In Software and Compilers for Embedded Systems, 77–91. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30113-4_7.

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Pham, Dac, Jim Holt, and Sanjay Deshpande. "Embedded Multicore Systems: Design Challenges and Opportunities." In Multiprocessor System-on-Chip, 197–222. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6460-1_9.

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Andrei, Alexandru, Petru Eles, Zebo Peng, Marcus Schmitz, and Bashir M. Al-Hashimi. "Voltage Selection for Time-Constrained Multiprocessor Systems." In Designing Embedded Processors, 259–84. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_12.

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van Santen, Victor M., Hussam Amrouch, Thomas Wild, Jörg Henkel, and Andreas Herkersdorf. "Thermal Management and Communication Virtualization for Reliability Optimization in MPSoCs." In Dependable Embedded Systems, 181–205. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_8.

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AbstractThis chapter covers the interdependencies of temperature and the reliable operation of multiprocessor systems on chip (MPSoC). Starting with the assessment of temperature values for the different cores either through measurement or estimation, it is shown which methods on system level can be applied to balance the thermal stress in the system and thus to come to an evenly distributed probability of errors. Special focus is given to task migration as a system-level means, which is supported by an on-chip interconnect virtualization technique that eases fast and transparent switch-over of communication channels. Overall, it is shown how mechanisms on different levels of the system stack can be combined to cooperate across layers for improving system reliability.
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Lee, Trong-Yen, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, and Rong-Shue Hsiao. "Partitioning Strategy for Embedded Multiprocessor FPGA Systems." In Lecture Notes in Electrical Engineering, 395–408. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-74935-8_28.

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Schoeberl, Martin, Peter Puschner, and Raimund Kirner. "A Single-Path Chip-Multiprocessor System." In Software Technologies for Embedded and Ubiquitous Systems, 47–57. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-10265-3_5.

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Belleudy, Cécile, and Sébastien Bilavarn. "Power Models and Strategies for Multiprocessor Platforms." In Design Technology for Heterogeneous Embedded Systems, 411–35. Dordrecht: Springer Netherlands, 2012. http://dx.doi.org/10.1007/978-94-007-1125-9_19.

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Wu, Qiang, Jinian Bian, and Hongxi Xue. "A Distributed Architecture Model for Heterogeneous Multiprocessor System-on-Chip Design." In Embedded Software and Systems, 150–57. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11535409_21.

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Conference papers on the topic "Embedded multiprocessor systems"

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Xu, Jia. "Efficiently Handling Process Overruns and Underruns on Multiprocessors in Real-Time Embedded Systems." In ASME 2017 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. American Society of Mechanical Engineers, 2017. http://dx.doi.org/10.1115/detc2017-68412.

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In hard real-time and embedded multiprocessor system real-world applications, it is very important to strive to minimize the run-time overhead of the scheduler as much as possible, especially in hard real-time and embedded multiprocessor systems with limited processor and system resources. In this paper, we present a method that reduces the worst-case time complexity of the run-time scheduler for re-computing latest start times and for selecting processes for execution on a multiprocessor at run-time to O(n), where n is the number of processes.
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Popp, Merten, Orlando Moreira, Wim Yedema, and Menno Lindwer. "Automatic HAL generation for embedded multiprocessor systems." In ESWEEK'16: TWELFTH EMBEDDED SYSTEM WEEK. New York, NY, USA: ACM, 2016. http://dx.doi.org/10.1145/2968478.2968493.

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Gyorok, Gyorgy, Marta Seebauer, Tamas Orosz, Margit Mako, and Attila Selmeci. "Multiprocessor application in embedded control system." In 2012 IEEE 10th Jubilee International Symposium on Intelligent Systems and Informatics (SISY). IEEE, 2012. http://dx.doi.org/10.1109/sisy.2012.6339534.

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Thiele, Lothar, Iuliana Bacivarov, Wolfgang Haid, and Kai Huang. "Mapping Applications to Tiled Multiprocessor Embedded Systems." In Seventh International Conference on Application of Concurrency to System Design (ACSD 2007). IEEE, 2007. http://dx.doi.org/10.1109/acsd.2007.53.

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Lee, Trong-Yen, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, and Rong-Shue Hsiao. "Hardware-oriented Partition for Embedded Multiprocessor FPGA Systems." In Second International Conference on Innovative Computing, Informatio and Control (ICICIC 2007). IEEE, 2007. http://dx.doi.org/10.1109/icicic.2007.332.

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Harmanci, Derin, Nuria Pazos, Paolo Ienne, and Yusuf Leblebici. "A Predictable Communication Scheme for Embedded Multiprocessor Systems." In 2006 IFIP International Conference on Very Large Scale Integration. IEEE, 2006. http://dx.doi.org/10.1109/vlsisoc.2006.313225.

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Vidal, Jorgiano, Florent de Lamotte, Guy Gogniat, Jean-Philippe Diguet, and Philippe Soulard. "UML design for dynamically reconfigurable multiprocessor embedded systems." In 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010). IEEE, 2010. http://dx.doi.org/10.1109/date.2010.5456989.

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Patel, Krutartha, Sridevan Parameswaran, and Seng Lin Shee. "Ensuring secure program execution in multiprocessor embedded systems." In the 5th IEEE/ACM international conference. New York, New York, USA: ACM Press, 2007. http://dx.doi.org/10.1145/1289816.1289833.

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Huang, Jia, Jan Olaf Blech, Andreas Raabe, Christian Buckl, and Alois Knoll. "Reliability-Aware Design Optimization for Multiprocessor Embedded Systems." In 2011 14th Euromicro Conference on Digital System Design (DSD). IEEE, 2011. http://dx.doi.org/10.1109/dsd.2011.34.

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Pitter, Christof, and Martin Schoeberl. "Performance evaluation of a java chip-multiprocessor." In 2008 International Symposium on Industrial Embedded Systems (SIES). IEEE, 2008. http://dx.doi.org/10.1109/sies.2008.4577678.

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Reports on the topic "Embedded multiprocessor systems"

1

Kianzad, Vida, and Shuvra S. Bhattacharyya. Multiprocessor Clustering for Embedded System Implementation. Fort Belvoir, VA: Defense Technical Information Center, June 2001. http://dx.doi.org/10.21236/ada475832.

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Khandelia, Mukul, and Shuvra S. Bhattacharyya. Contention-Conscious Transaction Ordering in Embedded Multiprocessors Systems. Fort Belvoir, VA: Defense Technical Information Center, March 2000. http://dx.doi.org/10.21236/ada457629.

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