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Journal articles on the topic 'Embedded multiprocessor systems'

Author: Grafiati

Published: 4 June 2021

Last updated: 18 February 2022

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1

Wang, Shupeng, Kai Huang, Tianyi Xie, and Xiaolang Yan. "Hybrid Model: An Efficient Symmetric Multiprocessor Reference Model." Journal of Electrical and Computer Engineering 2015 (2015): 1–10. http://dx.doi.org/10.1155/2015/915409.

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Functional verification has become one of the main bottlenecks in the cost-effective design of embedded systems, particularly for symmetric multiprocessors. It is estimated that verification in its entirety accounts for up to 60% of design resources, including duration, computer resources, and total personnel. Simulation-based verification is a long-standing approach used to locate design errors in the symmetric multiprocessor verification. The greatest challenge of simulation-based verification is the creation of the reference model of the symmetric multiprocessor. In this paper, we propose an efficient symmetric multiprocessor reference model, Hybrid Model, written with SystemC. SystemC can provide a high-level simulation environment and is faster than the traditional hardware description languages. Hybrid Model has been implemented in an efficient 32-bit symmetric multiprocessor verification. Experimental results show our proposed model is a fast, accurate, and efficient symmetric multiprocessor reference model and it is able to help designers to locate design errors easily and accurately.

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2

Mignolet, Jean-Yves, and Roel Wuyts. "Embedded Multiprocessor Systems-on-Chip Programming." IEEE Software 26, no. 3 (May 2009): 34–41. http://dx.doi.org/10.1109/ms.2009.64.

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3

Wang, Rui, and Zhan Huai Li. "A Multiprocessor RTOS Design of uC/OS." Advanced Materials Research 756-759 (September 2013): 814–19. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.814.

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In many safety-critical missions, more and more Multiprocessor Embedded Systems are used to provide the ability of fault tolerance. Using Operating System can easy software design and make software development more efficient. Because of the limited resource in Embedded Systems, many advanced technologies used in common desktop multiprocessor environment have not been used in Embedded RTOS yet. In this paper, we introduce the technologies of Virtual CPU Pool and Multiprocessor Processor Communication Interface to solve task distributing and communication between deferent CPUs. After using and mending uC/OS, I finally realize and test an Operating System in a kind of SMP multiprocessor hardware module successfully.

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4

Ancona, M., T. Bottino, A. Clematis, G. Dodero, V. Gianuzzi, L. Pareto, M. Pronzato, and A. Repetti. "LINDA: An allocator for embedded multiprocessor systems." Microprocessing and Microprogramming 24, no. 1-5 (August 1988): 85–92. http://dx.doi.org/10.1016/0165-6074(88)90034-8.

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5

Wu, Peng, and Minsoo Ryu. "EDZL Scheduling and Schedulability Analysis for Performance Asymmetric Multiprocessors." International Journal of Foundations of Computer Science 27, no. 01 (January 2016): 1–14. http://dx.doi.org/10.1142/s0129054116500015.

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Heterogeneous multiprocessor architectures allow embedded real-time systems to better match computing resources to each application's needs and dynamic workload requirements, thereby providing many opportunities for improved performance with reduced power consumption. Unfortunately, guaranteeing real-time requirements on heterogeneous multiprocessors remains a critical problem due to the lack of appropriate scheduling algorithms and analysis methods. In this paper, we consider EDZL (Earliest Deadline First until Zero-Laxity) for performance asymmetric multiprocessor scheduling. EDZL has been shown to outperform other scheduling policies such as global EDF on identical multiprocessors. We show that EDZL is still effective on performance asymmetric multi-processors, and present an efficient EDZL schedulability test. Experimental results show that EDZL scheduling is able to schedule up to 20% more task sets than global EDF and that our new EDZL schedulability test can accept up to 30% more schedulable task sets than a presently exiting one.

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6

SUGIHARA, Makoto. "On Synthesizing a Reliable Multiprocessor for Embedded Systems." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E93-A, no. 12 (2010): 2560–69. http://dx.doi.org/10.1587/transfun.e93.a.2560.

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7

Dorta, Taho, Jaime Jiménez, José Luis Martín, Unai Bidarte, and Armando Astarloa. "Reconfigurable Multiprocessor Systems: A Review." International Journal of Reconfigurable Computing 2010 (2010): 1–10. http://dx.doi.org/10.1155/2010/570279.

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Modern digital systems demand increasing electronic resources, so the multiprocessor platforms are a suitable solution for them. This approach provides better results in terms of area, speed, and power consumption compared to traditional uniprocessor digital systems. Reconfigurable multiprocessor systems are a particular type of embedded system, implemented using reconfigurable hardware. This paper presents a review of this emerging research area. A number of state-of-the-art systems published in this field are presented and classified. Design methods and challenges are also discussed. Advances in FPGA technology are leading to more powerful systems in terms of processing and flexibility. Flexibility is one of the strong points of this kind of system, and multiprocessor systems can even be reconfigured at run time, allowing hardware to be adjusted to the demands of the application.

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8

Bokhari, Tayyaba, Sajjad Haider Shami, and Farhan Haseeb. "Thermal Analysis of Fair Scheduling in Real-time Embedded Systems." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 1 (May 30, 2018): 48. http://dx.doi.org/10.11591/ijres.v7.i1.pp48-56.

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Over the past few decades, increased demand of highly sophisticated real-time applications with complex functionalities has directly led to exponentially increased power consumption and significantly elevated system temperatures. These elevated temperature and thermal variations present formidable challenges towards system reliability, performance, cooling cost and leakages. This article explores the thermal management strength of two fairness based algorithms, namely Proportional Fair (PFair) and Deadline Partitioning Fair (DP-Fair). In related literature, the introduction of fairness is often considered as a tool to achieve optimality in multiprocessor scheduling algorithms. This work shows that these algorithms bring about better thermal profile when compared with the commonly used Earliest Deadline First (EDF) algorithm in similar conditions both in uniprocessor and multiprocessor environments. A simulation is conducted for periodic task set model. The obtained results are encouraging and show that use of fairness based algorithms reduces the operating temperature, peak temperature, and thermal variations.

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9

Salcic, Zoran, Dong Hui, Partha S. Roop, and Morteza Biglari-Abhari. "HiDRA—A reactive multiprocessor architecture for heterogeneous embedded systems." Microprocessors and Microsystems 30, no. 2 (March 2006): 72–85. http://dx.doi.org/10.1016/j.micpro.2005.05.001.

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10

Cho, Hyeonjoong, Binoy Ravindran, and E. Douglas Jensen. "Utility accrual real-time scheduling for multiprocessor embedded systems." Journal of Parallel and Distributed Computing 70, no. 2 (February 2010): 101–10. http://dx.doi.org/10.1016/j.jpdc.2009.10.003.

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11

Das, Dipankar, P. P. Chakrabarti, and Rajeev Kumar. "Functional verification of task partitioning for multiprocessor embedded systems." ACM Transactions on Design Automation of Electronic Systems 12, no. 4 (September 2007): 44. http://dx.doi.org/10.1145/1278349.1278357.

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12

Iqbal, Syed Muhammad Zeeshan, Yuchen Liang, and Hakan Grahn. "ParMiBench - An Open-Source Benchmark for Embedded Multiprocessor Systems." IEEE Computer Architecture Letters 9, no. 2 (February 2010): 45–48. http://dx.doi.org/10.1109/l-ca.2010.14.

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13

Pop, Traian, Paul Pop, Petru Eles, and Zebo Peng. "Analysis and Optimisation of Hierarchically Scheduled Multiprocessor Embedded Systems." International Journal of Parallel Programming 36, no. 1 (November 20, 2007): 37–67. http://dx.doi.org/10.1007/s10766-007-0059-9.

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14

Hajduk, Zbigniew, Bartosz Trybus, and Jan Sadolewski. "Architecture of FPGA Embedded Multiprocessor Programmable Controller." IEEE Transactions on Industrial Electronics 62, no. 5 (May 2015): 2952–61. http://dx.doi.org/10.1109/tie.2014.2362888.

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15

Elewi, Abdullah, Mohamed Shalan, Medhat Awadalla, and Elsayed M. Saad. "Energy-efficient task allocation techniques for asymmetric multiprocessor embedded systems." ACM Transactions on Embedded Computing Systems 13, no. 2s (January 2014): 1–27. http://dx.doi.org/10.1145/2544375.2544391.

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16

Yao, Jianguo, Xue Liu, Zonghua Gu, Xiaorui Wang, and Jian Li. "Online adaptive utilization control for real-time embedded multiprocessor systems." Journal of Systems Architecture 56, no. 9 (September 2010): 463–73. http://dx.doi.org/10.1016/j.sysarc.2010.06.002.

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17

Lin, Jian Denny, Albert M. K. Cheng, and Gokhan Gercek. "Partitioning Real-Time Tasks With Replications on Multiprocessor Embedded Systems." IEEE Embedded Systems Letters 8, no. 4 (December 2016): 89–92. http://dx.doi.org/10.1109/les.2016.2620473.

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18

Shatnawi, A., J. Ghanim, and M. N. S. Swamy. "Memory Optimization on Heterogeneous Multiprocessor Embedded Systems for DSP Applications." International Journal of Modelling and Simulation 23, no. 4 (January 2003): 240–50. http://dx.doi.org/10.1080/02286203.2003.11442278.

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19

YangHsin Fan, and TrongYen Lee. "Grey Relational Hardware-Software Partitioning for Embedded Multiprocessor FPGA Systems." INTERNATIONAL JOURNAL ON Advances in Information Sciences and Service Sciences 3, no. 3 (April 30, 2011): 32–39. http://dx.doi.org/10.4156/aiss.vol3.issue3.5.

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20

Cannella, Emanuele, and Todor P. Stefanov. "Energy efficient semi-partitioned scheduling for embedded multiprocessor streaming systems." Design Automation for Embedded Systems 20, no. 3 (June 16, 2016): 239–66. http://dx.doi.org/10.1007/s10617-016-9176-2.

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21

Panda, Preeti Ranjan. "Guest Editor Introduction: Special Issue on Multiprocessor-based Embedded Systems." International Journal of Parallel Programming 36, no. 1 (November 7, 2007): 1–2. http://dx.doi.org/10.1007/s10766-007-0060-3.

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22

Xu, Cheng, and Tao Li. "Chemical Reaction Optimization for Task Mapping in Heterogeneous Embedded Multiprocessor Systems." Advanced Materials Research 712-715 (June 2013): 2604–10. http://dx.doi.org/10.4028/www.scientific.net/amr.712-715.2604.

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With different task mapping and scheduling will lead to different time consumption and energy consumption on heterogeneous multiprocessor systems, using appropriate task mapping and scheduling algorithms can save more energy. In this paper, we propose a new method to solve the task mapping problem. The algorithm consists of two elements: An intelligent approach to assign the execution orders of tasks by task level, and an allocation algorithm based on chemical-reaction-inspired metaheuristic called Chemical Reaction Optimization (CRO) to map processors to tasks. The results show that it can use less time to reduce more energy consumption.

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23

Nair, Piyoosh Purushothaman, Arnab Sarkar, N. M. Harsha, Megha Gandhi, P. P. Chakrabarti, and Sujoy Ghose. "ERfair Scheduler with Processor Suspension for Real-Time Multiprocessor Embedded Systems." ACM Transactions on Design Automation of Electronic Systems 22, no. 1 (December 28, 2016): 1–25. http://dx.doi.org/10.1145/2948979.

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24

Betti, Emiliano, Daniel Pierre Bovet, Marco Cesati, and Roberto Gioiosa. "Hard Real-Time Performances in Multiprocessor-Embedded Systems Using ASMP-Linux." EURASIP Journal on Embedded Systems 2008 (2008): 1–16. http://dx.doi.org/10.1155/2008/582648.

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25

Taheri, Golnaz, Ahmad Khonsari, Reza Entezari-Maleki, and Leonel Sousa. "A hybrid algorithm for task scheduling on heterogeneous multiprocessor embedded systems." Applied Soft Computing 91 (June 2020): 106202. http://dx.doi.org/10.1016/j.asoc.2020.106202.

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26

Wang, Hwang-Cheng, Isaac Woungang, Cheng-Wen Yao, Alagan Anpalagan, and Mohammad S. Obaidat. "Energy-efficient tasks scheduling algorithm for real-time multiprocessor embedded systems." Journal of Supercomputing 62, no. 2 (April 26, 2012): 967–88. http://dx.doi.org/10.1007/s11227-012-0771-0.

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27

Kada, Barkahoum, and Hamoudi Kalla. "An Efficient Fault-Tolerant Scheduling Approach with Energy Minimization for Hard Real-Time Embedded Systems." Cybernetics and Information Technologies 19, no. 4 (November 1, 2019): 45–60. http://dx.doi.org/10.2478/cait-2019-0035.

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Abstract In this paper, we focus on two major problems in hard real-time embedded systems fault tolerance and energy minimization. Fault tolerance is achieved via both checkpointing technique and active replication strategy to tolerate multiple transient faults, whereas energy minimization is achieved by adapting Dynamic Voltage Frequency Scaling (DVFS) technique. First, we introduce an original fault-tolerance approach for hard real-time systems on multiprocessor platforms. Based on this approach, we then propose DVFS_FTS algorithm for energy-efficient fault-tolerant scheduling of precedence-constrained applications. DVFS_FTS is based on a list scheduling heuristics, it satisfies real-time constraints and minimizes energy consumption even in the presence of faults by exploring the multiprocessor architecture. Simulation results reveal that the proposed algorithm can save a significant amount of energy while preserving the required fault-tolerance of the system and outperforms other related approaches in energy savings.

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28

Rutzig, Mateus B., Antonio C. S. Beck, Felipe Madruga, Marco A. Alves, Henrique C. Freitas, Nicolas Maillard, Philippe O. A. Navaux, and Luigi Carro. "Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment." International Journal of Reconfigurable Computing 2011 (2011): 1–13. http://dx.doi.org/10.1155/2011/546962.

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Limits of instruction-level parallelism and higher transistor density sustain the increasing need for multiprocessor systems: they are rapidly taking over both general-purpose and embedded processor domains. Current multiprocessing systems are composed either of many homogeneous and simple cores or of complex superscalar, simultaneous multithread processing elements. As parallel applications are becoming increasingly present in embedded and general-purpose domains and multiprocessing systems must handle a wide range of different application classes, there is no consensus over which are the best hardware solutions to better exploit instruction-level parallelism (TLP) and thread-level parallelism (TLP) together. Therefore, in this work, we have expanded the DIM (dynamic instruction merging) technique to be used in a multiprocessing scenario, proving the need for an adaptable ILP exploitation even in TLP architectures. We have successfully coupled a dynamic reconfigurable system to an SPARC-based multiprocessor and obtained performance gains of up to 40%, even for applications that show a great level of parallelism at thread level.

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29

Göhringer, Diana, Michael Hübner, Etienne Nguepi Zeutebouo, and Jürgen Becker. "Operating System for Runtime Reconfigurable Multiprocessor Systems." International Journal of Reconfigurable Computing 2011 (2011): 1–16. http://dx.doi.org/10.1155/2011/121353.

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Operating systems traditionally handle the task scheduling of one or more application instances on processor-like hardware architectures. RAMPSoC, a novel runtime adaptive multiprocessor System-on-Chip, exploits the dynamic reconfiguration on FPGAs to generate, start and terminate hardware and software tasks. The hardware tasks have to be transferred to the reconfigurable hardware via a configuration access port. The software tasks can be loaded into the local memory of the respective IP core either via the configuration access port or via the on-chip communication infrastructure (e.g. a Network-on-Chip). Recent-series of Xilinx FPGAs, such as Virtex-5, provide two Internal Configuration Access Ports, which cannot be accessed simultaneously. To prevent conflicts, the access to these ports as well as the hardware resource management needs to be controlled, e.g. by a special-purpose operating system running on an embedded processor. For that purpose and to handle the relations between temporally and spatially scheduled operations, the novel approach of an operating system is of high importance. This special purpose operating system, called CAP-OS (Configuration Access Port-Operating System), which will be presented in this paper, supports the clients using the configuration port with the services of priority-based access scheduling, hardware task mapping and resource management.

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30

Wajiansyah, Agusma, and Supriadi Supriadi. "Implementasi Master-slave pada Embedded system menggunakan komunikasi RS485." ELKHA 12, no. 1 (October 10, 2020): 26. http://dx.doi.org/10.26418/elkha.v12i1.39166.

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The use of multiprocessor methods in robotics systems has a significant impact on overall robot performance. The Master-slave method is a model of a multiprocessor system where there are several processors that communicate with each other to carry out the robot's overall function. RS-485 can be used as a communication model in the master-slave method. RS-485 is a development of RS-232 which has the ability to communicate with several nodes. In this research, an experiment will be conducted to implement RS-485 to support the master-slave processor communication. Stages of research began with making system design, which includes the design of embedded hardware systems, the design of data communication protocols on RS-485 networks, software design, followed by implementation and testing. The test is carried out to measure the time response of the device to three data transmission models, namely broadcast, addressing slaves without responding and addressing slaves with responses. The test results carried out on three slaves with a communication speed of 9600 bps. Measured response time on broadcast data transmission is 8ms, and address slave without response is 7ms. Whereas delivery by addressing slaves with responses, shows that the measurement method cannot be applied.

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31

Karami, Masoomeh, Athena Abdi, and Hamid R. Zarandi. "A cross-layer aging-aware task scheduling approach for multiprocessor embedded systems." Microelectronics Reliability 85 (June 2018): 190–97. http://dx.doi.org/10.1016/j.microrel.2018.04.015.

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32

Iguider, Adil, Kaouthar Bousselam, Oussama Elissati, Mouhcine Chami, and Abdeslam En-Nouaary. "GO Game Inspired Algorithm for Hardware Software Partitioning in Multiprocessor Embedded Systems." Computer and Information Science 12, no. 4 (November 22, 2019): 111. http://dx.doi.org/10.5539/cis.v12n4p111.

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The codesign is a robust methodology, used in modern embedded systems with the objective of achieving the functional specifications and meeting the non-functional requirements. The most interesting step in the codesing  is the process of  Hardware/Software Partitioning. The aim is to decide which functionalities of the system should be implemented in hardware ($HW$) or in software ($SW$). In this article, a new heuristic algorithm is proposed to simultaneously optimize the hardware area (cost) and the execution time (performance) of a multiprocessor system. The proposed algorithm is inspired from game theory and especially from the GO game. The system is modeled using the DAG graph (Data Acyclic Graph), and two players (HW player and SW player) play in turn and choose a block (functionality) from the graph (system). The HW player has the goal of optimizing the global HW area while the SW player has the objective of minimizing the global execution time. After the game termination, and based on the 0-1 Knapsack algorithm, a step of refinement is used to meet the constraint on the total hardware area or on the overall execution time if a constraint is pre-defined. Experimental results show that the proposed algorithm gives better solutions compared to the Simulated Annealing algorithm and the Genetic Algorithm.

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33

Janka, R. S., L. M. Wills, and L. B. Baumstark. "Virtual benchmarking and model continuity in prototyping embedded multiprocessor signal processing systems." IEEE Transactions on Software Engineering 28, no. 9 (September 2002): 832–46. http://dx.doi.org/10.1109/tse.2002.1033224.

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34

Masood, Sabeen, Shoab Ahmed Khan, Ali Hassan, and Urooj Fatima. "A Novel Framework for Testing High-Speed Serial Interfaces in Multiprocessor Based Real-Time Embedded System." Applied Sciences 11, no. 16 (August 13, 2021): 7465. http://dx.doi.org/10.3390/app11167465.

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Recent years has seen a tremendous increase in processing requirements of present-day embedded system applications. Embedded systems consist of multiple processing elements (PEs) connected to each other using different types of interfaces. Many complicated tasks are accomplished by embedded systems in varied settings, which may introduce errors during inter-processor communication. Testing such systems is tremendously difficult and challenging from testing non-real time systems. A major part of testing real time embedded systems involves ensuring accuracy and timing in synchronous inter-process communication More specifically, the synchronization and inter-processor communication of real-time applications makes testing a challenging task and due to the demand for higher data rate increases, day-by-day, making testing of such systems even more complex. This paper presents a novel frame work that uses multiple instances of simulators with physical high-speed serial interfaces to emulate any real time embedded system communication. The framework presents a testing technique that detects all faults related to synchronization of high-speed synchronous serial interfaces in a systematic manner. The novelty of our approach is to simulate communication across multiple processors in a simulation environment for detecting and localizing bugs. We verify this framework using a case study consisting of an embedded software defined radio (SDR) system. The test results show the applicability of our approach in fixing bugs that relates to synchronization issues that otherwise are very hard to find and fix in very complicated systems, such as SDR.

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35

Mittal, Shaily, and Nitin. "Memory Map: A Multiprocessor Cache Simulator." Journal of Electrical and Computer Engineering 2012 (2012): 1–12. http://dx.doi.org/10.1155/2012/365091.

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Nowadays, Multiprocessor System-on-Chip (MPSoC) architectures are mainly focused on by manufacturers to provide increased concurrency, instead of increased clock speed, for embedded systems. However, managing concurrency is a tough task. Hence, one major issue is to synchronize concurrent accesses to shared memory. An important characteristic of any system design process is memory configuration and data flow management. Although, it is very important to select a correct memory configuration, it might be equally imperative to choreograph the data flow between various levels of memory in an optimal manner. Memory map is a multiprocessor simulator to choreograph data flow in individual caches of multiple processors and shared memory systems. This simulator allows user to specify cache reconfigurations and number of processors within the application program and evaluates cache miss and hit rate for each configuration phase taking into account reconfiguration costs. The code is open source and in java.

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36

Boutekkouk, Fateh. "Real Time Scheduling Optimization." Journal of Information Technology Research 12, no. 4 (October 2019): 132–52. http://dx.doi.org/10.4018/jitr.2019100107.

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This article deals with real time embedded multiprocessor systems scheduling optimization using conventional and quantum inspired genetic algorithms. Real time scheduling problems are known to be NP-hard. In order to resolve it, researchers have resorted to meta-heuristics instead of exact methods. Genetic algorithms seem to be a good choice to solve complex, non-linear, multi-objective and multi-modal problems. However, conventional genetic algorithms may consume much time to find good solutions. For this reason, to minimize the mean response time and the number of tasks missing their deadlines using quantum inspired genetic algorithms for multiprocessors architectures. Our proposed approach takes advantage of both static and dynamic preemptive scheduling. This article has the developed algorithms on a typical example showing a big improvement in research time of good solutions in quantum genetic algorithms with comparison to conventional ones.

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37

Harkut, Dinesh G. "HW SW Co-design of Adaptive Task Scheduler for Real Time Systems." International Journal of Reconfigurable and Embedded Systems (IJRES) 5, no. 1 (March 1, 2016): 59. http://dx.doi.org/10.11591/ijres.v5.i1.pp59-70.

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In embedded system, a real-time operating system (RTOs) is often used to structure the application code and ensure that the deadlines are met by reacting on events in the environment by executing the functions within precise time. Most embedded systems are bound to real-time constraints with determinism and latency as a critical metrics. Generally RTOs are implemented in software, which in turns increases computational overheads, jitter and memory footprint which can be reduced even if not remove completely by utilizing latest FPGA technology, which enables the implementation of a full featured and flexible hardware based RTOs. Scheduling algorithms play an important role in the design of real-time systems. This paper proposes the novel FIS based adaptive hardware task scheduler for multiprocessor systems that minimizes the processor time for scheduling activity which uses fuzzy logic to model the uncertainty at first stage along with adaptive framework that uses feedback which allows processors share of task running on multiprocessor to be controlled dynamically at runtime. This Fuzzy logic based adaptive hardware scheduler breakthroughs the limit of the number of total task and thus improves efficiency of the entire real-time system. The increased computation overheads resulted from proposed model can be compensated by exploiting the parallelism of the hardware as being migrated to FPGA

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38

Naseer, Oumair. "Online Adaptive Fault Tolerant Based Feedback Control Scheduling Algorithm for Multiprocessor Embedded Systems." International Journal of Embedded Systems and Applications 2, no. 3 (September 30, 2012): 1–9. http://dx.doi.org/10.5121/ijesa.2012.2301.

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39

Obermaisser, Roman, Hermann Kopetz, and Christian Paukovits. "A Cross-Domain Multiprocessor System-on-a-Chip for Embedded Real-Time Systems." IEEE Transactions on Industrial Informatics 6, no. 4 (November 2010): 548–67. http://dx.doi.org/10.1109/tii.2010.2071388.

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40

Capota, Eugenia Ana, Cristina Sorina Stangaciu, Mihai Victor Micea, and Daniel-Ioan Curiac. "Towards Fully Jitterless Applications: Periodic Scheduling in Multiprocessor MCSs Using a Table-Driven Approach." Applied Sciences 10, no. 19 (September 25, 2020): 6702. http://dx.doi.org/10.3390/app10196702.

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In mixed criticality systems (MCSs), the time-triggered scheduling approach focuses on a special case of safety-critical embedded applications which run in a time-triggered environment. Sometimes, for these types of MCSs, perfectly periodical (i.e., jitterless) scheduling for certain critical tasks is needed. In this paper, we propose FENP_MC (Fixed Execution Non-Preemptive Mixed Criticality), a real-time, table-driven, non-preemptive scheduling method specifically adapted to mixed criticality systems which guarantees jitterless execution in a mixed criticality time-triggered environment. We also provide a multiprocessor version, namely, P_FENP_MC (Partitioned Fixed Execution Non-Preemptive Mixed Criticality), using a partitioning heuristic. Feasibility tests are proposed for both uniprocessor and homogenous multiprocessor systems. An analysis of the algorithm performance is presented in terms of success ratio and scheduling jitter by comparing it against a time-triggered and an event-driven method in a non-preemptive context.

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41

Castells-Rufas, David, Eduard Fernandez-Alonso, and Jordi Carrabina. "Performance Analysis Techniques for Multi-Soft-Core and Many-Soft-Core Systems." International Journal of Reconfigurable Computing 2012 (2012): 1–14. http://dx.doi.org/10.1155/2012/736347.

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Multi-soft-core systems are a viable and interesting solution for embedded systems that need a particular tradeoff between performance, flexibility and development speed. As the growing capacity allows it, many-soft-cores are also expected to have relevance to future embedded systems. As a consequence, parallel programming methods and tools will be necessarily embraced as a part of the full system development process. Performance analysis is an important part of the development process for parallel applications. It is usually mandatory when you want to get a desired performance or to verify that the system is meeting some real-time constraints. One of the usual techniques used by the HPC community is the postmortem analysis of application traces. However, this is not easily transported to the embedded systems based on FPGA due to the resource limitations of the platforms. We propose several techniques and some hardware architectural support to be able to generate traces on multiprocessor systems based on FPGAs and use them to optimize the performance of the running applications.

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Miele, Antonio. "A fault-injection methodology for the system-level dependability analysis of multiprocessor embedded systems." Microprocessors and Microsystems 38, no. 6 (August 2014): 567–80. http://dx.doi.org/10.1016/j.micpro.2014.05.008.

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Salehi, Mohammad, and Alireza Ejlali. "A Hardware Platform for Evaluating Low-Energy Multiprocessor Embedded Systems Based on COTS Devices." IEEE Transactions on Industrial Electronics 62, no. 2 (February 2015): 1262–69. http://dx.doi.org/10.1109/tie.2014.2352215.

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Xie, Yuan, and Wei-lun Hung. "Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design." Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 45, no. 3 (December 2006): 177–89. http://dx.doi.org/10.1007/s11265-006-9760-y.

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Ishebabi, Harold, Philipp Mahr, Christophe Bobda, Martin Gebser, and Torsten Schaub. "Answer Set versus Integer Linear Programming for Automatic Synthesis of Multiprocessor Systems from Real-Time Parallel Programs." International Journal of Reconfigurable Computing 2009 (2009): 1–11. http://dx.doi.org/10.1155/2009/863630.

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An automated design approach for multiprocessor systems on FPGAs is presented which customizes architectures for parallel programs by simultaneously solving the problems of task mapping, resource allocation, and scheduling. The latter considers effects of fixed-priority preemptive scheduling in order to guarantee real-time requirements, hence covering a broad spectrum of embedded applications. Being inherently a combinatorial optimization problem, the design space is modeled using linear equations that capture high-level design parameters. A comparison of two methods for solving resulting problem instances is then given. The intent is to study how well recent advances in propositional satisfiability (SAT) and thus Answer Set Programming (ASP) can be exploited to automate the design of flexible multiprocessor systems. Integer Linear Programming (ILP) is taken as a baseline, where architectures for IEEE 802.11g and WCDMA baseband signal processing are synthesized. ASP-based synthesis used a few seconds in the solver, faster by three orders of magnitude compared to ILP-based synthesis, thereby showing a great potential for solving difficult instances of the automated synthesis problem.

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Wajiansyah, Agusma, Hari Purwadi, Asrina Astagani, and Supriadi Supriadi. "Implementation of master-slave method on multiprocessor-based embedded system: case study on mobile robot." International Journal of Engineering & Technology 7, no. 2.2 (March 5, 2018): 53. http://dx.doi.org/10.14419/ijet.v7i2.2.12732.

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In this research the master-slave method implemented on an embedded system using 3 processor applied to the mobile robot, to know the speed of program execution of robot. As a comparison is also used a robot with an embedded system based on single processor. From the experimental results, by applying the slave master method obtained the execution time of 546,5 μs and the number of iteration 1079, while for single processor-based system obtained execution time average 67828 μs and the amount of iteration average 147 times. Where the number of iterations is obtained by running the robot for 10 s. From this experiment, it can be concluded that there is a performance increase of 7.3% when compared to embedded systems based on single processor.

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Lee Kee Goh, B. Veeravalli, and S. Viswanathan. "Design of Fast and Efficient Energy-Aware Gradient-Based Scheduling Algorithms Heterogeneous Embedded Multiprocessor Systems." IEEE Transactions on Parallel and Distributed Systems 20, no. 1 (January 2009): 1–12. http://dx.doi.org/10.1109/tpds.2008.55.

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Boukhechem, Sami, and El-Bay Bourennane. "SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication." International Journal of Reconfigurable Computing 2008 (2008): 1–10. http://dx.doi.org/10.1155/2008/902653.

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Transaction-level modeling (TLM) is a promising technique to deal with the increasing complexity of modern embedded systems. This model allows a system designer to model a complete application, composed of hardware and software parts, at several levels of abstraction. For this purpose, we use systemC, which is proposed as a standardized modeling language. This paper presents a transaction-level modeling cosimulation methodology for modeling, validating, and verifying our embedded open architecture platform. The proposed platform is an open source multiprocessor system-on-chip (MPSoC) platform, integrated under the synthesis tool for adaptive and reconfigurable system-on-chip (STARSoC) environment. It relies on the integration between an open source instruction set simulators (ISSs), OR1Ksim platform, and the systemC simulation environment which contains other components (wishbone bus, memories, , etc.). The aim of this work is to provide designers with the possibility of faster and efficient architecture exploration at a higher level of abstractions, starting from an algorithmic description to implementation details.

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Müller, M., W. Fengler, A. Amthor, and C. Ament. "Model-driven development and multiprocessor implementation of a dynamic control algorithm for nanopositioning and nanomeasuring machines." Proceedings of the Institution of Mechanical Engineers, Part I: Journal of Systems and Control Engineering 223, no. 3 (January 21, 2009): 417–29. http://dx.doi.org/10.1243/09596518jsce673.

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This article presents a computationally intensive adaptive trajectory tracking control algorithm for dynamic control of nanopositioning and nanomeasuring machines. To realize the required high sample rate of the control algorithm, an embedded multiprocessor architecture has been chosen as development target. The model-oriented development approach studied here aims to narrow the gap between the control system design environment MATLAB/Simulink® and the actual distributed implementation on the custom platform by introducing a custom code generation target intending the utilization of automatic code generation facilities.

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Poletti, Francesco, Antonio Poggiali, Davide Bertozzi, Luca Benini, Pol Marchal, Mirko Loghi, and Massimo Poncino. "Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support." IEEE Transactions on Computers 56, no. 5 (May 2007): 606–21. http://dx.doi.org/10.1109/tc.2007.1040.

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