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Relevant bibliographies by topics / Embedded processor

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Academic literature on the topic 'Embedded processor'

Author: Grafiati

Published: 4 June 2021

Last updated: 26 July 2025

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Journal articles on the topic "Embedded processor"

1

DJUKIC, M., M. POPOVIC, N. CETIC, and I. POVAZAN. "Embedded Processor Oriented Compiler Infrastructure." Advances in Electrical and Computer Engineering 14, no. 3 (2014): 123–30. http://dx.doi.org/10.4316/aece.2014.03016.

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Shin, Youngsoo, Kiyoung Choi, and Takayasu Sakurai. "Power-conscious Scheduling for Real-time Embedded Systems Design." VLSI Design 12, no. 2 (2001): 139–50. http://dx.doi.org/10.1155/2001/23925.

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Power efficient design of real-time embedded systems based on programmable processors becomes more important as system functionality is increasingly realized through software. We address a power optimization method for real-time embedded applications on a variable speed processor. The method combines off-line and on-line components. The off-line component determines the lowest possible maximum processor speed while guaranteeing deadlines of all tasks. The on-line component dynamically varies the processor speed or bring a processor into a power-down mode to exploit execution time variations an

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Naik Dessai, Sanket Suresh, and Varuna Eswer. "Embedded Software Testing to Determine BCM5354 Processor Performance." International Journal of Software Engineering and Technologies (IJSET) 1, no. 3 (2016): 121. http://dx.doi.org/10.11591/ijset.v1i3.4577.

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Efficiency of a processor is a critical factor for an embedded system. One of the deciding factors for efficiency is the functioning of the L1 cache and Translation Lookaside Buffer (TLB). Certain processors have the L1 cache and TLB managed by the operating system, MIPS32 is one such processor. The performance of the L1 cache and TLB necessitates a detailed study to understand its management during varied load on the processor. This paper presents an implementation of embedded testing procedure to analyse the performance of the MIPS32 processor L1 cache and TLB management by the operating sys

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Carrizosa‐Corral, Fernando, Alberto Vázquez‐Cervantes, Josué‐Rafael Montes, et al. "FPGA‐SoC implementation of an ICA‐based background subtraction method." International Journal of Circuit Theory and Applications 46, no. 9 (2018): 1703–22. http://dx.doi.org/10.1002/cta.2544.

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SummaryThis paper presents the development and implementation of an independent component analysis (ICA)–based background subtraction method on a field programmable gate array (FPGA) system on a chip (SoC) with embedded processor. The use of the classic form of ICA for this purpose results in a complex implementation with high hardware resource usage for an embedded system. Therefore, an alternative version of FastICA was developed that adapts directly to the parallelism offered by the FPGA. In addition, the incorporation of this version of ICA into the motion‐detection method exploits the arc

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Yoon, Young Hyun, Dong Hyun Hwang, Jun Hyeok Yang, and Seung Eun Lee. "Intellino: Processor for Embedded Artificial Intelligence." Electronics 9, no. 7 (2020): 1169. http://dx.doi.org/10.3390/electronics9071169.

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The development of computation technology and artificial intelligence (AI) field brings about AI to be applied to various system. In addition, the research on hardware-based AI processors leads to the minimization of AI devices. By adapting the AI device to the edge of internet of things (IoT), the system can perform AI operation promptly on the edge and reduce the workload of the system core. As the edge is influenced by the characteristics of the embedded system, implementing hardware which operates with low power in restricted resources on a processor is necessary. In this paper, we propose

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Lozano, Hanni, and Mabo Ito. "Energy Efficient Dual Issue Embedded Processor." EAI Endorsed Transactions on Industrial Networks and Intelligent Systems 3, no. 6 (2016): 150814. http://dx.doi.org/10.4108/eai.1-1-2016.150814.

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Ghosh, Arijit, and Tony Givargis. "Cache optimization for embedded processor cores." ACM Transactions on Design Automation of Electronic Systems 9, no. 4 (2004): 419–40. http://dx.doi.org/10.1145/1027084.1027086.

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Parimala, N., and S. R. N. Reddy. "Processor Selection for Embedded System Design." International Journal of Computers and Applications 30, no. 4 (2008): 348–53. http://dx.doi.org/10.1080/1206212x.2008.11441916.

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Bhonagiri, Raghava. "Embedded Ethernet Interface Using Arm Processor." IOSR Journal of Electronics and Communication Engineering 4, no. 4 (2013): 24–28. http://dx.doi.org/10.9790/2834-0442428.

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Uma, S., and P. Sakthivel. "Hardware Evaluation and Software Framework Construction for Performance Measurement of Embedded Processor." Journal of Computational and Theoretical Nanoscience 15, no. 2 (2018): 586–94. http://dx.doi.org/10.1166/jctn.2018.7126.

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A frame work for analysing the capabilities and area of improvements for working of an embedded processor is constructed, and also a methodology for comparative study of simulation of processor on load and hardware results are explained in this paper. The processor can be modelled as a standalone processor or as a group of processors working together to take parallel program execution mode. The proposed frame work and simulation method uses the processor representation of current embedded processor model which is relevant in product design and devices modelling. This system utilizes the ARM pr

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Dissertations / Theses on the topic "Embedded processor"

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Watcharawitch, Panit. "MulTEP : a Multi-Threaded Embedded Processor." Thesis, University of Cambridge, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.615851.

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Kwong, Joyce Y. S. (Joyce Yui Si). "Low-voltage embedded biomedical processor design." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/61587.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 180-190).<br>Advances in mobile electronics are fueling new possibilities in a variety of applications, one of which is ambulatory medical monitoring with body-worn or implanted sensors. Digital processors on such sensors serve to analyze signals in real-time and extract key features for transmission or storage. To support diverse and evolving applications, the processor should be flexible, and to

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Goman, Anna. "Waveform Generator Implemented in FPGA with an Embedded Processor." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2026.

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<p>Communication and digital signal processing applications of today are often developed as fully integrated systems on one single chip and are implemented as application specific integrated circuits using e.g. VLSI technology. As the systems are getting more and more complex in terms of speed and performance the chip size and the design time tend to increase rapidly. This will result in search for cheaper and less time consuming alternatives. One alternative is field programmable gate arrays, so called FPGAs. The FPGAs are getting faster, cheaper and the number of gates increases all the time

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Tolunay, John. "Parallel gaming related algorithms for an embedded media processor." Thesis, Linköpings universitet, Informationskodning, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-86154.

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A new type of computing architecture called ePUMA is under development by the ePUMA Research Team at the Department of Electrical Engineering at Linköping University in Linköping. This contains several single instruction multiple data (SIMD) cores, which are called SIMD Units, where up to 64 computations can be done in parallel. The goal with the architecture is to create a low-power chip with good performance for embedded applications. One possible application is video games. In this work we have studied a selected set of video game related algorithms, including a Pseudo-Random Number Generat

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Obeidat, Fadi. "Embedded Processor Selection/Performance Estimation using FPGA-based Profiling." VCU Scholars Compass, 2010. http://scholarscompass.vcu.edu/etd/2232.

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In embedded systems, modeling the performance of the candidate processor architectures is very important to enable the designer to estimate the capability of each architecture against the target application. Considering the large number of available embedded processors, the need has increased for building an infrastructure by which it is possible to estimate the performance of a given application on a given processor with a minimum of time and resources. This dissertation presents a framework that employs the softcore MicroBlaze processor as a reference architecture where FPGA-based profiling

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Senni, Sophiane. "Exploration of non-volatile magnetic memory for processor architecture." Thesis, Montpellier, 2015. http://www.theses.fr/2015MONTS264/document.

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De par la réduction continuelle des dimensions du transistor CMOS, concevoir des systèmes sur puce (SoC) à la fois très denses et énergétiquement efficients devient un réel défi. Concernant la densité, réduire la dimension du transistor CMOS est sujet à de fortes contraintes de fabrication tandis que le coût ne cesse d'augmenter. Concernant l'aspect énergétique, une augmentation importante de la puissance dissipée par unité de surface frêne l'évolution en performance. Ceci est essentiellement dû à l'augmentation du courant de fuite dans les transistors CMOS, entraînant une montée de la consomm

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Fahmi, Youssef. "Contribution à l’optimisation de densité de code pour Processeur Embarqué." Thesis, Cergy-Pontoise, 2013. http://www.theses.fr/2013CERG0630.

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Les systèmes embarqués prennent une place de plus en plus grande dans le marché actuelavec des dispositifs basée sur des systèmes on-chip. Ces systèmes embarqués ont descontraintes très fortes concernant leurs coût, taille, consommation, fiabilité et dimensions.Dans ce contexte la densité de code d'un processeur devient un critère important.Dans cette thèse l'idée était de prendre un processeur RISC(l'APS3 de la société Cortus)qui a de bonne performance pour le monde embarqué et d'augmenter sa densité de code.Plusieurs méthodes ont été testé :– compression à base de Huffman.– compression à bas

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Franz, Jonathan D. Duren Russell Walker. "An evaluation of CoWare Inc.'s Processor Designer tool suite for the design of embedded processors." Waco, Tex. : Baylor University, 2008. http://hdl.handle.net/2104/5254.

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Le, Thinh Minh. "Visual communications on a memory-embedded array processor: The Computational*RAM." Thesis, University of Ottawa (Canada), 2002. http://hdl.handle.net/10393/6436.

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In this thesis, image and video processing algorithms, especially the compression algorithms, are first studied in their natural formats to appreciate the needs for real-time operations and hence, parallel computing. The computational intense, memory-bound problems are next approached from two directions: algorithmic and architectural. Algorithmic approach tends to systematically analyze the flow independence and data independence of a program, while architectural approach tends to gain speed-up by resource multiplicity and time sharing. The majority of image and video processing algorithms ar

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Petrov, Peter. "Application specific embedded processor customizations for low power and high performance /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2004. http://wwwlib.umi.com/cr/ucsd/fullcit?p3137218.

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Books on the topic "Embedded processor"

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Deprettere, Ed F., Jürgen Teich, and Stamatis Vassiliadis, eds. Embedded Processor Design Challenges. Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45874-3.

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Corporation, National Semiconductor, ed. Embedded system processor databook. National Semiconductor Corp., 1989.

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Gizopoulos, Dimitris, Antonis Paschalis, and Yervant Zorian. Embedded Processor-Based Self-Test. Springer US, 2004. http://dx.doi.org/10.1007/978-1-4020-2801-4.

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Corporation, Intel. 16-/32-bit embedded processor handbook. Intel Corporation, 1990.

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Uchiyama, Kunio, Fumio Arakawa, Hironori Kasahara, et al. Heterogeneous Multicore Processor Technologies for Embedded Systems. Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0284-8.

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Uchiyama, Kunio. Heterogeneous Multicore Processor Technologies for Embedded Systems. Springer New York, 2012.

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Wieferink, Andreas. Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms. Springer Science+Business Media B.V., 2008.

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Fleury, M. Pipelined processor farms: Structured design for embedded parallel systems. J. Wiley, 2001.

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Chu, Pong P. Embedded SoPC Design with Nios II Processor and VHDL Examples. John Wiley & Sons, Inc., 2011. http://dx.doi.org/10.1002/9781118146538.

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Morar, Petre. Enha nced pre-processor for embedded open structured query language. University of East London, 1992.

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Book chapters on the topic "Embedded processor"

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Murti, KCS. "Embedded Processor Architectures." In Transactions on Computer Systems and Networks. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-3293-8_12.

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Nurmi, Jari. "Embedded Computer Architecture Fundamentals." In Processor Design. Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5530-0_2.

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Säntti, Tero, Joonas Tyystjärvi, and Juha Plosila. "Java Co-Processor for Embedded Systems." In Processor Design. Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5530-0_13.

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Kranitis, Nektarios, Antonis Paschalis, Dimitris Gizopoulos, and George Xenoulis. "Software-Based Self-Testing of Embedded Processors." In Processor Design. Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5530-0_20.

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Gizopoulos, Dimitris, Antonis Paschalis, and Yervant Zorian. "Processor Testing Techniques." In Embedded Processor-Based Self-Test. Springer US, 2004. http://dx.doi.org/10.1007/978-1-4020-2801-4_4.

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Uchiyama, Kunio, Fumio Arakawa, Hironori Kasahara, et al. "Processor Cores." In Heterogeneous Multicore Processor Technologies for Embedded Systems. Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0284-8_3.

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Hua, Shaoxiong, Gang Qu, and Shuvra S. Bhattacharyya. "Energy-Efficient Multi-processor Implementation of Embedded Software." In Embedded Software. Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-45212-6_17.

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Bhattacharya, Bishnupriya, and Shuvra S. Bhattacharyya. "Consistency Analysis of Reconfigurable Dataflow Specifications." In Embedded Processor Design Challenges. Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45874-3_1.

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Knijnenburg, P. M. W., T. Kisuki, and M. F. P. O’Boyle. "Iterative Compilation." In Embedded Processor Design Challenges. Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45874-3_10.

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Pirsch, P., A. Freimann, C. Klar, and J. P. Wittenburg. "Processor Architectures for Multimedia Applications." In Embedded Processor Design Challenges. Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45874-3_11.

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Conference papers on the topic "Embedded processor"

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Ichioka, Tomosuke, Yohei Watanabe, and Yuko Hara. "PreLock: Precision Locking for Protecting Embedded Processor." In 2024 Asian Hardware Oriented Security and Trust Symposium (AsianHOST). IEEE, 2024. https://doi.org/10.1109/asianhost63913.2024.10838478.

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Petrov, P., and A. Orailoglu. "Customizable embedded processor architectures." In Proceedings. Euromicro Symposium on Digital System Design. IEEE, 2003. http://dx.doi.org/10.1109/dsd.2003.1231986.

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HU, Jie, and Gen-bao Zhang. "High-performance embedded processor technology." In 2010 International Conference on Computer Design and Applications (ICCDA 2010). IEEE, 2010. http://dx.doi.org/10.1109/iccda.2010.5541076.

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Tongyao Zhou, Luc Charest, and El Mostapha Aboulhamid. "SCIL processor — a CIL processor for embedded systems." In 2007 IEEE North-East Workshop on Circuits and Systems (NEWCAS 2007). IEEE, 2007. http://dx.doi.org/10.1109/newcas.2007.4488013.

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Osawa, Hisashi, and Yuko Hara-Azumi. "Approximate data reuse-based processor." In ESWEEK'17: THIRTEENTH EMBEDDED SYSTEM WEEK. ACM, 2017. http://dx.doi.org/10.1145/3139315.3139316.

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Gholamipour, Amir Hossein, Elaheh Bozorgzadeh, and Sudarshan Banerjee. "Energy-aware co-processor selection for embedded processors on FPGAs." In 2007 25th International Conference on Computer Design ICCD 2007. IEEE, 2007. http://dx.doi.org/10.1109/iccd.2007.4601895.

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Stanic, Milan, Oscar Palomar, Timothy Hayes, Ivan Ratkovic, Osman Unsal, and Adrian Cristal. "Towards low-power embedded vector processor." In CF'16: Computing Frontiers Conference. ACM, 2016. http://dx.doi.org/10.1145/2903150.2903485.

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Micallef, Eric, Yuanlong Xiao, and Andre DeHon. "HLS-Compatible, Embedded-Processor Stream Links." In 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2021. http://dx.doi.org/10.1109/fccm51124.2021.00033.

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Bauer, Lars, Muhammad Shafique, Dirk Teufel, and Jorg Henkel. "A Self-Adaptive Extensible Embedded Processor." In First International Conference on Self-Adaptive and Self-Organizing Systems (SASO 2007). IEEE, 2007. http://dx.doi.org/10.1109/saso.2007.2.

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Papaux, Geoffrey, Daniel Gachet, and Wolfram Luithardt. "Processor virtualization on embedded linux systems." In 2014 6th European Embedded Design in Education and Research Conference (EDERC). IEEE, 2014. http://dx.doi.org/10.1109/ederc.2014.6924360.

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Reports on the topic "Embedded processor"

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Wilcox, D. R., and P. N. Pham. Unix STREAMS Emulation of an Input/Output Controller (IOC) for an Embedded AN/UYK-44(V) Processor. Defense Technical Information Center, 1993. http://dx.doi.org/10.21236/ada270867.

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Learn, Mark Walter. Mitigation of cache memory using an embedded hard-core PPC440 processor in a Virtex-5 Field Programmable Gate Array. Office of Scientific and Technical Information (OSTI), 2010. http://dx.doi.org/10.2172/984165.

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Lee, Edward A. System-Level Design Methodology for Embedded Signal Processors. Defense Technical Information Center, 1997. http://dx.doi.org/10.21236/ada342899.

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Graham, Paul, and Brent Nelson. Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing. Defense Technical Information Center, 1999. http://dx.doi.org/10.21236/ada451425.

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Wheat, Jr., Robert Mitchell, Dale A. Dalmas, and Gregory E. Dale. A Four Channel Beam Current Monitor Data Acquisition System Using Embedded Processors. Office of Scientific and Technical Information (OSTI), 2015. http://dx.doi.org/10.2172/1209457.

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Shen, Chung-Ching, Shenpei Wu, Lai-Huei Wang, Stephen Won, Kishan Sudusinghe, and Shuvra Bhattacharyya. Dataflow-Based Implementation of Layered Sensing Applications on High-Performance Embedded Processors. Defense Technical Information Center, 2013. http://dx.doi.org/10.21236/ada582499.

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Chou, Pai, Ken Hines, Kurt Partridge, and Gaetano Borriello. Control Generation for Embedded Systems Based on Composition of Modal Processes. Defense Technical Information Center, 1998. http://dx.doi.org/10.21236/ada416531.

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Engel-Enright, Carol, and Nancy J. Miller. Entrepreneurial Apparel Design, Development and Production: An Embedded Socio-Economic Process. Iowa State University. Library, 2019. http://dx.doi.org/10.31274/itaa.8274.

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Marsden, Eric, Noëlle Laneyrie, Cécile Laugier, and Olivier Chanton. The regulator-regulatee relationship embedded in a coregulatory network. Foundation for an industrial safety culture, 2024. http://dx.doi.org/10.57071/368rrn.

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This document concerns the regulatory oversight and governance of high-hazard industrial activities. A complex set of laws, regulations and institutions contribute to the social control of these activities, reinforcing and serving as a complement to the risk prevention mechanisms put in place by operating companies. This document focuses in particular on the relationships between regulated firms, regulatory authorities and third party intermediaries who play a role in safety oversight (certification bodies, auditors, insurers, professional associations, etc.) and the impact of the quality of t

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Lawrence, C. M., D. V. Nelson, J. R. Spingarn, and T. E. Bennett. Measurement of process-induced strains in composite materials using embedded fiber optic sensors. Office of Scientific and Technical Information (OSTI), 1996. http://dx.doi.org/10.2172/226060.

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