Log in

Relevant bibliographies by topics / Embedded processor / Journal articles

To see the other types of publications on this topic, follow the link: Embedded processor.

Journal articles on the topic 'Embedded processor'

Author: Grafiati

Published: 4 June 2021

Last updated: 26 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Embedded processor.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

DJUKIC, M., M. POPOVIC, N. CETIC, and I. POVAZAN. "Embedded Processor Oriented Compiler Infrastructure." Advances in Electrical and Computer Engineering 14, no. 3 (2014): 123–30. http://dx.doi.org/10.4316/aece.2014.03016.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Shin, Youngsoo, Kiyoung Choi, and Takayasu Sakurai. "Power-conscious Scheduling for Real-time Embedded Systems Design." VLSI Design 12, no. 2 (2001): 139–50. http://dx.doi.org/10.1155/2001/23925.

Full text

Abstract:

Power efficient design of real-time embedded systems based on programmable processors becomes more important as system functionality is increasingly realized through software. We address a power optimization method for real-time embedded applications on a variable speed processor. The method combines off-line and on-line components. The off-line component determines the lowest possible maximum processor speed while guaranteeing deadlines of all tasks. The on-line component dynamically varies the processor speed or bring a processor into a power-down mode to exploit execution time variations an

APA, Harvard, Vancouver, ISO, and other styles

3

Naik Dessai, Sanket Suresh, and Varuna Eswer. "Embedded Software Testing to Determine BCM5354 Processor Performance." International Journal of Software Engineering and Technologies (IJSET) 1, no. 3 (2016): 121. http://dx.doi.org/10.11591/ijset.v1i3.4577.

Full text

Abstract:

Efficiency of a processor is a critical factor for an embedded system. One of the deciding factors for efficiency is the functioning of the L1 cache and Translation Lookaside Buffer (TLB). Certain processors have the L1 cache and TLB managed by the operating system, MIPS32 is one such processor. The performance of the L1 cache and TLB necessitates a detailed study to understand its management during varied load on the processor. This paper presents an implementation of embedded testing procedure to analyse the performance of the MIPS32 processor L1 cache and TLB management by the operating sys

APA, Harvard, Vancouver, ISO, and other styles

4

Carrizosa‐Corral, Fernando, Alberto Vázquez‐Cervantes, Josué‐Rafael Montes, et al. "FPGA‐SoC implementation of an ICA‐based background subtraction method." International Journal of Circuit Theory and Applications 46, no. 9 (2018): 1703–22. http://dx.doi.org/10.1002/cta.2544.

Full text

Abstract:

SummaryThis paper presents the development and implementation of an independent component analysis (ICA)–based background subtraction method on a field programmable gate array (FPGA) system on a chip (SoC) with embedded processor. The use of the classic form of ICA for this purpose results in a complex implementation with high hardware resource usage for an embedded system. Therefore, an alternative version of FastICA was developed that adapts directly to the parallelism offered by the FPGA. In addition, the incorporation of this version of ICA into the motion‐detection method exploits the arc

APA, Harvard, Vancouver, ISO, and other styles

5

Yoon, Young Hyun, Dong Hyun Hwang, Jun Hyeok Yang, and Seung Eun Lee. "Intellino: Processor for Embedded Artificial Intelligence." Electronics 9, no. 7 (2020): 1169. http://dx.doi.org/10.3390/electronics9071169.

Full text

Abstract:

The development of computation technology and artificial intelligence (AI) field brings about AI to be applied to various system. In addition, the research on hardware-based AI processors leads to the minimization of AI devices. By adapting the AI device to the edge of internet of things (IoT), the system can perform AI operation promptly on the edge and reduce the workload of the system core. As the edge is influenced by the characteristics of the embedded system, implementing hardware which operates with low power in restricted resources on a processor is necessary. In this paper, we propose

APA, Harvard, Vancouver, ISO, and other styles

6

Lozano, Hanni, and Mabo Ito. "Energy Efficient Dual Issue Embedded Processor." EAI Endorsed Transactions on Industrial Networks and Intelligent Systems 3, no. 6 (2016): 150814. http://dx.doi.org/10.4108/eai.1-1-2016.150814.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Ghosh, Arijit, and Tony Givargis. "Cache optimization for embedded processor cores." ACM Transactions on Design Automation of Electronic Systems 9, no. 4 (2004): 419–40. http://dx.doi.org/10.1145/1027084.1027086.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Parimala, N., and S. R. N. Reddy. "Processor Selection for Embedded System Design." International Journal of Computers and Applications 30, no. 4 (2008): 348–53. http://dx.doi.org/10.1080/1206212x.2008.11441916.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Bhonagiri, Raghava. "Embedded Ethernet Interface Using Arm Processor." IOSR Journal of Electronics and Communication Engineering 4, no. 4 (2013): 24–28. http://dx.doi.org/10.9790/2834-0442428.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Uma, S., and P. Sakthivel. "Hardware Evaluation and Software Framework Construction for Performance Measurement of Embedded Processor." Journal of Computational and Theoretical Nanoscience 15, no. 2 (2018): 586–94. http://dx.doi.org/10.1166/jctn.2018.7126.

Full text

Abstract:

A frame work for analysing the capabilities and area of improvements for working of an embedded processor is constructed, and also a methodology for comparative study of simulation of processor on load and hardware results are explained in this paper. The processor can be modelled as a standalone processor or as a group of processors working together to take parallel program execution mode. The proposed frame work and simulation method uses the processor representation of current embedded processor model which is relevant in product design and devices modelling. This system utilizes the ARM pr

APA, Harvard, Vancouver, ISO, and other styles

11

Wang, Tun, and Yu Tian. "Design of Embedded Ai Engine Based on the Microkernel Operating System." Wireless Communications and Mobile Computing 2022 (April 21, 2022): 1–9. http://dx.doi.org/10.1155/2022/9304019.

Full text

Abstract:

At present, the application of the embedded microkernel operating system in military and civil fields has begun to take shape, but it has not yet formed a unified method and standard. Due to its high performance, low frequency, and high reliability, dual-core embedded processors are getting the attention of many chip manufacturers. Compatibility has been favored by many telecom equipment manufacturers and embedded high-end application integrators, but the dual-core embedded processor needs a new real-time operating system to support it, so that it can give full play to the high performance of

APA, Harvard, Vancouver, ISO, and other styles

12

Eswer, Varuna, and Sanket Suresh Naik Dessai. "Embedded Software Engineering Approach to Implement BCM5354 Processor Performance." International Journal of Software Engineering and Technologies (IJSET) 1, no. 1 (2016): 41. http://dx.doi.org/10.11591/ijset.v1i1.4568.

Full text

Abstract:

Efficiency of a processor is a critical factor for an embedded system. One of the deciding factors for efficiency is the functioning of the L1 cache and Translation Lookaside Buffer (TLB). Certain processors have the L1 cache and TLB managed by the operating system, MIPS32 is one such processor. The performance of the L1 cache and TLB necessitates a detailed study to understand its management during varied load on the processor. This paper presents an implementation to analyse the performance of the MIPS32 processor L1 cache and TLB management by the operating system (OS) using software engine

APA, Harvard, Vancouver, ISO, and other styles

13

Guan, Xiaochun, Jianlin Huang, and Tinglong Tang. "Robot vision application on embedded vision implementation with digital signal processor." International Journal of Advanced Robotic Systems 17, no. 1 (2020): 172988141990043. http://dx.doi.org/10.1177/1729881419900437.

Full text

Abstract:

The great development of robot vision represented by deep learning places urgent demands on embedded vision implementation. This article introduces a hardware framework for implementation of embedded vision based on digital signal processor, which can be widely used in robot vision applications. Firstly, the article discusses implementation of a pretrained typical convolutional neural network on the digital signal processor embedded system for real-time handwritten digit recognition. Then, the article introduces the migration of OpenCV software packages to digital signal processor embedded sys

APA, Harvard, Vancouver, ISO, and other styles

14

Haresh, Pandya, Rangapariya Mahesh, and Rajput Jitendra. "Implement embedded controller using FPGA chip." TELKOMNIKA Telecommunication, Computing, Electronics and Control 8, no. 2 (2019): 130–44. https://doi.org/10.11591/ijres.v8.i2.pp130-144.

Full text

Abstract:

The designer of an FPGA embedded processor system has complete flexibility to select any combination of peripherals and controllers. In fact, the designer can invent new, unique peripherals that can be connected directly to the processor bus. If a designer has a non-standard requirement for a peripheral set, this can be met easily with an FPGA embedded processor system. For example, a designer would not easily find an off-the-shelf processor with ten UARTs. However, in an FPGA, this configuration is very easily accomplished.

APA, Harvard, Vancouver, ISO, and other styles

15

Hasan, Muhammad Z., and Flores Jacob. "Development and Evaluation of a Platform for Comparison of Processor Performance." American Journal of Advanced Research 8, no. 2 (2024): 11–14. https://doi.org/10.5281/zenodo.13862647.

Full text

Abstract:

Embedded microprocessor systems are used every day by millions of people. They are buried inside the products (or the equipment) that it controls such as cars, fridges, ovens, traffic lights, hand-held devices. Embedded processors are expected to grow worldwide. Current embedded processors consume more power than their earlier generations. It is important for embedded systems (especially battery-operated ones) to choose a processor that consumes less power. The focus of this project is to develop a platform to investigate the dynamic power consumption of various processors when it is running.

APA, Harvard, Vancouver, ISO, and other styles

16

Pandya, Haresh, Mahesh Rangapariya, and Jitendra Rajput. "Implement Embedded Controller Using FPGA Chip." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 2 (2019): 130. http://dx.doi.org/10.11591/ijres.v8.i2.pp130-144.

Full text

Abstract:

<p>The designer of an FPGA embedded processor system has complete flexibility to select any combination of peripherals and controllers. In fact, the designer can invent new, unique peripherals that can be connected directly to the processor bus. If a designer has a non-standard requirement for a peripheral set, this can be met easily with an FPGA embedded processor system. For example, a designer would not easily find an off-the-shelf processor with ten UARTs. However, in an FPGA, this configuration is very easily accomplished.</p>

APA, Harvard, Vancouver, ISO, and other styles

17

Misko, Joshua, Shrikant S. Jadhav, and Youngsoo Kim. "Extensible Embedded Processor for Convolutional Neural Networks." Scientific Programming 2021 (April 21, 2021): 1–12. http://dx.doi.org/10.1155/2021/6630552.

Full text

Abstract:

Convolutional neural networks (CNNs) require significant computing power during inference. Smart phones, for example, may not run a facial recognition system or search algorithm smoothly due to the lack of resources and supporting hardware. Methods for reducing memory size and increasing execution speed have been explored, but choosing effective techniques for an application requires extensive knowledge of the network architecture. This paper proposes a general approach to preparing a compressed deep neural network processor for inference with minimal additions to existing microprocessor hardw

APA, Harvard, Vancouver, ISO, and other styles

18

Gauthier, Lovic, and Tohru Ishihara. "Processor Energy Characterization for Compiler-Assisted Software Energy Reduction." Journal of Electrical and Computer Engineering 2012 (2012): 1–16. http://dx.doi.org/10.1155/2012/786943.

Full text

Abstract:

Energy consumption is a fundamental barrier in taking full advantage of today and future semiconductor manufacturing technologies. The paper presents our recent research activities and results on characterizing and reducing the energy consumption in embedded systems. Firstly, a technique for characterizing the energy consumption of embedded processors during an application execution is presented. The technique trains a per-processor linear approximation model for fitting it to the energy consumption of the processor obtained by postlayout simulation. Secondly, based on the energy model mention

APA, Harvard, Vancouver, ISO, and other styles

19

Shreya Mane. "Theoretical Study on Embedded Processor and Networking." international journal of engineering technology and management sciences 7, no. 3 (2023): 861–67. http://dx.doi.org/10.46647/ijetms.2023.v07i03.131.

Full text

Abstract:

Embedded processors are specialized microprocessors designed to perform specific tasks within a larger system or device. They are commonly used in various applications such as consumer electronics, automotive systems, industrial automation, and Internet of Things (IoT) devices. This abstract focuses on the role of embedded processors in networking applications. Networking refers to the interconnection of devices and systems to enable communication and data exchange. Embedded processors play a crucial role in networking by providing the necessary computational power and functionality to handle

APA, Harvard, Vancouver, ISO, and other styles

20

Han, Yong Qi, Li Ma, and Hong Liang Guo. "Design of Monitoring Alarm System Based on GPRS MMS." Advanced Materials Research 1049-1050 (October 2014): 2149–52. http://dx.doi.org/10.4028/www.scientific.net/amr.1049-1050.2149.

Full text

Abstract:

This system based on embedded technology, MMS wireless communication, etc. Various kinds of modern technology, design a kind of based on GPRS MMS remote monitoring alarm system, this system chooses LPC2132 chip as embedded processor, serial ports, camera, GPRS and infrared pyroelectric sensor module and other hardware. Main funtions as follows: when someone illegally broken into specific space abnormal happens, infrared pyroelectric sensor embedded processor immediately trigger caused disruption, the camera automatically shooting scene image, and transferred to the embedded processor module, e

APA, Harvard, Vancouver, ISO, and other styles

21

Wang, Xiang, Zongmin Zhao, Dongdong Xu, et al. "Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded Processor." Electronics 9, no. 7 (2020): 1165. http://dx.doi.org/10.3390/electronics9071165.

Full text

Abstract:

Nowadays, the secure program execution of embedded processor has attracted considerable research attention, since more and more code tampering attacks and transient faults are seriously affecting the security of embedded processors. The program monitoring and fault recovery strategies are not only closely related to the security of embedded devices, but also directly affect the performance of the processor. This paper presents a security monitoring and fault recovery architecture for run-time program execution, which takes regular backup copies of the two-stage checkpoint. In this framework, t

APA, Harvard, Vancouver, ISO, and other styles

22

Sanket, Dessai, Kannan Deepa, and Prasad Yadav Shiva. "Implementation of video surveillance system using embedded Blackfin processor." International Journal of Reconfigurable and Embedded Systems 10, no. 2 (2021): 115–22. https://doi.org/10.11591/ijres.v10.i2.pp115-122.

Full text

Abstract:

The video surveillance is critical system to track the people at the various places and to track and monitor the nuciencess bound to be happened. On the other side several studies have proved and showed the hit and miss nature of human intervention to spot change in a surrounding environment which increasing the designer challenges for the development of video surveillance system with the help of embedded processor. The designer faces a greater challenge to apply the principle of embedded systems and develop the system smart features with low power and cost for the required applications of VSS

APA, Harvard, Vancouver, ISO, and other styles

23

Vásárhelyi, József, Roland Batók, and Dániel Drótos. "Examination of Embedded System Adaptive Configurability." Műszaki Tudományos Közlemények, no. 21 (2024): 97–106. https://doi.org/10.33894/mtk-2024.21.15.

Full text

Abstract:

Field Programmable Gate Arrays or FPGA circuits have been the focus of applied research since their appearance. Following the introduction of these circuits in 1980, their year-by-year development and the expansion of application areas have opened up new areas of research. With the appearance of system-on-chip, SOC (System on Chip) solutions and adaptive processing units, they occupy an important role in industrial applications. The question is: when, why and what hardware is to change dynamically during system operation? Whether it is necessary to expand computing resources by expanding new c

APA, Harvard, Vancouver, ISO, and other styles

24

Hyodo, Kazuhito, Hirokazu Noborisaka, and Takashi Yada. "Development of Mechatronics Teaching Materials for Embedded System Engineer Education." Journal of Robotics and Mechatronics 23, no. 5 (2011): 611–17. http://dx.doi.org/10.20965/jrm.2011.p0611.

Full text

Abstract:

We have developed a learning environment for embedded system design. The learning environment consists of a multi-purpose controller and terminal devices. The controller consists of main processor (arm) and a multi-core microprocessor (Propeller). The main processor provides the software development environment. The Propeller chip has eight 32-bit processors and can perform simultaneous tasks for multiple users. In addition, the Propeller chip provides a reconfigurable peripheral module. This feature is very useful for the development of educational materials. Teachers can develop various educ

APA, Harvard, Vancouver, ISO, and other styles

25

Zhang, Song, Yi Zhang, Lian Fa Bai, and Wen Jiang Li. "Design on Embedded Processor with Configurable Divider." Applied Mechanics and Materials 336-338 (July 2013): 1504–9. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.1504.

Full text

Abstract:

By analyzing Cortex-M3 Instruction Set and AHB Bus protocol, a Cortex-M3 Instruction Set compatible 32-bit RISC embedded microprocessor with built-in an optimized 5+2-stage pipeline was realized in this paper. The performance of the 32-bit RISC processor is optimized by deepening pipeline and optimizing functional modules compared with Cortex-M3. According to division instructions, a configurable hardware divider in different realization ways was realized for different applications. The design of the system architecture was completed using Verilog hardware description language (Verilog HDL) an

APA, Harvard, Vancouver, ISO, and other styles

26

SHIMIZU, Toru, Kazutami ARIMOTO, Osamu NISHII, Sugako OTANI, and Hiroyuki KONDO. "Low Power Platform for Embedded Processor LSIs." IEICE Transactions on Electronics E94-C, no. 4 (2011): 394–400. http://dx.doi.org/10.1587/transele.e94.c.394.

Full text

APA, Harvard, Vancouver, ISO, and other styles

27

Fu, Hui Kai. "An Embedded Optical Vector Matrix Multiplication Processor." Applied Mechanics and Materials 263-266 (December 2012): 1334–37. http://dx.doi.org/10.4028/www.scientific.net/amm.263-266.1334.

Full text

Abstract:

In this paper, an embedded architecture of optical vector matrix multiplier (OVMM) is presented. The embedded architecture is aimed at optimizing the data flow of vector matrix multiplier (VMM) to promote its performance. The performance according to the architecture is analyzed and the simulation shows that Amdahl's law is used to analyze the hybrid opto-electronic system, and the electronic part and its interaction with optical part form the bottleneck of system.

APA, Harvard, Vancouver, ISO, and other styles

28

Cates, R. "Processor architecture considerations for embedded controller applications." IEEE Micro 8, no. 3 (1988): 28–38. http://dx.doi.org/10.1109/40.538.

Full text

APA, Harvard, Vancouver, ISO, and other styles

29

Suzuki, K., T. Arai, K. Nadehara, and I. Kuroda. "V830R/AV: embedded multimedia superscalar RISC processor." IEEE Micro 18, no. 2 (1998): 36–47. http://dx.doi.org/10.1109/40.671401.

Full text

APA, Harvard, Vancouver, ISO, and other styles

30

Martín-del-Brío, Bonifacio, Antonio Bono-Nuez, and Nicolás Medrano-Marqués. "Self-organizing maps for embedded processor selection." Microprocessors and Microsystems 29, no. 7 (2005): 307–15. http://dx.doi.org/10.1016/j.micpro.2004.11.001.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Tükel, Mehmet, Arda Yurdakul, and Berna Örs. "Customizable embedded processor array for multimedia applications." Integration 60 (January 2018): 213–23. http://dx.doi.org/10.1016/j.vlsi.2017.09.009.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

ZANG, C., S. IMAI, S. FRANK, and S. KIMURA. "Issue Mechanism for Embedded Simultaneous Multithreading Processor." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91-A, no. 4 (2008): 1092–100. http://dx.doi.org/10.1093/ietfec/e91-a.4.1092.

Full text

APA, Harvard, Vancouver, ISO, and other styles

33

Park, Gi‐Tae, and Soo‐Won Kim. "Embedded processor optimised for vascular pattern recognition." IET Circuits, Devices & Systems 7, no. 2 (2013): 81–92. http://dx.doi.org/10.1049/iet-cds.2012.0192.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

Hwang, Gwan Beom, Kwon Neung Cho, Chang Yeop Han, Hyun Woo Oh, Young Hyun Yoon, and Seung Eun Lee. "Lossless Decompression Accelerator for Embedded Processor with GUI." Micromachines 12, no. 2 (2021): 145. http://dx.doi.org/10.3390/mi12020145.

Full text

Abstract:

The development of the mobile industry brings about the demand for high-performance embedded systems in order to meet the requirement of user-centered application. Because of the limitation of memory resource, employing compressed data is efficient for an embedded system. However, the workload for data decompression causes an extreme bottleneck to the embedded processor. One of the ways to alleviate the bottleneck is to integrate a hardware accelerator along with the processor, constructing a system-on-chip (SoC) for the embedded system. In this paper, we propose a lossless decompression accel

APA, Harvard, Vancouver, ISO, and other styles

35

Shankar, Kumar Mishra, and Nisha P. Sarwade Dr. "Review of 5 stage Pipelined Architecture of 8 Bit Pico Processor." International Journal of Electronics, Communication & Soft Computing Science and Engineering 3, no. 4 (2014): 8–11. https://doi.org/10.5281/zenodo.32440.

Full text

Abstract:

Proposed paper is the study of unpipelined architecture of a 8 bit Pico Processor (pP) [3][4] and how its overall through put can be increased by implementing pipelining. Pico processor is an 8 bit processor which is similar to 8 bit microprocessors for small embedded applications and it is intended for educational purpose .In the past un pipelined single cycle and multi cycle Pico Processor is implemented [3] .Its speed and overall through put can be increased by implementation of pipeline architecture [1] so that it can be used in small embedded applications like gaming proces

APA, Harvard, Vancouver, ISO, and other styles

36

Dessai, Sanket, Deepa Kannan, and Shiva Prasa Yadav. "Implementation of video surveillance system using embedded Blackfin processor." International Journal of Reconfigurable and Embedded Systems (IJRES) 10, no. 2 (2021): 115. http://dx.doi.org/10.11591/ijres.v10.i2.pp115-122.

Full text

Abstract:

<p class="NormalLinespacing15lines">The video surveillance is critical system to track the people at the various places and to track and monitor the nuciencess bound to be happened. On the other side several studies have proved and showed the hit and miss nature of human intervention to spot change in a surrounding environment which increasing the designer challenges for the development of video surveillance system with the help of embedded processor. The designer faces a greater challenge to apply the principle of embedded systems and develop the system smart features with low power and

APA, Harvard, Vancouver, ISO, and other styles

37

Kulkarni, V. A., and G. R. Udupi. "Instruction Level Energy Consumption Estimation of Embedded Processor." European Journal of Engineering Research and Science 4, no. 2 (2019): 40–44. http://dx.doi.org/10.24018/ejers.2019.4.2.1144.

Full text

Abstract:

Embedded systems are portable battery powered devices that have limited power resource. Hence, most of embedded systems need to meet energy constraint. Performance and energy consumption are the most important metrics for embedded system design. Estimation of performance, energy utilization and its validation are essential for embedded system design. Attempt has been made to precisely measure software energy consumption by three methods on ARM Cortex M4 processor. The results are validated with five benchmark programs. Tedious calculation of inter instruction cost has been minimized by taking

APA, Harvard, Vancouver, ISO, and other styles

38

Kulkarni, V. A., and G. R. Udupi. "Instruction Level Energy Consumption Estimation of Embedded Processor." European Journal of Engineering and Technology Research 4, no. 2 (2019): 40–44. http://dx.doi.org/10.24018/ejeng.2019.4.2.1144.

Full text

Abstract:

Embedded systems are portable battery powered devices that have limited power resource. Hence, most of embedded systems need to meet energy constraint. Performance and energy consumption are the most important metrics for embedded system design. Estimation of performance, energy utilization and its validation are essential for embedded system design. Attempt has been made to precisely measure software energy consumption by three methods on ARM Cortex M4 processor. The results are validated with five benchmark programs. Tedious calculation of inter instruction cost has been minimized by taking

APA, Harvard, Vancouver, ISO, and other styles

39

Ma, Wenheng, Qiao Cheng, Yudi Gao, Lan Xu, and Ningmei Yu. "An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture." Micromachines 12, no. 3 (2021): 292. http://dx.doi.org/10.3390/mi12030292.

Full text

Abstract:

Embedded processors are widely used in various systems working on different tasks with different workloads. A more complex micro-architecture leads to better peak performance and worse power consumption. Shutting down the units designed for performance enhancement could improve energy efficiency in low-workload scenarios. In this paper, we evaluated the energy distribution in various embedded processors. According to the analysis, pipeline registers and the dynamic branch predictor, which are employed for better peak performance, have great impacts on energy efficiency. Thus, we proposed an ul

APA, Harvard, Vancouver, ISO, and other styles

40

Singh Thakur, Dharmendra, and Sunil Kumar Shah. "Design and Implementation of High Speed and Area Optimized Vedic Processor for Embedded Systems." Journal of Remote Sensing GIS & Technology 9, no. 3 (2023): 16–26. http://dx.doi.org/10.46610/jorsgt.2023.v09i03.004.

Full text

Abstract:

The proposed work on the design and implementation of a High-Speed and Area-Optimized Vedic Processor for Embedded Systems appears promising. Here's an outline that we might find useful for organizing our work. Discuss briefly the growing need for high-performance embedded systems and the crucial role of processors. Summarize prior research on Vedic Processors, highlighting major features and optimizations gained by earlier researchers. The exact Vedic mathematics ideas and sutras that we propose to exploit in our processor design. Detail tactics for obtaining high-speed operations in the CPU,

APA, Harvard, Vancouver, ISO, and other styles

41

Han, Jin Ho, Mi Young Lee, Younghwan Bae, and Hanjin Cho. "Application Specific Processor Design for H.264 Decoder with a Configurable Embedded Processor." ETRI Journal 27, no. 5 (2005): 491–96. http://dx.doi.org/10.4218/etrij.05.0905.0001.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Grycel, Jacob, and Patrick Schaumont. "SimpliFI: Hardware Simulation of Embedded Software Fault Attacks." Cryptography 5, no. 2 (2021): 15. http://dx.doi.org/10.3390/cryptography5020015.

Full text

Abstract:

Fault injection simulation on embedded software is typically captured using a high-level fault model that expresses fault behavior in terms of programmer-observable quantities. These fault models hide the true sensitivity of the underlying processor hardware to fault injection, and they are unable to correctly capture fault effects in the programmer-invisible part of the processor microarchitecture. We present SimpliFI, a simulation methodology to test fault attacks on embedded software using a hardware simulation of the processor running the software. We explain the purpose and advantage of S

APA, Harvard, Vancouver, ISO, and other styles

43

Vojtko, Martin, and Tibor Krajčovič. "Semi-automated process of adaptation of platform dependent parts of embedded operating systems." Journal of Electrical Engineering 68, no. 2 (2017): 87–98. http://dx.doi.org/10.1515/jee-2017-0013.

Full text

Abstract:

Abstract Each year manufacturers develop new processors. As a reaction to this continuous development, the developers of software have to adapt their software to those new processors. As a minimal requirement, the code of an operating system has to be changed to enable the execution of other user applications. This change is a complicated process during which incompatible parts of an operating system have to be redesigned and missing parts have to be implemented. Complications arise when there is a need to adapt an operating system to completely different processor architecture. In this paper

APA, Harvard, Vancouver, ISO, and other styles

44

Goudarzi, Maziar, Shaahin Hessabi, and Alan Mycroft. "Object-Oriented Embedded System Development Based on Synthesis and Reuse of OO-ASIPs." JUCS - Journal of Universal Computer Science 10, no. (9) (2004): 1123–55. https://doi.org/10.3217/jucs-010-09-1123.

Full text

Abstract:

We present an embedded_system design flow, discuss its details, and demonstrate its advantages. We adopt the object_oriented methodology for the system_level model because software dominates hardware in embedded systems and the object_oriented methodology is already established for software design and reuse. As the building_block of system implementation, we synthesise application_specific processors that are reusable, through programming, for several related applications. This addresses the high cost and risk of manufacturing specialised hardware tailored to only a single application. Both th

APA, Harvard, Vancouver, ISO, and other styles

45

Xing, Wen Qi, Qian Zhong Zhang, and Zi Wei Feng. "A Kind of Embedded Firewall Mechanism for ARM Processors." Applied Mechanics and Materials 556-562 (May 2014): 1757–60. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1757.

Full text

Abstract:

The traditional firewall is a protect mechanism usually between the internal and external network, through the input and output of data packets in real-time network monitoring, it will make protective response immediately if it find security threats. With short data processing time and high efficiency, it can satisfy most procedures of application, but it has high cost and is difficult to achieve. In this paper, in view of these problems, embedded firewall security protection mechanisms set based AMR processor innovation, given the overall framework of embedded firewall hardware and the design

APA, Harvard, Vancouver, ISO, and other styles

46

KWON, YOUNG-SU, and NAK-WOONG EUM. "APPLICATION-ADAPTIVE RECONFIGURATION OF MEMORY ADDRESS SHUFFLER FOR FPGA-EMBEDDED INSTRUCTION-SET PROCESSOR." Journal of Circuits, Systems and Computers 19, no. 07 (2010): 1435–47. http://dx.doi.org/10.1142/s0218126610006748.

Full text

Abstract:

Programmability requirement in reconfigurable systems necessitates the integration of soft processors in FPGAs. The extensive memory bandwidth sets a major performance bottleneck in soft processors for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions in media processors, memory access conflicts caused by multiple memory buses limit the overall performance. We propose and evaluate the configurable memory address shuffler integrated in memory access arbiter for the parallel memory system in a soft processor. The novel

APA, Harvard, Vancouver, ISO, and other styles

47

Kulkarni, V. A., and G. R. Udupi. "Software Power Measurement of ARM Processor Based Embedded System." European Journal of Engineering and Technology Research 1, no. 5 (2018): 5–9. http://dx.doi.org/10.24018/ejeng.2016.1.5.184.

Full text

Abstract:

Energy consumption is very crucial for battery powered Embedded Systems. In recent times, embedded system functionalities are increasing by many folds. But the battery technology is not advancing in the same pace. This necessitates the need to reduce energy consumption of battery powered embedded applications. The total energy of a typical embedded system is due to energy of software and hardware components. Once we know the total energy, we can estimate battery life accurately. Conversely, various measures can be taken to increase battery life. This paper presents measurement based approach t

APA, Harvard, Vancouver, ISO, and other styles

48

LIU, WANLI, DAVID H. ALBONESI, JOHN GOSTOMSKI, et al. "AN EVALUATION OF A CONFIGURABLE VLIW MICROARCHITECTURE FOR EMBEDDED DSP APPLICATIONS." Journal of Circuits, Systems and Computers 13, no. 06 (2004): 1321–45. http://dx.doi.org/10.1142/s0218126604001994.

Full text

Abstract:

The last decade has witnessed a significant increase in processor offerings geared towards embedded DSP applications. Such processors are commonly VLIW architectures with special ISA and/or microarchitecture features for speeding up signal processing functions and customization options to improve cost/performance. The Jazz Programmable System Architecture from Improv Systems is one such processor offering. Jazz employs a VLIW architecture which is well-suited to the characteristics of embedded DSP applications such as voice over packet, media processing, and home connectivity. The microarchite

APA, Harvard, Vancouver, ISO, and other styles

49

Baans, Omar Salem, and Asral Bahari Jambek. "Implementation of an ARM-based system using a Xilinx ZYNQ SoC." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 2 (2019): 485. http://dx.doi.org/10.11591/ijeecs.v13.i2.pp485-491.

Full text

Abstract:

<span>ARM processors are widely used in embedded systems. They are often implemented as microcontrollers, field-programmable gate arrays (FPGAs) or systems-on-chip. In this paper, a variety of ARM processor platform implementations are reviewed, such as implementation into a microcontroller, a system-on-chip and a hybrid ARM-FPGA platform. Furthermore, the implementation of a specific ARM processor, the Cortex-A9 processor, into a system-on-chip (SoC) on an FPGA is discussed using Xilinx’s Vivado and SDK software system and execution on a Xilinx Zynq Board.</span>

APA, Harvard, Vancouver, ISO, and other styles

50

Baans, Omar Salem, and Asral Bahari Jambek. "Implementation of an ARM-Based system using a Xilinx ZYNQ SoC." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 2 (2019): 485–91. https://doi.org/10.11591/ijeecs.v13.i2.pp485-491.

Full text

Abstract:

ARM processors are widely used in embedded systems. They are often implemented as microcontrollers, field-programmable gate arrays (FPGAs) or systems-on-chip. In this paper, a variety of ARM processor platform implementations are reviewed, such as implementation into a microcontroller, a system-on-chip and a hybrid ARM-FPGA platform. Furthermore, the implementation of a specific ARM processor, the CortexA9 processor, into a system-on-chip (SoC) on an FPGA is discussed using Xilinx’s Vivado and SDK software system and execution on a Xilinx Zynq Board.

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!