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Journal articles on the topic 'Embedded Processors'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 September 2023

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1

Pflanz, M., and H. T. Vierhaus. "Generating reliable embedded processors." IEEE Micro 18, no. 5 (1998): 33–41. http://dx.doi.org/10.1109/40.735942.

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2

Wei, Xiaotong, Ying Yang, and Jie Chen. "A Low-Latency Divider Design for Embedded Processors." Sensors 22, no. 7 (March 23, 2022): 2471. http://dx.doi.org/10.3390/s22072471.

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Division is generally regarded as a low-frequency, high-latency operation in integer operations. Division is also the operation that stalls the processor pipeline most frequently. In order to improve the overall performance of embedded processors, a low-delay divider for embedded processors was designed. Based on the non-restoring algorithm, the divider uses a compound adder to execute addition and subtraction simultaneously and reduces the iteration path delay. By shifting the operands to align the most effective bits, the divider dynamically adjusts the number of iteration cycles to reduce t

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3

KWON, YOUNG-SU, and NAK-WOONG EUM. "APPLICATION-ADAPTIVE RECONFIGURATION OF MEMORY ADDRESS SHUFFLER FOR FPGA-EMBEDDED INSTRUCTION-SET PROCESSOR." Journal of Circuits, Systems and Computers 19, no. 07 (November 2010): 1435–47. http://dx.doi.org/10.1142/s0218126610006748.

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Programmability requirement in reconfigurable systems necessitates the integration of soft processors in FPGAs. The extensive memory bandwidth sets a major performance bottleneck in soft processors for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions in media processors, memory access conflicts caused by multiple memory buses limit the overall performance. We propose and evaluate the configurable memory address shuffler integrated in memory access arbiter for the parallel memory system in a soft processor. The novel

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4

Doraipandian, Manivannan, and Periasamy Neelamegam. "Wireless Sensor Network Using ARM Processors." International Journal of Embedded and Real-Time Communication Systems 4, no. 4 (October 2013): 48–59. http://dx.doi.org/10.4018/ijertcs.2013100103.

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The hardware design of Wireless Sensor Networks (WSN) is the crux of its effective deployment. Nowadays these networks are used in microscopic, secure and high-end embedded products. WSN's potentiality in terms of efficient data sensing and distributed data processing has led to its usage in applications for measurement and tracking. WSN comprises of small number of embedded devices known as sensor nodes, gateways and base stations. Sensor nodes consist of sensors, processors and transceivers. The property of embedded sensor devices, also called motes, is to determine the strength of WSN. Thus

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5

Núñez-Prieto, Ricardo, David Castells-Rufas, and Lluís Terés-Terés. "RisCO2: Implementation and Performance Evaluation of RISC-V Processors for Low-Power CO2 Concentration Sensing." Micromachines 14, no. 7 (July 4, 2023): 1371. http://dx.doi.org/10.3390/mi14071371.

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In the field of embedded systems, energy efficiency is a critical requirement, particularly for battery-powered devices. RISC-V processors have gained popularity due to their flexibility and open-source nature, making them an attractive choice for embedded applications. However, not all RISC-V processors are equally energy-efficient, and evaluating their performance in specific use cases is essential. This paper presents RisCO2, an RISC-V implementation optimized for energy efficiency. It evaluates its performance compared to other RISC-V processors in terms of resource utilization and energy

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Muralidharan, K., and S. Uma Maheswari. "Design of Low Power Cam Memory Cell for the Next Generation Network Processors." IRO Journal on Sustainable Wireless Systems 3, no. 4 (December 3, 2021): 208–18. http://dx.doi.org/10.36548/jsws.2021.4.001.

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In the modern world, high performance embedded applications in the field of multimedia, networking, and imaging are increasing day by day. These applications require high performance and more complex out-of-order superscalar processor. These complex dynamic instructions scheduling superscalar processors need higher levels of on-chip integration designs which are often associated with power dissipation. These out-of-order superscalar processors achieve higher performance compared to other processors by simultaneous fetching, decoding and execution for multiple instructions in out-of-order that

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7

Levy, Markus, and Thomas M. Conte. "Embedded Multicore Processors and Systems." IEEE Micro 29, no. 3 (May 2009): 7–9. http://dx.doi.org/10.1109/mm.2009.41.

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8

Dutt, N., and Kiyoung Choi. "Configurable processors for embedded computing." Computer 36, no. 1 (January 2003): 120–23. http://dx.doi.org/10.1109/mc.2003.1160063.

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9

Shin, Youngsoo, Kiyoung Choi, and Takayasu Sakurai. "Power-conscious Scheduling for Real-time Embedded Systems Design." VLSI Design 12, no. 2 (January 1, 2001): 139–50. http://dx.doi.org/10.1155/2001/23925.

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Power efficient design of real-time embedded systems based on programmable processors becomes more important as system functionality is increasingly realized through software. We address a power optimization method for real-time embedded applications on a variable speed processor. The method combines off-line and on-line components. The off-line component determines the lowest possible maximum processor speed while guaranteeing deadlines of all tasks. The on-line component dynamically varies the processor speed or bring a processor into a power-down mode to exploit execution time variations an

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10

Wang, Tun, and Yu Tian. "Design of Embedded Ai Engine Based on the Microkernel Operating System." Wireless Communications and Mobile Computing 2022 (April 21, 2022): 1–9. http://dx.doi.org/10.1155/2022/9304019.

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At present, the application of the embedded microkernel operating system in military and civil fields has begun to take shape, but it has not yet formed a unified method and standard. Due to its high performance, low frequency, and high reliability, dual-core embedded processors are getting the attention of many chip manufacturers. Compatibility has been favored by many telecom equipment manufacturers and embedded high-end application integrators, but the dual-core embedded processor needs a new real-time operating system to support it, so that it can give full play to the high performance of

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11

Xia, Jun. "An Energy-Efficient Approach to Hot-Plugging of Embedded Multiprocessors." Advanced Materials Research 756-759 (September 2013): 4229–34. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.4229.

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With the increasing of the number of processors in one chip, the energy consumption became increasingly important in the low power design of embedded system. In time-sharing OS, different application scenarios lead to different workload. A novel policy for energy saving is that some processors can be hot-plugged on while the workload of the system becomes high and some processors can be hot-plugged off while the workload becomes low. This paper proposed an energy-efficient workload prediction approach called PID prediction algorithm (PPA) which aims dynamic processors number changes for energy

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12

Talawar, Arun K., Sunita S. Malaj, and Raju Hiremath. "An Analysis of : Embedded Systems in Embedded Processors Knack." Gyan Management Journal 17, no. 1 (March 6, 2023): 78–84. http://dx.doi.org/10.48165/gmj.2022.17.1.9.

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The mechanisms via way of means of which software program interacts with the bodily international are converting rapidly. Today’s fashion is “smart” sensors and drives with microprocessors, community interfaces and software program that permit far flung get entry to to sensor records and far flung unit activation. There is likewise the Internet of Things (IoT), Industry 4.0, Industrial Internet, Machine to Machine, Internet of Everything, Smart Planet, TSensors (trillions of sensors) or Fog (similar, however towards the cloud). Earth is an expression of era that deeply connects our bodily and

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13

Vojtko, Martin, and Tibor Krajčovič. "Semi-automated process of adaptation of platform dependent parts of embedded operating systems." Journal of Electrical Engineering 68, no. 2 (March 28, 2017): 87–98. http://dx.doi.org/10.1515/jee-2017-0013.

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Abstract Each year manufacturers develop new processors. As a reaction to this continuous development, the developers of software have to adapt their software to those new processors. As a minimal requirement, the code of an operating system has to be changed to enable the execution of other user applications. This change is a complicated process during which incompatible parts of an operating system have to be redesigned and missing parts have to be implemented. Complications arise when there is a need to adapt an operating system to completely different processor architecture. In this paper

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14

Hyodo, Kazuhito, Hirokazu Noborisaka, and Takashi Yada. "Development of Mechatronics Teaching Materials for Embedded System Engineer Education." Journal of Robotics and Mechatronics 23, no. 5 (October 20, 2011): 611–17. http://dx.doi.org/10.20965/jrm.2011.p0611.

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We have developed a learning environment for embedded system design. The learning environment consists of a multi-purpose controller and terminal devices. The controller consists of main processor (arm) and a multi-core microprocessor (Propeller). The main processor provides the software development environment. The Propeller chip has eight 32-bit processors and can perform simultaneous tasks for multiple users. In addition, the Propeller chip provides a reconfigurable peripheral module. This feature is very useful for the development of educational materials. Teachers can develop various educ

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15

Shreya Mane. "Theoretical Study on Embedded Processor and Networking." international journal of engineering technology and management sciences 7, no. 3 (2023): 861–67. http://dx.doi.org/10.46647/ijetms.2023.v07i03.131.

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Embedded processors are specialized microprocessors designed to perform specific tasks within a larger system or device. They are commonly used in various applications such as consumer electronics, automotive systems, industrial automation, and Internet of Things (IoT) devices. This abstract focuses on the role of embedded processors in networking applications. Networking refers to the interconnection of devices and systems to enable communication and data exchange. Embedded processors play a crucial role in networking by providing the necessary computational power and functionality to handle

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16

Coombs, Joseph, Rahul Prabhu, and Greg Peake. "Overcoming the Challenges of Porting OpenCV to TI's Embedded ARM + DSP Platforms." International Journal of Electrical Engineering & Education 49, no. 3 (July 2012): 260–74. http://dx.doi.org/10.7227/ijeee.49.3.6.

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The growing performance and decreasing price of embedded processors are opening many doors, for both developers in the industry and in academia. However, the complexities of these systems can create serious developmental bottlenecks. Sophisticated software packages such as OpenCV can assist in both the functional development and educational aspects of these otherwise complex applications; such tools lend themselves very well to use by the academic community, in particular in providing examples of algorithm implementation. However the task of migrating this software to embedded platforms poses

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17

OSKIN, MARK, DIANA KEEN, JUSTIN HENSLEY, LUCIAN-VLAD LITA, and FREDERIC T. CHONG. "OPERATING SYSTEMS TECHNIQUES FOR PARALLEL COMPUTATION IN INTELLIGENT MEMORY." Parallel Processing Letters 12, no. 03n04 (September 2002): 311–26. http://dx.doi.org/10.1142/s0129626402001014.

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Advances in DRAM density have led to several proposals to perform computation in memory [1] [2] [3]. Active Pages is a page-based model of intelligent memory that can exploit large amounts of parallel computation in data-intensive applications. With a simple VLIW processor embedded near each page on DRAM, Active Page memory systems achieve up to 1000X speedups over conventional memory systems [4]. Active Pages are specifically designed to support virtualized hardware resources. In this study, we examine operating system techniques that allow Active Page memories to share, or multiplex, embedde

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18

Bui, Phuc, Minh Le, Binh Hoang, Nguyen Ngoc, and Huong Pham. "Data Partitioning and Asynchronous Processing to Improve the Embedded Software Performance on Multicore Processors." Informatics and Automation 21, no. 2 (February 17, 2022): 243–74. http://dx.doi.org/10.15622/ia.21.2.2.

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Nowadays, ensuring information security is extremely inevitable and urgent. We are also witnessing the strong development of embedded systems, IoT. As a result, research to ensure information security for embedded software is being focused. However, studies on optimizing embedded software on multi-core processors to ensure information security and increase the performance of embedded software have not received much attention. The paper proposes and develops the embedded software performance improvement method on multi-core processors based on data partitioning and asynchronous processing. Data

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19

Yoon, Young Hyun, Dong Hyun Hwang, Jun Hyeok Yang, and Seung Eun Lee. "Intellino: Processor for Embedded Artificial Intelligence." Electronics 9, no. 7 (July 18, 2020): 1169. http://dx.doi.org/10.3390/electronics9071169.

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The development of computation technology and artificial intelligence (AI) field brings about AI to be applied to various system. In addition, the research on hardware-based AI processors leads to the minimization of AI devices. By adapting the AI device to the edge of internet of things (IoT), the system can perform AI operation promptly on the edge and reduce the workload of the system core. As the edge is influenced by the characteristics of the embedded system, implementing hardware which operates with low power in restricted resources on a processor is necessary. In this paper, we propose

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20

Wang, Jiandi. "Research Status and Prospect of Embedded System." Highlights in Science, Engineering and Technology 46 (April 25, 2023): 49–55. http://dx.doi.org/10.54097/hset.v46i.7663.

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Embedded system is one of the key research topics nowadays. The engineers found that embedded system can be applied in many electronic engineering fields, such as daily household appliances, industrial control, etc. A complete embedded system includes all of the necessary components, such as an embedded processor, hardware structure, software system, and operating system. The central characteristics of embedded systems are the heterogeneity of their implementation technologies (digital hardware, software), the tightness of their nonfunctional requirements, and their complexity. Despite the fac

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21

Moyer, B. "Low-power design for embedded processors." Proceedings of the IEEE 89, no. 11 (2001): 1576–87. http://dx.doi.org/10.1109/5.964439.

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22

Leupers, R. "Compiler design issues for embedded processors." IEEE Design & Test of Computers 19, no. 4 (July 2002): 51–58. http://dx.doi.org/10.1109/mdt.2002.1018133.

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23

Zhuang, Xiaotong, and Santosh Pande. "Power-efficient prefetching for embedded processors." ACM Transactions on Embedded Computing Systems 6, no. 1 (February 2007): 3. http://dx.doi.org/10.1145/1210268.1210271.

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24

Wang, Chenxu, Jiamin Zheng, and Mingyan Yu. "Cache Performance Research for Embedded Processors." Physics Procedia 25 (2012): 1322–28. http://dx.doi.org/10.1016/j.phpro.2012.03.239.

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25

Chocholac, Jaromir. "Embedded Processors for Networking and Communications." IFAC Proceedings Volumes 33, no. 1 (February 2000): 77–80. http://dx.doi.org/10.1016/s1474-6670(17)35590-8.

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26

Kozyrakis, C. E., and D. A. Patterson. "Scalable vector processors for embedded systems." IEEE Micro 23, no. 6 (November 2003): 36–45. http://dx.doi.org/10.1109/mm.2003.1261385.

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27

Sarma, M. Sandeep, K. V. Ravi Kumar, B. Rajesh Kumar, and P. H. S. T. Murthy. "Digital Signal Processing On Embedded Processors." International Journal of Engineering Trends and Technology 22, no. 5 (April 25, 2015): 222–24. http://dx.doi.org/10.14445/22315381/ijett-v22p247.

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28

Bonny, Talal, and JÖrg Henkel. "Efficient Code Compression for Embedded Processors." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16, no. 12 (December 2008): 1696–707. http://dx.doi.org/10.1109/tvlsi.2008.2001950.

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29

Jayaseelan, Ramkumar, and Tulika Mitra. "Temperature Aware Scheduling for Embedded Processors." Journal of Low Power Electronics 5, no. 3 (October 1, 2009): 363–72. http://dx.doi.org/10.1166/jolpe.2009.1036.

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30

Kondo, Hiroyuki, Masami Nakajima, Miroslaw Bober, Krzysztof Kucharski, Osamu Yamamoto, and Toru Shimizu. "Implementation of Face Recognition Processing Using an Embedded Processor." Journal of Robotics and Mechatronics 17, no. 4 (August 20, 2005): 428–36. http://dx.doi.org/10.20965/jrm.2005.p0428.

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Embedded processors are conventionally difficult to use in face recognition in the security and robotic fields because of the tremendous amount of processing required. We implemented face recognition processing with a multicore based embedded processor having low power consumption and high performance. The single-chip multiprocessor is manufactured using a 0.15μm process with two M32R cores, 512KB of SRAM, and peripheral circuits integrated on a single-chip. It has a power supply voltage of 1.5V, a frequency of 600MHz, and power consumption of 800mW.

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31

Ma, Wenheng, Qiao Cheng, Yudi Gao, Lan Xu, and Ningmei Yu. "An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture." Micromachines 12, no. 3 (March 10, 2021): 292. http://dx.doi.org/10.3390/mi12030292.

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Embedded processors are widely used in various systems working on different tasks with different workloads. A more complex micro-architecture leads to better peak performance and worse power consumption. Shutting down the units designed for performance enhancement could improve energy efficiency in low-workload scenarios. In this paper, we evaluated the energy distribution in various embedded processors. According to the analysis, pipeline registers and the dynamic branch predictor, which are employed for better peak performance, have great impacts on energy efficiency. Thus, we proposed an ul

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32

Cantero, David, Iker Esnaola-Gonzalez, Jose Miguel-Alonso, and Ekaitz Jauregi. "Benchmarking Object Detection Deep Learning Models in Embedded Devices." Sensors 22, no. 11 (May 31, 2022): 4205. http://dx.doi.org/10.3390/s22114205.

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Object detection is an essential capability for performing complex tasks in robotic applications. Today, deep learning (DL) approaches are the basis of state-of-the-art solutions in computer vision, where they provide very high accuracy albeit with high computational costs. Due to the physical limitations of robotic platforms, embedded devices are not as powerful as desktop computers, and adjustments have to be made to deep learning models before transferring them to robotic applications. This work benchmarks deep learning object detection models in embedded devices. Furthermore, some hardware

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33

Götze, Johannes. "Comparison of acceleration methods of matrix calculations in embedded systems." Embedded Selforganising Systems 6, no. 1 (December 27, 2019): 9–17. http://dx.doi.org/10.14464/ess61429.

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In today's algorithms for sound localization techniques, matrix calculations are ubiquitous. Therefore, this work deals with the analysis of matrix calculations and their possible realization on embedded systems. For this purpose, common acceleration technologies such as processors, GPU processing and acceleration with the help of FPGAs are compared. The results show that a graphics chip is capable to accelerate such a matrix vector multiplication compared to an implementation on a processor. Therefore a runtime of an implementation on an FPGA cannot be achieved by a GPU.

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34

Gauthier, Lovic, and Tohru Ishihara. "Processor Energy Characterization for Compiler-Assisted Software Energy Reduction." Journal of Electrical and Computer Engineering 2012 (2012): 1–16. http://dx.doi.org/10.1155/2012/786943.

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Energy consumption is a fundamental barrier in taking full advantage of today and future semiconductor manufacturing technologies. The paper presents our recent research activities and results on characterizing and reducing the energy consumption in embedded systems. Firstly, a technique for characterizing the energy consumption of embedded processors during an application execution is presented. The technique trains a per-processor linear approximation model for fitting it to the energy consumption of the processor obtained by postlayout simulation. Secondly, based on the energy model mention

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35

Manor, Erez, Avrech Ben-David, and Shlomo Greenberg. "CORDIC Hardware Acceleration Using DMA-Based ISA Extension." Journal of Low Power Electronics and Applications 12, no. 1 (January 15, 2022): 4. http://dx.doi.org/10.3390/jlpea12010004.

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The use of RISC-based embedded processors aimed at low cost and low power is becoming an increasingly popular ecosystem for both hardware and software development. High-performance yet low-power embedded processors may be attained via the use of hardware acceleration and Instruction Set Architecture (ISA) extension. Recent publications of AI have demonstrated the use of Coordinate Rotation Digital Computer (CORDIC) as a dedicated low-power solution for solving nonlinear equations applied to Neural Networks (NN). This paper proposes ISA extension to support floating-point CORDIC, providing effi

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36

Cooper, Keith D., and Nathaniel McIntosh. "Enhanced code compression for embedded RISC processors." ACM SIGPLAN Notices 34, no. 5 (May 1999): 139–49. http://dx.doi.org/10.1145/301631.301655.

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37

Ubal, R., J. Sahuquillo, S. Petit, H. Hassan, and P. López. "Power Reduction In Advanced Embedded IPC Processors." Intelligent Automation & Soft Computing 15, no. 3 (January 2009): 495–507. http://dx.doi.org/10.1080/10798587.2009.10643045.

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38

Kranitis, N., A. Paschalis, D. Gizopoulos, and G. Xenoulis. "Software-Based Self-Testing of Embedded Processors." IEEE Transactions on Computers 54, no. 4 (April 2005): 461–75. http://dx.doi.org/10.1109/tc.2005.68.

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39

Hyeran Jeon, Woo Hyong Lee, and Sung Woo Chung. "Load Unbalancing Strategy for Multicore Embedded Processors." IEEE Transactions on Computers 59, no. 10 (October 2010): 1434–40. http://dx.doi.org/10.1109/tc.2009.181.

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40

Levison, Nadav, and Shlomo Weiss. "Branch target buffer design for embedded processors." Microprocessors and Microsystems 34, no. 6 (October 2010): 215–27. http://dx.doi.org/10.1016/j.micpro.2010.04.005.

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41

Zhuang, Xiaotong, Tao Zhang, and Santosh Pande. "Hardware-managed register allocation for embedded processors." ACM SIGPLAN Notices 39, no. 7 (July 11, 2004): 192–201. http://dx.doi.org/10.1145/998300.997191.

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42

Ayala, José L., Cándido Méndez, and Marisa López-Vallejo. "Thermal analysis and modeling of embedded processors." Computers & Electrical Engineering 36, no. 1 (January 2010): 142–54. http://dx.doi.org/10.1016/j.compeleceng.2009.07.001.

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43

Kim, Jongmyon, Linda M. Wills, and D. Scott Wills. "Color-Aware Instructions for Embedded Superscalar Processors." Journal of Signal Processing Systems 64, no. 3 (May 22, 2010): 335–50. http://dx.doi.org/10.1007/s11265-010-0497-2.

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44

Nojiri, Tohru, Yuki Kondo, Naohiko Irie, Masayuki Ito, Hajime Sasaki, and Hideo Maejima. "Domain Partitioning Technology for Embedded Multicore Processors." IEEE Micro 29, no. 6 (November 2009): 7–17. http://dx.doi.org/10.1109/mm.2009.96.

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45

Miller, Jason E., and Anant Agarwal. "Software-based instruction caching for embedded processors." ACM SIGOPS Operating Systems Review 40, no. 5 (October 20, 2006): 293–302. http://dx.doi.org/10.1145/1168917.1168894.

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46

Miller, Jason E., and Anant Agarwal. "Software-based instruction caching for embedded processors." ACM SIGPLAN Notices 41, no. 11 (November 2006): 293–302. http://dx.doi.org/10.1145/1168918.1168894.

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47

Miller, Jason E., and Anant Agarwal. "Software-based instruction caching for embedded processors." ACM SIGARCH Computer Architecture News 34, no. 5 (October 20, 2006): 293–302. http://dx.doi.org/10.1145/1168919.1168894.

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48

Park, Sungkyung, and Chester Sungchung Park. "Design of Low-Gate-Count Low-Power Microprocessors with High Code Density for Deeply Embedded Applications." Journal of Circuits, Systems and Computers 26, no. 09 (April 24, 2017): 1750132. http://dx.doi.org/10.1142/s0218126617501328.

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Deeply embedded applications demand small area, low power, high code density, and low design complexity for high adaptability. Both a 16-bit microprocessor with a 4G byte linear memory space and a 4-bit processor are proposed and designed to achieve these goals. Hardware reuse and sharing, multicycle architecture, compact instruction set architecture, and counter-based instruction decoder are utilized to reduce gate count. As a result, gate count and power dissipation of the synthesized ASIC gate-level netlists of 16-bit and 4-bit processors are less than 14,000, 1,490, 0.5[Formula: see text]m

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Hendarmawan, Morihiro Kuga, and Masahiro Iida. "Streaming Accelerator Design for Regular Expression on CPU+FPGA Embedded System." ECTI Transactions on Computer and Information Technology (ECTI-CIT) 16, no. 4 (October 11, 2022): 448–59. http://dx.doi.org/10.37936/ecti-cit.2022164.249268.

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A pattern matching application is one of the necessary tasks in streaming data processing. A hardware accelerator employing FPGA can be faster than a general-purpose processor in performing data pattern matching using regular expression methods. However, it is difficult and time-consuming to design the hardware on the FPGA for each regular expression pattern. We are researching a method for automatically designing hardware accelerators for higher efficiency and performance to improve user productivity. In this research, we propose rules and methods for translating regular expression patterns i

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50

Xing, Wen Qi, Qian Zhong Zhang, and Zi Wei Feng. "A Kind of Embedded Firewall Mechanism for ARM Processors." Applied Mechanics and Materials 556-562 (May 2014): 1757–60. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1757.

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The traditional firewall is a protect mechanism usually between the internal and external network, through the input and output of data packets in real-time network monitoring, it will make protective response immediately if it find security threats. With short data processing time and high efficiency, it can satisfy most procedures of application, but it has high cost and is difficult to achieve. In this paper, in view of these problems, embedded firewall security protection mechanisms set based AMR processor innovation, given the overall framework of embedded firewall hardware and the design

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