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Journal articles on the topic 'EMV Chip'

Author: Grafiati

Published: 7 June 2025

Last updated: 17 July 2025

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Olowolayemo, Akeem, Nafisat Adewale, Akram M. Zeki, and Zubair Ahmad. "Examining Users’ Understanding of Security Failures in EMV Smart Card Payment Systems." JOIV : International Journal on Informatics Visualization 3, no. 2 (2019): 185. http://dx.doi.org/10.30630/joiv.3.2.244.

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New credit cards containing Europay, MasterCard and Visa (EMV) chips for enhanced security, and for in-store purchases (rather than online purchases) have been adopted considerably in recent years. EMV supposedly protects the payment cards in such a way that the computer chips in a card referred to as chip-and-pin cards generate a unique one-time code each time the card is used. The one-time code is designed such that if it is copied or stolen from the merchant system or from the system terminal, it cannot be useful for creating a counterfeit copy of that card or counterfeit chip of the transaction. However, in spite of this design, EMV technology is not entirely foolproof from failure. This paper dis-cusses the issues, failures and fraudulent cases associated with EMV Chip-And-Card technology. The work also evaluates people’s understanding of these issues and the consequential precautions they take to safeguard their information while using the EMV cards for transactions.

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Brumercikova, Eva, and Bibiana Bukova. "Proposals for Using the NFC Technology in Regional Passenger Transport in the Slovak Republic." Open Engineering 10, no. 1 (2020): 238–44. http://dx.doi.org/10.1515/eng-2020-0005.

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AbstractNFC (Near Field Communication) devices are used in contactless payment systems, similar to those used in credit cards and electronic ticket smart cards, and they allow a mobile payment to replace or supplement these systems. The trend of increasing the quality of transport services also includes the use of progressive information technologies. The article focuses on the use of NFC technology in regional passenger transport. In the first proposal, the implementation of NFC technology in the form of an electronic wallet in a regional contactless chip card is being considered. In the second proposal we deal with the implementation of NFC technology in regional passenger transport using mobile phones with an active NFC chip. The proposals use Check-In/Check-Out validation, where validators are placed in vehicles. In both proposals it would be possible to create a link to EMV (Europay/MasterCard/VISA) technology, and thus to provide a linking of a contactless smart card, possibly a mobile phone to the passenger’s personal account.

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Nagesh Mapari, Samiksha Sandip Borkar, Karan Pradip Morey, Harshwardhan Tejrao Pawar, and Om Vishwanath Vasu. "A Systematic Credit Card Analysis for Detection of Compromised Data Using Machine Learning." International Research Journal on Advanced Engineering and Management (IRJAEM) 3, no. 04 (2025): 1273–77. https://doi.org/10.47392/irjaem.2025.0208.

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Credit card security is paramount for banks, especially during the pre-issuance phase. This paper examines the multifaceted security measures implemented by banks to protect credit cards and cardholder data before a card is even issued. We explore the vulnerabilities inherent in the card production and personalization processes, and analyze the various countermeasures employed to mitigate these risks. These include secure printing facilities, data encryption, EMV chip technology integration, and rigorous access controls. Furthermore, we discuss the importance of robust data security protocols for safeguarding sensitive information during application processing and account setup. This paper highlights the proactive approach taken by banks to minimize the potential for fraud and data breaches in the critical pre-issuance stage, ensuring the integrity and security of the credit card ecosystem. The findings emphasize the continuous need for vigilance and innovation in security practices to stay ahead of evolving threats and maintain customer trust.

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Lai-hua, Zhu, Liang Cheng-zhu, Lu Cheng-ping, et al. "The development of a diagnostic gene chip for detecting five kinds of viruses in horses." Chinese Journal of Agricultural Biotechnology 3, no. 3 (2006): 209–15. http://dx.doi.org/10.1079/cjb2006112.

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AbstractThe highly conserved DNAs of Equine herpesvirus-1 (EHV-1), Equine arteritis virus (EAV), Equine influenza virus (EIV), Equine infectious anaemia virus (EIAV) and Eastern equine encephalomyelitis virus (EEEV) were acquired by molecular cloning, and spotted on the diagnostic gene chip. The cDNAs reverse-transcribed from RNAs of samples were labelled with Cy5-dUTP/Cy3-dUTP as fluorescent probes. Following specific hybridization of the deposited gene chip and labelled probes, fluorescence signals were scanned by laser scanner and the resulting image was analysed by QiamtArray software on a digital computer. The results showed that the prepared gene chip could detect and distinguish the five equine viruses. Its sensitivity was about 25 viral genome copies. The hybridization specificity was confirmed by the presence of red fluorescence signals on the corresponding sites with samples from the five relevant viruses in horses and by the absence of positive signals with the specimens from irrelevant viruses from other animals. Peripheral blood leucocytes (PBL) from some seropositive horses in post-arrival quarantine were negative according to virus isolation, but were positive for EHV-1 and EAV according to the gene chip technique. The overall results suggest that gene chips, which are quick, specific, sensitive and reliable, can provide a practical alternative for screening quarantined animals, and will be able to deal with a large number of animal samples within a very short period of time.

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Won, Yoo-Seung, Jonghyeok Lee, and Dong-Guk Han. "Side Channel Leakages Against Financial IC Card of the Republic of Korea." Applied Sciences 8, no. 11 (2018): 2258. http://dx.doi.org/10.3390/app8112258.

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Integrated circuit (IC) chip cards are commonly used in payment system applications since they can provide security and convenience simultaneously. More precisely, Europay, MasterCard, and VISA (EMV) are widely known to be well equipped with security frameworks that can defend against malicious attacks. On the other hand, there are other payment system applications at the national level. In the case of the Republic of Korea, standards for financial IC card specifications are established by the Korea Financial Telecommunications and Clearings Institute. Furthermore, security features defending against timing analysis, power analysis, electromagnetic analysis, and TEMPEST are required. This paper identifies side channel leakages in the financial IC cards of the Republic of Korea, although there may be side channel countermeasures. Side channel leakages in the financial IC cards of the Republic of Korea are identified for the first time since the side channel countermeasures were included in the standards. The countermeasure that is applied to the IC card from a black box perspective is estimated to measure security features against power analysis. Then, in order to investigate whether an underlying countermeasure is applied, first-order and second-order power analyses are performed on the main target, e.g., a S-box of the block cipher SEED that is employed in the financial system. Furthermore, the latest proposal in ICISC 2017 is examined to apply block cipher SEED to the financial IC card protocol. As a result, it is possible to identify some side channel leakages while expanding the lemma of the paper accepted in ICISC 2017. Algebraic logic is also constructed to recover the master key from some round keys. Finally, it is found that only 20,000 traces are required to find the master key.

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Blackburn, Simon R., and Sam Scott. "The discrete logarithm problem for exponents of bounded height." LMS Journal of Computation and Mathematics 17, A (2014): 148–56. http://dx.doi.org/10.1112/s1461157014000230.

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AbstractLet $\def \xmlpi #1{}\def \mathsfbi #1{\boldsymbol {\mathsf {#1}}}\let \le =\leqslant \let \leq =\leqslant \let \ge =\geqslant \let \geq =\geqslant \def \Pr {\mathit {Pr}}\def \Fr {\mathit {Fr}}\def \Rey {\mathit {Re}}G$ be a cyclic group written multiplicatively (and represented in some concrete way). Let $n$ be a positive integer (much smaller than the order of $G$). Let $g,h\in G$. The bounded height discrete logarithm problem is the task of finding positive integers $a$ and $b$ (if they exist) such that $a\leq n$, $b\leq n$ and $g^a=h^b$. (Provided that $b$ is coprime to the order of $g$, we have $h=g^{a/b}$ where $a/b$ is a rational number of height at most $n$. This motivates the terminology.)The paper provides a reduction to the two-dimensional discrete logarithm problem, so the bounded height discrete logarithm problem can be solved using a low-memory heuristic algorithm for the two-dimensional discrete logarithm problem due to Gaudry and Schost. The paper also provides a low-memory heuristic algorithm to solve the bounded height discrete logarithm problem in a generic group directly, without using a reduction to the two-dimensional discrete logarithm problem. This new algorithm is inspired by (but differs from) the Gaudry–Schost algorithm. Both algorithms use $O(n)$ group operations, but the new algorithm is faster and simpler than the Gaudry–Schost algorithm when used to solve the bounded height discrete logarithm problem. Like the Gaudry–Schost algorithm, the new algorithm can easily be carried out in a distributed fashion.The bounded height discrete logarithm problem is relevant to a class of attacks on the privacy of a key establishment protocol recently published by EMVCo for comment. This protocol is intended to protect the communications between a chip-based payment card and a terminal using elliptic curve cryptography. The paper comments on the implications of these attacks for the design of any final version of the EMV protocol.

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Su, T., Y. Huang, and Z. Wang. "An On-Chip EMI Sensor Array." ECS Transactions 52, no. 1 (2013): 853–58. http://dx.doi.org/10.1149/05201.0853ecst.

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Loipold, G., and B. Deutschmann. "EMC awareness for multi chip modules." e & i Elektrotechnik und Informationstechnik 122, no. 12 (2005): 460–65. http://dx.doi.org/10.1007/bf03054379.

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Wang, Xiyou, Sicheng Cao, Guangsheng Lu, and Daoguo Yang. "Viscoelastic Simulation of Stress and Warpage for Memory Chip 3D-Stacked Package." Coatings 12, no. 12 (2022): 1976. http://dx.doi.org/10.3390/coatings12121976.

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Three-dimensional-stacked packaging technology is widely used in memory chip packaging, which can greatly increase the utilization ratio of the packaging area. However, problems with the reliability of 3D-stacked packaging are also becoming more and more serious. In this paper, first, a dynamic mechanical analyzer is used to obtain the EMC viscoelasticity parameters. Then, the influence trend of different factors, such as EMC, die bond material and chip, on the performance of the memory chip 3D-stacked packaging under a fixed temperature cyclic loading condition is explored by the FE method.

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Morais, Pedro, Alireza Akhavan-Safar, Ricardo J. C. Carbas, Eduardo A. S. Marques, Bala Karunamurthy, and Lucas F. M. da Silva. "Mode I Fatigue and Fracture Assessment of Polyimide–Epoxy and Silicon–Epoxy Interfaces in Chip-Package Components." Polymers 16, no. 4 (2024): 463. http://dx.doi.org/10.3390/polym16040463.

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Semiconductor advancements demand greater integrated circuit density, structural miniaturization, and complex material combinations, resulting in stress concentrations from property mismatches. This study investigates the failure in two types of interfaces found in chip packages: silicon–epoxy mold compound (EMC) and polyimide–EMC. These interfaces were subjected to quasi-static and fatigue loading conditions. Employing a compliance-based beam method, the tests determined interfacial critical fracture energy values, (GIC), of 0.051 N/mm and 0.037 N/mm for the silicon–EMC and polyimide–EMC interfaces, respectively. Fatigue testing on the polyimide–epoxy interface revealed a fatigue threshold strain energy, (Gth), of 0.042 N/mm. We also observed diverse failure modes and discuss potential mechanical failures in multi-layer chip packages. The findings of this study can contribute to the prediction and mitigation of failure modes in the analyzed chip packaging. The obtained threshold energy and crack growth rate provide insights for designing safe lives for bi-material interfaces in chip packaging under cyclic loads. These insights can guide future research directions, emphasizing the improvement of material properties and exploration of the influence of manufacturing parameters on delamination in multilayer semiconductors.

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Schmidt, Stefanie C. S., Sizun Jiang, Hufeng Zhou, et al. "Epstein–Barr virus nuclear antigen 3A partially coincides with EBNA3C genome-wide and is tethered to DNA through BATF complexes." Proceedings of the National Academy of Sciences 112, no. 2 (2014): 554–59. http://dx.doi.org/10.1073/pnas.1422580112.

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Epstein–Barr Virus (EBV) conversion of B-lymphocytes to Lymphoblastoid Cell Lines (LCLs) requires four EBV nuclear antigen (EBNA) oncoproteins: EBNA2, EBNALP, EBNA3A, and EBNA3C. EBNA2 and EBNALP associate with EBV and cell enhancers, up-regulate the EBNA promoter, MYC, and EBV Latent infection Membrane Proteins (LMPs), which up-regulate BCL2 to protect EBV-infected B-cells from MYC proliferation-induced cell death. LCL proliferation induces p16INK4A and p14ARF-mediated cell senescence. EBNA3A and EBNA3C jointly suppress p16INK4A and p14ARF, enabling continuous cell proliferation. Analyses of the EBNA3A human genome-wide ChIP-seq landscape revealed 37% of 10,000 EBNA3A sites to be at strong enhancers; 28% to be at weak enhancers; 4.4% to be at active promoters; and 6.9% to be at weak and poised promoters. EBNA3A colocalized with BATF-IRF4, ETS-IRF4, RUNX3, and other B-cell Transcription Factors (TFs). EBNA3A sites clustered into seven unique groups, with differing B-cell TFs and epigenetic marks. EBNA3A coincidence with BATF-IRF4 or RUNX3 was associated with stronger EBNA3A ChIP-Seq signals. EBNA3A was at MYC, CDKN2A/B, CCND2, CXCL9/10, and BCL2, together with RUNX3, BATF, IRF4, and SPI1. ChIP-re-ChIP revealed complexes of EBNA3A on DNA with BATF. These data strongly support a model in which EBNA3A is tethered to DNA through a BATF-containing protein complexes to enable continuous cell proliferation.

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GÜÇLÜER, Sinan. "A Battery Powered on-Chip Peristaltic Pump for Lab-On-A-Chip Applications." European Mechanical Science 5, no. 4 (2021): 201–5. http://dx.doi.org/10.26701/ems.876597.

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Peng, Chih-Wen, Bo Zhao, Hong-Chi Chen, et al. "Hsp72 up-regulates Epstein-Barr virus EBNALP coactivation with EBNA2." Blood 109, no. 12 (2007): 5447–54. http://dx.doi.org/10.1182/blood-2006-08-040634.

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AbstractThe Epstein-Barr virus (EBV) transcriptional coactivator EBNALP specifically associates and colocalizes with Hsp72 in lymphoblastoid cell lines. We now find that overexpression of Hsp72 more than doubled EBNALP coactivation with EBNA2 of a transfected EBV LMP1 promoter in B lymphoblasts, did not affect EBNA2 or EBNALP protein levels, and strongly up-regulated EBNA2 and EBNALP coactivation of LMP1 protein expression from the endogenous EBV genome in latency I infected Akata cells. The Hsp72 ATP, protein binding, and the C-terminal regulatory domains were required for full activity. An EBNALP deletion mutant, EBNALPd45, which does not associate with Hsp72, coactivated with EBNA2, but was not affected by Hsp72 overexpression, despite Hsp72 up-regulation of wild-type EBNALP coactivation with EBNA2 at all levels of EBNALP expression, indicating the importance of Hsp72 association with EBNALP for Hsp72 up-regulation of coactivation. Of importance, a 90% RNAi knockdown of Hsp72 reduced EBNALP coactivation with EBNA2 of transfected EBV LMP1 and Cp promoters by approximately 50%. Overexpression of the Hsp72 C-terminal interacting and regulatory protein, CHIP, strongly down-regulated EBNALP coactivation, independently of CHIP ubiquitin ligase activity. CHIP effects were Hsp72 dependent, indicating a background downmodulating role for CHIP in Hsp72 augmentation of EBNA2 and EBNALP coactivation. Based on these and other cited data, we favor a model in which Hsp72 chaperones EBNALP shuttling of repressors from EBNA2-enhanced promoters.

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Vargas, Fabian. "Design and test on chip for EMC." IEEE Design and Test of Computers 23, no. 6 (2006): 502–3. http://dx.doi.org/10.1109/mdt.2006.143.

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Yen, Ching-Yu, Min-Chi Lu, Ching-Cherng Tzeng, et al. "Detection of EBV Infection and Gene Expression in Oral Cancer from Patients in Taiwan by Microarray Analysis." Journal of Biomedicine and Biotechnology 2009 (2009): 1–15. http://dx.doi.org/10.1155/2009/904589.

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Epstein-Barr virus is known to cause nasopharyngeal carcinoma. Although oral cavity is located close to the nasal pharynx, the pathogenetic role of Epstein-Barr virus (EBV) in oral cancers is unclear. This molecular epidemiology study uses EBV genomic microarray (EBV-chip) to simultaneously detect the prevalent rate and viral gene expression patterns in 57 oral squamous cell carcinoma biopsies (OSCC) collected from patients in Taiwan. The majority of the specimens (82.5%) were EBV-positive that probably expressed coincidently the genes for EBNAs, LMP2A and 2B, and certain structural proteins. Importantly, the genes fabricated at the spots 61 (BBRF1, BBRF2, and BBRF3) and 68 (BDLF4 and BDRF1) on EBV-chip were actively expressed in a significantly greater number of OSCC exhibiting exophytic morphology or ulceration than those tissues with deep invasive lesions (P=.0265and .0141, resp.). The results may thus provide the lead information for understanding the role of EBV in oral cancer pathogenesis.

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Iwai, Masahiro, Ken Ukawa, Go Ichizawa, and Takeshi Mori. "Latest Technologies of Epoxy Molding Compound (EMC) for FO-WLP." International Symposium on Microelectronics 2020, no. 1 (2020): 000051–56. http://dx.doi.org/10.4071/2380-4505-2020.1.000051.

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Abstract FO-WLP is used for RF etc. for mobile as a package excellent in low profile, low warpage, cost reduction, electric performance etc. and this market is expanding since it began to be used in Application processer (AP) in 2016. It is expected that adoption to AP for mobile will continue to grow and further expansion to other products is also expected. Meanwhile, Epoxy molding compound (EMC) for FO-WLP is required to have functions not found in EMC for low-end packages. For example, since the molding area is large and the molding thickness is thin, if a conventional EMC is used, the warpage becomes large after curing and it cannot proceed to the subsequent process. In order to control warpage after curing, it is important to reduce cure shrinkage of EMC. In addition, in order to fill completely the gap between flip chip bumps of large size chip, control of filler size, melt viscosity etc. is more severely required.

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Monirul Islam, Monirul Islam. "On-Chip Techniques for Electromagnetic Interference (EMI) reduction." IOSR journal of VLSI and Signal Processing 2, no. 4 (2013): 47–52. http://dx.doi.org/10.9790/4200-0244752.

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Jeon, Hyoil, Zeeshan A. Khan, Emad Barakat, and Seungkyung Park. "Label-Free Electrochemical Microfluidic Chip for the Antimicrobial Susceptibility Testing." Antibiotics 9, no. 6 (2020): 348. http://dx.doi.org/10.3390/antibiotics9060348.

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The emergence and spread of antibiotic-resistant bacteria is a global threat to human health. An accurate antibiotic susceptibility test (AST) before initiating the treatment is paramount in the treatment and bacterial resistance control. However, the current AST methods either are complex, use chemical and biological labels, lack multiplexing, are expensive, or are too slow to be used for routine screening. The primary objective of the current study is to develop an automated electrochemical microfluidic chip (EMC) for simple and rapid AST. The microfluidic channels and gold microelectrodes were designed for the automation of antibiotic mixing and distribution in multiple test chambers and for electrical signal measurements. The designed chip was tested for AST with E. coli samples, and the results were compared with conventional broth microdilution. The presented EMC provided rapid bacterial count and AST in 170 and 150 min, respectively, while the conventional broth microdilution evaluates in 450 and 240 min, respectively. The rapid AST capability of the EMC was further demonstrated with the artificial urine samples, and the results were obtained in 270 min, which was 90 min faster than the broth microdilution method. Additionally, the minimum inhibitory concentration (MIC) was evaluated on the EMC and compared with the results from an AlamarBlue assay. The experimental results indicate the sensitivity of the chip, minimum loss of antibiotics, and eventually, reduction in the evolution of antibiotic resistance. Cumulatively, we have developed an automated, label-free, economical, rapid, robust, and user-friendly EMC for the evaluation of AST in urine samples.

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Cho, In-Kui, Jae-Hoon Yun, Myung-Yung Jeong, and Hyo-Hoon Park. "Optical Chip-to-Chip Link System by Using Optical Wiring Method for Reducing EMI." IEEE Transactions on Advanced Packaging 33, no. 3 (2010): 722–28. http://dx.doi.org/10.1109/tadvp.2010.2049018.

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La Fratta, Patrick Anthony, and James M. Baker. "Exploring power reduction options for a single-chip multiprocessor through system-level modeling." Journal of Embedded Computing 2, no. 2 (2006): 235–47. https://doi.org/10.3233/emc-2006-00024.

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Moore's law predicts that fabrication processes will soon yield over a billion transistors on a single die. Over the past twenty years, the gap between the amount of available real estate on a chip and designer productivity has widened and continues to grow, so that designers are less able to make effective use of the increasing number of transistors on a chip. The primary problem in system-on-a-chip (SoC) design is no longer the limit on the number of resources. Rather, the development of new methodologies and system-level design tools is the challenge that lies ahead, as these have become essential to keeping costs low in the planning and construction of these systems. Designers have realized that the consideration of the overwhelming details at register-transfer level (RTL) early in development restricts design space exploration, inhibits trade-off evaluation, and results in increased time-to-market. In order to effectively utilize the available resources, the entry point of design flows in recent methodologies is at higher levels of abstraction, with consideration to significantly fewer details of the final hardware implementation. In recent years, we have also seen the introduction of single-chip multiprocessors. As new tools and methodologies emerge for abstract system design, proposed solutions to the arising problems in the performance of single-chip multiprocessors can be implemented and evaluated more efficiently. For example, the amount of on-chip memory for such parallel systems continues to steadily rise, but so does the amount of power used by the memory system. In this work, we apply novel design methodology and tools to a single-chip multicore architecture, considering alternatives for power reduction of the storage components through system-level modeling.

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Ding, Guo Bao, Fushan Yao, Guangxu Ren, and Jie Yu. "Design of Electromagnetism Compatibility for Automatic Loading System." Applied Mechanics and Materials 496-500 (January 2014): 1273–76. http://dx.doi.org/10.4028/www.scientific.net/amm.496-500.1273.

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Based on the theory of electromagnetic compatibility, in view of the automatic loading control system, and carries on the EMC design, analyzed the sensitive circuit part of the principle and method of EMC design, mainly includes the power supply part, CPU control chip, the digital interface circuit and D/A conversion circuit protective measures.

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Ali Khan, Wajid, Yadollah Yamini, Mahroo Baharfar, and Muhammad Balal Arain. "A new microfluidic-chip device for selective and simultaneous extraction of drugs with various properties." New Journal of Chemistry 43, no. 24 (2019): 9689–95. http://dx.doi.org/10.1039/c9nj01104h.

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Oliver, John, Ravishankar Rao, Diana Franklin, Frederic T. Chong, and Venkatesh Akella. "Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications." Journal of Embedded Computing 2, no. 2 (2006): 157–66. https://doi.org/10.3233/emc-2006-00026.

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We present an overview of the Synchroscalar single-chip, multi-core processor. Through the design of Synchroscalar, we find that high energy efficiency and low complexity can be attained through parallelization. The importance of adequate inter-core interconnect is also demonstrated. We discuss the impact of having multiple frequency and voltage domains on chip to reduce the power consumption where parallelization fails. Finally, we investigate how the ad-hoc selection of tile size that is currently used in most single-chip multi-core processors impacts the power consumption of these architectures.

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Lin, Jing-Yuan, Yi-Chieh Hsu, and Yo-Da Lin. "A Low EMI DC-DC Buck Converter with a Triangular Spread-Spectrum Mechanism." Energies 13, no. 4 (2020): 856. http://dx.doi.org/10.3390/en13040856.

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In this paper, a triangular spread-spectrum mechanism is proposed to suppress the electromagnetic interference (EMI) of a DC-DC buck converter. The proposed triangular spread-spectrum mechanism, which is implemented in the chip, can avoid modifying the printed circuit board of switching regulators. In addition, a lower ripple of output voltage of switching regulators and a better system stability can be realized by the inductive DC resistance (DCR) current sensing circuit. The chip is fabricated by using TSMC 0.18-μm 1P6M CMOS technology. The chip area including PADs is 1.2 × 1.15 mm2. The input voltage range is 2.7~3.3 V and the output voltage is 1.8 V. The maximum load current is 700 mA. The off-chip inductor and capacitor are 3.3 μH and 10 μF, respectively. The experimental results demonstrate that the maximum spur of the proposed DC-DC buck converter with the triangular spread-spectrum mechanism improves to 14dBm. Moreover, the transient recovery time of step-up and step-down loads are both 5 μs. The measured maximum efficiency is 94% when the load current is 200 mA.

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Laurynenka, Viktoryia, Martha Carter, Sreeja Parameswaran, et al. "New role of Epstein-Barr virus in pathogenesis of acute and chronic lymphocytic leukemia." Journal of Immunology 202, no. 1_Supplement (2019): 197.11. http://dx.doi.org/10.4049/jimmunol.202.supp.197.11.

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Abstract Acute lymphoblastic leukemia (ALL) is the most common mortal cancer in children. Chronic lymphocytic leukemia (CLL) is the most prevalent form of adult leukemia in western countries. B lymphocytes dominate the origin of both diseases. We have found a possible role for Epstein-Barr virus (EBV) in the origins of both ALL and CLL. We applied our strategy (Nat Genet 50:699, 2018) to determine whether the binding of EBV transcription factors (TFs) was concentrate at the 84 known risk loci for CLL and 16 loci for ALL. We evaluated 52 virally encoded TF ChIP-seq (chromatin immunoprecipitation with DNA sequencing) datasets and complemented this analysis with the results from 1535 human TF ChIP-seq datasets. We found that Epstein-Barr nuclear antigen leader protein (EBNALP), EBNA3C and EBNA2 were concentrated in the CLL loci by 3.7, 3.7 and 3.5-fold with p=4.89*10−19, p=2.74*10−11 and p=1.07*10−8, respectively. The viral (n=3) and human TFs (n=40) cluster together in an optimal subset of ~15 of the 84 known loci in CLL at p&lt;10−6. Eighty percent of the most highly associated viral and human TF ChIP-seq datasets were collected from EBV transformed B cell lines in the Latency III program of viral expression, for which EBNALP, EBNA3C and EBNA2 are viral gene products. In ALL 3 of 16 loci were occupied by EBNA3ABC by a 17.7-fold enrichment with p=2.0*10−10. Among human TFs only c-MYC reached statistical significance binding 2 non-overlapping risk loci with 28.4-fold enrichment with p=2.9*10−10. These results nominate EBV for a role in the pathogenesis of CLL and ALL by a mechanism operating in transformed B cells through the EBV Latency III program of viral expression.

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Yang, Y., Z. Wang, Z. Cai, and T. Su. "Initial Designs of an on-Chip EMI Sensor Array." ECS Transactions 60, no. 1 (2014): 1209–14. http://dx.doi.org/10.1149/06001.1209ecst.

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Wong, K. L., and C. H. Chang. "Surface-Mountable EMC Monopole Chip Antenna for WLAN Operation." IEEE Transactions on Antennas and Propagation 54, no. 4 (2006): 1100–1104. http://dx.doi.org/10.1109/tap.2006.872589.

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Dias Rangel, Ryan M., and José C. da Costa. "RF CMOS Device Modelling for on Chip EMC Evaluation." ECS Transactions 4, no. 1 (2019): 265–74. http://dx.doi.org/10.1149/1.2813499.

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Wong, Kin-Lu, and Chih-Hwa Chang. "An EMC foam-base chip antenna for WLAN operation." Microwave and Optical Technology Letters 47, no. 1 (2005): 80–82. http://dx.doi.org/10.1002/mop.21087.

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Pan, Shing-Tai, Ching-Fa Chen, and Wen-Sin Tseng. "Efficient robust speech recognition with empirical mode decomposition using an FPGA chip with dual core." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 2 (2020): 109. http://dx.doi.org/10.11591/ijres.v9.i2.pp109-115.

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The purpose of this paper is to accelate the computing speed of Empirical Mode Decomposition (EMD) based on multi-core embedded systems for robust speech recognition. A reconfigurable chip, Field Programmable Gate Array (FPGA), is used for the implementation of the designed system. This paper applies EMD to discompose some noised speech signals into several Intrinsic Mode Functions (IMFs). These IMFs will be combined to recover the original speech by multiplying their corresponding weights which were trained by Genetic Algorithms (GA). After applying Empirical Mode Decomposition (EMD), we obtain a cleaner speech for recognition. Due to the complexity of the computation of the EMD, a dual-core architecture of embedded system on FPGA is proposed to accelerate the computing speed of EMD for robust speech recognition. This will enhance the efficiency of embedded speech recognition system.

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Shing-Tai, Pan, Chen Ching-Fa, and Tseng Wen-Sin. "Efficient robust speech recognition with empirical mode decomposition using an FPGA chip with dual core." International Journal of Reconfigurable and Embedded Systems 9, no. 2 (2020): 109–15. https://doi.org/10.11591/ijres.v9.i2.pp109-115.

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Tempera, Italo, Alessandra De Leo, Andrew V. Kossenkov, et al. "Identification ofMEF2B,EBF1, andIL6Ras Direct Gene Targets of Epstein-Barr Virus (EBV) Nuclear Antigen 1 Critical for EBV-Infected B-Lymphocyte Survival." Journal of Virology 90, no. 1 (2015): 345–55. http://dx.doi.org/10.1128/jvi.02318-15.

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ABSTRACTEpstein-Barr virus (EBV) nuclear antigen 1 (EBNA1) is the EBV-encoded nuclear antigen and sequence-specific DNA binding protein required for viral origin binding and episome maintenance during latency. EBNA1 can also bind to numerous sites in the cellular genome and can provide a host cell survival function, but it is not yet known how EBNA1 sequence-specific binding is responsible for host cell survival. Here, we integrate EBNA1 chromatin immunoprecipitation sequencing (ChIP-Seq) with transcriptome sequencing (RNA-Seq) after EBNA1 depletion to identify cellular genes directly regulated by EBNA1 that are also essential for B-cell survival. We first compared EBNA1 ChIP-Seq patterns in four different EBV-positive cell types, including Burkitt lymphoma (BL) cells, nasopharyngeal carcinoma (NPC) cells, and lymphoblastoid cell lines (LCLs). EBNA1 binds to ∼1,000 sites that are mostly invariant among cell types and share a consensus recognition motif. We found that a large subset of EBNA1 binding sites are located proximal to transcription start sites and correlate genome-wide with transcription activity. EBNA1 bound to genes of high significance for B-cell growth and function, includingMEF2B,IL6R, andEBF1. EBNA1 depletion from latently infected LCLs results in the loss of cell proliferation and the loss of gene expression for some EBNA1-bound genes, includingMEF2B,EBF1, andIL6R. Depletion of MEF2B, EBF1, or IL6R partially phenocopies EBNA1 depletion by decreasing the cell growth and viability of cells latently infected with EBV. These findings suggest that EBNA1 binds to a large cohort of cellular genes important for cell viability and implicates EBNA1 as a critical regulator of transcription of host cell genes important for enhanced survival of latently infected cells.IMPORTANCEEpstein-Barr virus (EBV) latent infection is responsible for a variety of lymphoid and epithelial cell malignancies. EBNA1 is the EBV-encoded nuclear antigen that is consistently expressed in all EBV-associated cancers. EBNA1 is known to provide a host cell survival function, but the mechanism is not known. EBNA1 is a sequence-specific binding protein important for viral genome maintenance during latency. Here, by integrating ChIP-Seq and RNA-Seq, we demonstrate that EBNA1 binds directly to the promoter regulatory regions and upregulates the transcription of host genes that are important for the survival of EBV-infected cells. Identification of EBNA1 target genes provides potential new targets for therapeutic intervention in EBV-associated disease.

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Li, Dejian, Bofu Li, Shunfeng Han, et al. "The Effect of BEOL Design Factors on the Thermal Reliability of Flip-Chip Chip-Scale Packaging." Micromachines 16, no. 2 (2025): 121. https://doi.org/10.3390/mi16020121.

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With the development of high-density integrated chips, low-k dielectric materials are used in the back end of line (BEOL) to reduce signal delay. However, due to the application of fine-pitch packages with high-hardness copper pillars, BEOL is susceptible to chip package interaction (CPI), which leads to reliability issues such as the delamination of interlayer dielectric (ILD) layers. In order to improve package reliability, the effect of CPI at multi-scale needs to be explored in terms of package integration. In this paper, the stress of BEOL in the flip-chip chip-scale packaging (FCCSP) model during thermal cycling is investigated by using the finite-element-based sub-model approach. A three-dimensional (3D) multi-level finite element model is established based on the FCCSP. The wiring layers were treated by the equivalent homogenization method to ensure high prediction accuracy. The stress distribution of the BEOL around the critical bump was analyzed. The cracking risk of the interface layer of the BEOL was assessed by pre-cracking at a dangerous location. In addition, the effects of the epoxy molding compound (EMC) thickness, polyimide (PI) opening, and coefficient of thermal expansion (CTE) of the underfill on cracking were investigated. The simulation results show that the first principal stress of BEOL is higher at high-temperature moments than at low-temperature moments, and mainly concentrated near the PI opening. Compared with the oxide layer, the low-k layer has a higher risk of cracking. A smaller EMC thickness, lower CTE of the underfill, and larger PI opening help to reduce the risk of cracking in the BEOL.

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Settle, Alex, Dan Connors, Enric Gibert, and Antonio González. "A dynamically reconfigurable cache for multithreaded processors." Journal of Embedded Computing 2, no. 2 (2006): 221–33. https://doi.org/10.3233/emc-2006-00027.

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Chip multi-processors (CMP) are rapidly emerging as an important design paradigm for both high performance and embedded processors. These machines provide an important performance alternative to increasing the clock frequency. In spite of the increase in potential performance, several issues related to resource sharing on the chip can negatively impact the performance of embedded applications. In particular, the shared on-chip caches make each job's memory access times dependent on the behavior of the other jobs sharing the cache. If not adequately managed, this can lead to problems in meeting hard real-time scheduling constraints. This work explores adaptable caching strategies which balance the resource demands of each application and in turn lead to improvements in throughput for the collective workload. Experimental results demonstrate speedups of up to 1.47X for workloads of two co-scheduled applications compared against a fully-shared two-level cache hierarchy. Additionally, the adaptable caching scheme is shown to achieve an average speedup of 1.10X over the leading cache partitioning model. By dynamically managing cache storage for multiple application threads at runtime, sizable performance levels are achieved, which provides chip designers the opportunity to maintain high performance as cache size and power budgets become a concern in the CMP design space.

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Chau, Charles M., Xiao-Yong Zhang, Steven B. McMahon, and Paul M. Lieberman. "Regulation of Epstein-Barr Virus Latency Type by the Chromatin Boundary Factor CTCF." Journal of Virology 80, no. 12 (2006): 5723–32. http://dx.doi.org/10.1128/jvi.00025-06.

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ABSTRACT Epstein Barr virus (EBV) can establish distinct latency types with different growth-transforming properties. Type I latency and type III latency can be distinguished by the expression of EBNA2, which has been shown to be regulated, in part, by the EBNA1-dependent enhancer activity of the origin of replication (OriP). Here, we report that CTCF, a chromatin boundary factor with well-established enhancer-blocking activity, binds to EBV sequences between the OriP and the RBP-Jκ response elements of the C promoter (Cp) and regulates transcription levels of EBNA2 mRNA. Using DNA affinity, electrophoretic mobility shift assay, DNase I footprinting, and chromatin immunoprecipitation (ChIP), we found that CTCF binds both in vitro and in vivo to the EBV genome between OriP and Cp, with an ∼50-bp footprint at EBV coordinates 10515 to 10560. Deletion of this CTCF binding site in a recombinant EBV bacterial artificial chromosome (BAC) increased EBNA2 transcription by 3.5-fold compared to a wild-type EBV BAC. DNA affinity and ChIP showed more CTCF binding at this site in type I latency cell lines (MutuI and KemI) than in type III latency cell lines (LCL3456 and Raji). CTCF protein and mRNA expression levels were higher in type I than type III cell lines. Short interfering RNA depletion of CTCF in type I MutuI cells stimulated EBNA2 mRNA levels, while overexpression of CTCF in type III Raji cells inhibited EBNA2 mRNA levels. These results indicate that increased CTCF can repress EBNA2 transcription. We also show that c-MYC, as well as EBNA2, can stimulate CTCF mRNA levels, suggesting that CTCF levels may contribute to B-cell differentiation as well as EBV latency type determination.

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Bartolini, Sandro, and Roberto Giorgi. "Issues in Embedded Single-Chip Multicore Architectures." Journal of Embedded Computing 2, no. 2 (2006): 137–39. https://doi.org/10.3233/emc-2006-00022.

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Vanwassenhove, Luc. "Low‐cost fibre‐chip coupling for electro‐optic EMC‐probes." Microelectronics International 15, no. 1 (1998): 32–34. http://dx.doi.org/10.1108/13565369810199095.

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Kim, Tae-Eun, Seok-Won Park, Nam-Yun Cho, et al. "Quantitative measurement of serum allergen-specific IgE on protein chip." Experimental & Molecular Medicine 34, no. 2 (2002): 152–58. http://dx.doi.org/10.1038/emm.2002.22.

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Gu, Pei, and Uzi Vishkin. "Case study of gate-level logic simulation on an extremely fine-grained chip multiprocessor." Journal of Embedded Computing 2, no. 2 (2006): 181–90. https://doi.org/10.3233/emc-2006-00031.

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Explicit-multi-threading (XMT) is a parallel programming approach for exploiting on-chip parallelism. Its fine-grained single program multiple data (SPMD) programming model is suitable for many computing intensive applications. In this paper, we present a parallel gate level logic simulator implemented on an XMT platform and study its performance. Test results show potential for achieving more than a hundred-fold speedup over a serial implementation. This indicates an interesting possibility for a certain type of a single chip multicore architecture: use an existing easy-to-program API, such as VHDL or Verilog, for reduced application-software development time and better performance over serial performance-driven languages, such as C.

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KUROKAWA, A., H. FUJITA, and T. IBE. "Prevention in a Chip of EMI Noise Caused by X'tal Oscillator." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91-A, no. 4 (2008): 1077–83. http://dx.doi.org/10.1093/ietfec/e91-a.4.1077.

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Shang, Xinchao, Weiwei Shan, and Xinning Liu. "Design and Implementation of a Reconfigurable Cryptographic Coprocessor with Multiple Side-Channel Attacks Countermeasures." Journal of Circuits, Systems and Computers 27, no. 11 (2018): 1850180. http://dx.doi.org/10.1142/s0218126618501803.

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Nowadays, countermeasures against side-channel attack (SCA) have become necessary in hardware security. And the need for supporting multiple crypto algorithms on a chip is increasing. We propose a reconfigurable crypto coprocessor, which not only supports multiple crypto algorithms, but also provides multiple effective SCA countermeasures of SPA, DPA and EMA, by making use of its own reconfigurable features other than using extra resources. The countermeasure methods include several global and encryption flow related countermeasures, which can also be reconfigured along with the circuit function. This coprocessor is a coarse-grained reconfigurable architecture composed of several reconfigurable modules, such as logic arithmetic, shift, modular ADD/Substrate, permutation, S-box and modular multiplication units, all of which are reconfigurable. This reconfigurable cryptographic coprocessor is integrated into a system-on chip with a 32-bit CPU and fabricated in 0.18 m CMOS process with 1.8[Formula: see text]V supply and 100 MHz maximum frequency. Experimental results show that it can successfully resist SPA and DPA with one million power traces. As for EMA, if we use full countermeasures, it can resist EMA with up to 1.2 million electromagnetic traces without revealing the right subkey. Thus, this reconfigurable coprocessor can provide a good solution for both supporting multiple algorithms and providing SCA resistance, with no frequency influence, neglectable area overhead and small power overhead.

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Li, Liang, Yifan Xiao, Weiqi Wang, et al. "Advanced Fabrication of 56 Gbaud Electro-Absorption Modulated Laser (EML) Chips Integrated with High-Speed Silicon Photonic Substrates." Photonics 12, no. 4 (2025): 329. https://doi.org/10.3390/photonics12040329.

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With the rapid growth of data center demand driven by AI, high-speed optical modules (such as 800G and 1.6T) have become critical components. Traditional 800G modules face issues such as complex processes and large sizes due to the separate packaging of EML chips, AlN substrates, and capacitors. This study proposes a high-speed EML module based on silicon integration, where resistors, capacitors, and AuSn soldering areas are integrated onto the silicon substrate, enabling the bonding of the EML chip, reducing packaging costs, and enhancing scalability. Key achievements include: the development of a 100G EML chip; the fabrication of a high-speed silicon integrated carrier; successful Chip-on-Carrier (COC) packaging and testing, with a laser output power of 10 mW, extinction ratio of 10 dB, and bandwidth greater than 40 GHz; and reliability verified through 500 h of aging tests. This study provides an expandable solution for next-generation high-speed optical interconnects.

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Lee, Suman, Hyun Suk Joo, Sook-Hwan Lee, et al. "Application of DNA chip techniques for Yq microdeletion analysis in infertile males." Experimental & Molecular Medicine 36, no. 2 (2004): 179–84. http://dx.doi.org/10.1038/emm.2004.25.

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Shim, Joong Sup, Hae Kwang Lee, Hyo Mi Park, et al. "Development of an angiogenesis-focused cDNA chip and validation of its functionality." Experimental & Molecular Medicine 37, no. 4 (2005): 365–70. http://dx.doi.org/10.1038/emm.2005.46.

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Countryman, Jill K., Lyndle Gradoville, and George Miller. "Histone Hyperacetylation Occurs on Promoters of Lytic Cycle Regulatory Genes in Epstein-Barr Virus-Infected Cell Lines Which Are Refractory to Disruption of Latency by Histone Deacetylase Inhibitors." Journal of Virology 82, no. 10 (2008): 4706–19. http://dx.doi.org/10.1128/jvi.00116-08.

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ABSTRACT Activation of the Epstein-Barr virus (EBV) lytic cycle is mediated through the combined actions of ZEBRA and Rta, the products of the viral BZLF1 and BRLF1 genes. During latency, these two genes are tightly repressed. Histone deacetylase inhibitors (HDACi) can activate viral lytic gene expression. Therefore, a widely held hypothesis is that Zp and Rp, the promoters for BZLF1 and BRLF1, are repressed by chromatin and that hyperacetylation of histone tails, by allowing the access of positively acting factors, leads to transcription of BZLF1 and BRLF1. To investigate this hypothesis, we used chromatin immunoprecipitation (ChIP) to examine the acetylation and phosphorylation states of histones H3 and H4 on Zp and Rp in three cell lines, Raji, B95-8, and HH514-16, which differ in their response to EBV lytic induction by HDACi. We studied the effects of three HDACi, sodium butyrate (NaB), trichostatin A (TSA), and valproic acid (VPA). We also examined the effects of tetradecanoyl phorbol acetate (TPA) and 5-aza-2′-deoxycytidine, a DNA methyltransferase inhibitor, on histone modification. In Raji cells, TPA and NaB act synergistically to activate the EBV lytic cycle and promote an increase in histone H3 and H4 acetylation and phosphorylation at Zp and Rp. Surprisingly, however, when Raji cells were treated with NaB or TSA, neither of which is sufficient to activate the lytic cycle, an increase of comparable magnitude of hyperacetylated and phosphorylated histone H3 at Zp and Rp was observed. In B95-8 cells, NaB inhibited lytic induction by TPA, yet NaB promoted hyperacetylation of H3 and H4. In HH514-16 cells, NaB and TSA strongly activated the EBV lytic cycle and caused hyperacetylation of histone H3 on Zp and Rp. However, when HH514-16 cells were treated with VPA, lytic cycle mRNAs or proteins were not induced, although histone H3 was hyperacetylated as measured by immunoblotting or by ChIP on Zp and Rp. Taken together, our data suggest that open chromatin at EBV BZLF1 and BRLF1 promoters is not sufficient to activate EBV lytic cycle gene expression.

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Barkalov, Alexandr, Larysa Titarenko, Oleksandr Golovin, and Oleksandr Matvienko. "Address Translation in a Compositional Microprogram Control Unit." Cybernetics and Computer Technologies, no. 2 (June 6, 2025): 88–100. https://doi.org/10.34229/2707-451x.25.2.8.

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Introduction. Digital systems consist of combinational and sequential blocks. The most important sequential blocks include control units. Control unit circuits are not typical library components of CAD systems. Due to it, the designing a control unit circuit is a more labor-intensive process than implementing systems with such common blocks as registers, counters, arithmetic and logic blocks. The purpose of the article. When implementing digital systems, problems arise in optimizing their characteristics. This paper considers the problem of reducing hardware costs in the circuits of compositional microprogram control units (CMCU). The resources of FPGA (field-programmable logic array) chips are used as an element basis. The method proposed in the article is based on the adaptation of algorithms for optimizing microprogram automata circuits to the features of CMCUs. The method is aimed at converting the addresses of some microinstructions into partial inputs. Under certain conditions, this approach can significantly simplify the block of microinstruction addressing. This approach can improve the characteristics of the CMCU circuit in comparison with other known methods. The language of graph-schemes of algorithms (GSA) is used to specify the algorithm for the CMCU operating. Results. The implementation of the CMCU circuit using such FPGA chip resources as look-up table (LUT) elements and embedded memory blocks (EMB) is considered. Optimization is achieved by using the EMB redundancy at the outputs. The proposed method allows improving such basic CMCU characteristics as the chip area occupied by the CMCU circuit, the maximum operating frequency, the total number of interconnections and the power consumption. The article presents a step-by-step algorithm for synthesizing the CMCU for a given GSA. Also, it provides an example of CMCU synthesis using the proposed method. At last, the conditions of the proposed method’s applicability are shown. Conclusions. The proposed method allows reducing the number of LUT elements in the CMCU addressing circuit. This minimization does not require any additional FPGA chip resources. Reducing the number of LUT elements is achieved by using the redundancy of the EMB block outputs. Keywords: CMCU, LUT, EMB, operator linear chains.

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MASUNAGA, Naoki, Koichi ISHIDA, Takayasu SAKURAI, and Makoto TAKAMIYA. "EMI Camera LSI (EMcam) with On-Chip Loop Antenna Matrix to Measure EMI Noise Spectrum and Distribution." IEICE Transactions on Electronics E95.C, no. 6 (2012): 1059–66. http://dx.doi.org/10.1587/transele.e95.c.1059.

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Lau, John, Ming Li, Nelson Fan, et al. "Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution-Layers (RDLs)." International Symposium on Microelectronics 2017, no. 1 (2017): 000576–83. http://dx.doi.org/10.4071/isom-2017-tha35_056.

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Abstract This study is for fan-out wafer-level packaging (FOWLP) with chip-first (die face-up) formation. The chips with Cu contact-pads on the front-side and a die attach film (DAF) on the backside are picked and placed face-up on a temporary glass wafer carrier with a thin layer of light-to-heat conversion (LTHC) material. It is followed by compression molding with epoxy molding compound (EMC) and post mold cure (PMC) on the reconstituted wafer carrier, and then backgrinding the molded EMC to expose the Cu contact-pads of the chips. The next step is to build up the redistribution layers (RDLs) from the Cu contact-pads and then mount the solder balls. Next comes the de-bonding of the carrier with a laser, and then the dicing of the whole reconstituted wafer into individual packages. A 300mm reconstituted wafer with a package/die ratio = 1.8 and a die-top EMC cap = 100μm has also been fabricated (a total of 325 test packages on the reconstituted wafer.) This test package has three RDLs; the line width/spacing of the first RDL is 5μm/5μm, of the second RDL is 10μm/10μm, and of the third RDL is 15μm/15μm. The dielectric layer of the RDLs is fabricated with a photosensitive polyimide (PI) and the conductor layer of the RDLs is fabricated by electrochemical Cu deposition (ECD).

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Mazlan, Mohamed, A. Rahim, M. A. Iqbal, Mohd Mustafa Al Bakri Abdullah, W. Razak, and M. R. Mohd Sukhairi. "The Comparison between Four PLCC Packages and Eight PLCC Packages in Personal Computer (PC) Using Computational Fluid Dynamic (CFD), FLUENT Software^TM Using Epoxy Moulding Compound Material (EMC)." Advanced Materials Research 795 (September 2013): 174–81. http://dx.doi.org/10.4028/www.scientific.net/amr.795.174.

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The paper present the three dimensional numerical analysis of heat and fluid flow through Plastic Leaded Chip Carrier (PLCC) packages in inline orientation horizontally mounted on a printed circuit board in a wind tunnel is carried out using a commercial CFD code, FLUENTTM by using Epoxy Moulding Compound (EMC) as a main material. The study was made for four and eight packages with different Reynolds Number and package chip powers. The results are presented in term of junction temperature for four and eight PLCC package under different conditions. It is observed the chip temperatures of eight PLCC packages have higher junction temperature compare to four PLCC packages due to effect of other PLCC because of space and gap between PLCC that have more number of PLCC is smaller. Hence it makes junction temperature of eight PLCC higher compare to four PLCC packages. Moreover, the junction temperature of the packages decreases with increase in Reynolds Number.

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Lin, Han-Nien, Ya-Ying Chen, Hung-Yun Tsai, and Min-Shan Lin. "Characteristic Analysis and Applications of Electromagnetic Shielding Materials for Wireless Communications Device." Open Materials Science Journal 10, no. 1 (2016): 44–53. http://dx.doi.org/10.2174/1874088x01610010044.

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As the trend of consumer electronics and mobile communications devices is obviously developing toward to miniature and high-speed processing, the problem involving with electromagnetic compatibility (EMC) or radio frequency interference (RFI) is becoming more critical for the system integration of high-speed digital and RF mixed signal platforms. This paper is mainly focusing on the characteristics analysis of various electromagnetic shielding materials by utilizing the various shielding effectiveness (SE) measuring methods developed by TDK and ASTM (ASTM D4935). We also adopt the electromagnetic interference (EMI) testing methods developed by IEC for chip level (IEC 61967-3 and IEC 61967-6) to investigate the characteristics and distribution of EMI noise sources. To effectively shield the electric, magnetic, or electromagnetic field originated from noise source, we thus analyze the shielding capability for various materials with different measuring methods. Finally, we will show the EMI reduction and RF performance improvement with implementation of shielding material on module under investigated. With the systematic measurement and analysis described in this paper, we can further identify the related EMI problem and resolve the severe chip or module level EMC problem more effectively.

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