Dissertations / Theses on the topic 'Encoder-decoder'
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Kalchbrenner, Nal. "Encoder-decoder neural networks." Thesis, University of Oxford, 2017. http://ora.ox.ac.uk/objects/uuid:d56e48db-008b-4814-bd82-a5d612000de9.
Full textPadinjare, Sainath. "VLSI implementation of a turbo encoder/decoder /." Internet access available to MUN users only, 2003. http://collections.mun.ca/u?/theses,162832.
Full textWeitzman, Jonathan M. "SELECTABLE PERMUTATION ENCODER/DECODER FOR A QPSK MODEM." International Foundation for Telemetering, 2003. http://hdl.handle.net/10150/605817.
Full textAn artifact of QPSK modems is ambiguity of the recovered data. There are four variations of the output data for a given input data stream. All are equally probable. To resolve this ambiguity, the QPSK data streams can be differentially encoded before modulation and differentially decoded after demodulation. The encoder maps each input data pair to a phase angle change of the QPSK carrier. In the demodulator, the inverse is performed - each phase change of the input QPSK carrier is mapped to an output data pair. This paper discusses a very simple and unique differential encoder/decoder that handles all possible data pair/phase change permutations.
Mejdi, Sami. "Encoder-Decoder Networks for Cloud Resource Consumption Forecasting." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-291546.
Full textÖverflödig allokering av resurser I telekommunikationsnätverk kan förhindras genom att prognosera resursbehoven vid dimensionering av dessa nätverk. Detta görs i syfte att bidra till en mer hållbar utveckling. Inför detta prjekt har trafikdata från molnmiljön som hyser aktiva virtuella komponenter (VNFs) till ett IÅ Multimedia Subsystem (IMS) samlats in tillsammans med resursförbrukningen av dessa komponenter. Detta examensarbete avhandlar hur effektivt övervakad maskininlärning i form av encoder-decoder nätverk kan användas för att prognosera resursbehovet hos ovan nämnda VNFs. Encoder-decoder nätverken appliceras genom att betrakta den samlade datan som en tidsserie. Problemet med att förutspå utvecklingen av tidsserien formuleras sedan som ett sequence-2-sequence (seq2seq) problem. I detta arbete användes en samling encoder-decoder nätverk med olika arkitekturer för att prognosera resursförbrukningen och dessa jämfördes med en populär modell hämtad från klassisk tidsserieanalys. Resultaten visar att encoder-decoder nätverken misslyckades med att överträffa den klassiska tidsseriemodellen med avseende på Root Mean Squeared Error (RMSE) och Mean Absolut Error (MAE). Dock visar encoder-decoder nätverken en betydlig motståndskraft mot prestandaförfall över tid i jämförelse med den klassiska tidsseriemodellen. Detta indikerar att encoder-decoder nätverk är lämpliga för prognosering över en längre tidshorisont. Utöver detta visade encoder-decoder nätverken en konkurrenskraftig förmåga att förutspå det korrekta resursbehovet, trots en begränsad justering av disponeringsparametrarna och utan mer sofistikerad funktionalitet implementerad som exempelvis attention.
Mejdi, Sami. "Encoder-Decoder Networks for Cloud Resource Consumption Forecasting." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-294066.
Full textÖverflödig allokering av resurser i telekommunikationsnätverk kan förhindras genom att prognosera resursbehoven vid dimensionering av dessa nätverk. Detta görs i syfte att bidra till en mer hållbar utveckling. Infor detta projekt har trafikdata från molnmiljon som hyser aktiva virtuella komponenter (VNFs) till ett IP Multimedia Subsystem (IMS) samlats in tillsammans med resursförbrukningen av dessa komponenter. Detta examensarbete avhandlar hur effektivt övervakad maskininlärning i form av encoder-decoder natverk kan användas för att prognosera resursbehovet hos ovan nämnda VNFs. Encoder-decoder nätverken appliceras genom att betrakta den samlade datan som en tidsserie. Problemet med att förutspå utvecklingen av tidsserien formuleras sedan som ett sequence-to-sequence (seq2seq) problem. I detta arbete användes en samling encoder-decoder nätverk med olika arkitekturer for att prognosera resursförbrukningen och dessa jämfördes med en populär modell hämtad från klassisk tidsserieanalys. Resultaten visar att encoder- decoder nätverken misslyckades med att överträffa den klassiska tidsseriemodellen med avseende på Root Mean Squared Error (RMSE) och Mean Absolute Error (MAE). Dock visade encoder-decoder nätverken en betydlig motståndskraft mot prestandaförfall över tid i jämförelse med den klassiska tidsseriemodellen. Detta indikerar att encoder-decoder nätverk är lämpliga för prognosering över en längre tidshorisont. Utöver detta visade encoder-decoder nätverken en konkurrenskraftig förmåga att förutspå det korrekta resursbehovet, trots en begränsad justering av disponeringsparametrarna och utan mer sofistikerad funktionalitet implementerad som exempelvis attention.
Correia, Tiago Miguel Pina. "FPGA implementation of Alamouti encoder/decoder for LTE." Master's thesis, Universidade de Aveiro, 2013. http://hdl.handle.net/10773/12679.
Full textMotivados por transmissões mais rápidas e mais fiáveis num canal sem fios, os sistemas da 4G devem proporcionar processamento de dados mais rápido a baixa complexidade, elevadas taxas de dados, assim como robustez na performance reduzindo também, a latência e os custos de operação. LTE apresenta, na sua camada física, tecnologias como OFDM e MIMO que prometem alcançar elevadas taxas de dados e aumentar a eficiência espectral. Especificamente a camada física do LTE emprega OFDMA para downlink e SC-FDMA para uplink. A tecnologia MIMO permite também melhorar significativamente o desempenho dos sistemas OFDM com as vantagens de multiplexação e diversidade espacial diminuindo o efeito de desvanecimento de multi-percurso no canal. Nesta dissertação são implementados um codificador e um descodificador com base no algoritimo de Alamouti num sistema MISO nomeadamente para serem incluídos num OFDM transceiver que segue as especificações da camada física do LTE. A codificação/descodificação de Alamouti realiza-se no espaço e frequência e os blocos foram projetados e simulados em Matlab através do ambiente Simulink com o auxílio dos blocos da Xilinx inseridos no seu software System Generator para DSP. Pode-se concluir que os blocos baseados no algoritmo de Alamouti foram implementados em hardware com sucesso.
Motivated by faster transmissions and more reliable wireless channel, future 4G systems should provide faster data processing at low complexity, high data rates, as well as robustness in performance while also reducing the latency and operating costs. LTE presents in its physical layer technologies such as OFDM and MIMO that promise to achieve high data rates and increase spectral efficiency. Specifically the physical layer of LTE employs OFDMA on the downlink and SC-FDMA for uplink. MIMO technology also allows to significantly improve the performance of OFDM systems with the advantages of multiplexing and spatial diversity by decreasing the effect of multipath fading in the channel. In this thesis we implemented an encoder and a decoder based on an Alamouti algorithm in a MISO system namely to be added to an OFDM transceiver that follows closely the LTE physical layer specifications. Alamouti coding/decoding is performed in frequency and space and the blocks were projected and simulated in Matlab using Simulink environment through the Xilink's blocks in the System Generator for DSP. One can conclude that the blocks based on Alamouti algorithm were well-implemented.
Leivas, Oliveira Gabriel [Verfasser], Thomas [Akademischer Betreuer] Brox, and Wolfram [Akademischer Betreuer] Burgard. "Encoder-decoder methods for semantic segmentation: efficiency and robustness aspects." Freiburg : Universität, 2019. http://d-nb.info/1191689476/34.
Full textKopparthi, Sunitha. "Flexible encoder and decoder designs for low-density parity-check codes." Diss., Manhattan, Kan. : Kansas State University, 2010. http://hdl.handle.net/2097/4190.
Full textPisacane, Claudia. "Skopos Theory La figura del traduttore come decoder e re-encoder." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2015. http://amslaurea.unibo.it/8926/.
Full textNina, Oliver A. Nina. "A Multitask Learning Encoder-N-Decoder Framework for Movie and Video Description." The Ohio State University, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=osu1531996548147165.
Full textSari, Mehmet. "Designing fast Golay encoder/decoder in Xilinx XACT with Mentor Graphics CAD interface." Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1997. http://handle.dtic.mil/100.2/ADA331926.
Full textKumbala, Bharadwaj Reddy. "Predictive Maintenance of NOx Sensor using Deep Learning : Time series prediction with encoder-decoder LSTM." Thesis, Blekinge Tekniska Högskola, Institutionen för tillämpad signalbehandling, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-18668.
Full textSozen, Serkan. "A Viterbi Decoder Using System C For Area Efficient Vlsi Implementation." Master's thesis, METU, 2006. http://etd.lib.metu.edu.tr/upload/12607567/index.pdf.
Full textFerreira, Nathan. "An Assessment of Available Software Defined Radio Platforms Utilizing Iterative Algorithms." Digital WPI, 2015. https://digitalcommons.wpi.edu/etd-theses/728.
Full textRajan, Rachel. "Semi Supervised Learning for Accurate Segmentation of Roughly Labeled Data." University of Dayton / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1597082270750151.
Full textGrúbel, Michal. "Implementace metriky pro hodnocení kvality videosekvencí do dekodéru H.264/AVC." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2010. http://www.nusl.cz/ntk/nusl-218404.
Full textZhao, Chenyuan. "Spike Processing Circuit Design for Neuromorphic Computing." Diss., Virginia Tech, 2019. http://hdl.handle.net/10919/93591.
Full textDoctor of Philosophy
Neuromorphic computing is a kind of specific electronic system that could mimic biological bodies’ behavior. In most cases, neuromorphic computing system is built with analog circuits which have benefits in power efficient and low thermal radiation. Among neuromorphic computing system, one of the most important components is the signal processing interface, i.e. encoder/decoder. To increase the whole system’s performance, novel encoders and decoders have been proposed in this dissertation. In this dissertation, three kinds of temporal encoders, one rate encoder, one latency encoder, one temporal decoder, and one general spike decoder have been proposed. These designs could be combined together to build high efficient spike-based data link which guarantee the processing performance of whole neuromorphic computing system.
Ploštica, Stanislav. "Turbo kódy a jejich aplikace." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-218201.
Full textÖjerteg, Theo. "Design and implementation of test a tool for the GSM traffic channel." Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1240.
Full textTodays’ systems for telecommunication are getting more and more complex. Automatic testing is required to guarantee quality of the systems produced. An actual example is the introduction of GPRS traffic in the GSM network nodes. This thesis investigates the need and demands for such an automatic testing of the traffic channels in the GSM system. A solution intended to be a part of the Ericsson TSS is proposed. One problem to be solved is that today’s tools for testing do not support testing of speech channels with the speech transcoder unit installed. As part of the investigation, a speech codec is implemented for execution on current hardware used in the test platform. The selected speech codec is the enhanced full rate codec, generating a bitstream of 12.2 kbit/s, and gives a good trade-off between compression and speech quality. The report covers the design of the test tool and the implementation of speech codec. Particularly performance problems in the implementation of the encoder will be addressed.
Monsen, Julius. "Building high-quality datasets for abstractive text summarization : A filtering‐based method applied on Swedish news articles." Thesis, Linköpings universitet, Institutionen för datavetenskap, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-176352.
Full textLarsson, Susanna. "Monocular Depth Estimation Using Deep Convolutional Neural Networks." Thesis, Linköpings universitet, Datorseende, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-159981.
Full textHolcner, Jonáš. "Strojový překlad pomocí umělých neuronových sítí." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2018. http://www.nusl.cz/ntk/nusl-386020.
Full textRanalli, Lorenzo. "Studio ed implementazione di un modello di Action Recognition. Classificazione delle azioni di gioco e della tipologia di colpi durante un match di Tennis." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021.
Find full textNěmec, Jaroslav. "Bezeztrátová komprese videa." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2012. http://www.nusl.cz/ntk/nusl-236537.
Full textNawaz, Sabeen. "Analysis of Transactional Data with Long Short-Term Memory Recurrent Neural Networks." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-281282.
Full textObehöriga transaktioner och bedrägerier i betalningar kan leda till stora ekonomiska förluster för banker och myndigheter. Inom maskininlärning har detta problem tidigare hanterats med hjälp av klassifierare via supervised learning. I detta examensarbete föreslår vi en modell som kan användas i ett system för att upptäcka bedrägerier. Modellen appliceras på omärkt data med många olika variabler. Modellen som används är en Long Short-term memory i en auto-encoder decoder nätverk. Datan transformeras med PCA och klustras med K-means. Modellen tränas till att rekonstruera en sekvens av betalningar med hög noggrannhet. Vår resultat visar att LSTM-AED presterar bättre än en modell som endast gissar nästa punkt i sekvensen. Resultatet visar också att mycket information i datan går förlorad när den förbehandlas och transformeras.
Daliparthi, Venkata Satya Sai Ajay. "Semantic Segmentation of Urban Scene Images Using Recurrent Neural Networks." Thesis, Blekinge Tekniska Högskola, Institutionen för datavetenskap, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-20651.
Full textNishikimi, Ryo. "Generative, Discriminative, and Hybrid Approaches to Audio-to-Score Automatic Singing Transcription." Doctoral thesis, Kyoto University, 2021. http://hdl.handle.net/2433/263772.
Full textŠedý, Jakub. "Turbo konvoluční a turbo blokové kódy." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219287.
Full textZávorka, Radek. "Program pro demonstraci kanálového kódování." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-413009.
Full textKašpar, Jaroslav. "Zabezpečení přenosu dat BCH kódy." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217733.
Full textLindblad, Maria. "A Comparative Study of the Quality between Formality Style Transfer of Sentences in Swedish and English, leveraging the BERT model." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-299932.
Full textÖverföring av formalitetsstil syftar på uppgiften att automatiskt omvandla ett stycke text från en nivå av formalitet till en annan. Tidigare forskning har undersökt olika metoder för att utföra uppgiften på engelsk text men vid tiden för detta projekt fanns det enligt författarens vetskap inga tidigare studier som analyserat kvaliteten för överföring av formalitetsstil på svensk text. Syftet med detta arbete var att undersöka hur en modell tränad för överföring av formalitetsstil på svensk text presterar. Detta gjordes genom att jämföra kvaliteten på en modell tränad för överföring av formalitetsstil på svensk text, med en motsvarande modell tränad på engelsk text. Båda modellerna implementerades som kodnings-avkodningsmodeller, vars vikter initierats med hjälp av två befintliga Bidirectional Encoder Representations from Transformers (BERT)-modeller, förtränade på svensk respektive engelsk text. De två modellerna finjusterades för omvandling både från informell stil till formell och från formell stil till informell. Under finjusteringen användes en svensk och en engelsk version av korpusen Grammarly’s Yahoo Answers Formality Corpus (GYAFC). Den svenska versionen av GYAFC skapades genom automatisk maskinöversättning av den ursprungliga engelska versionen. Den svenska korpusen utvärderades sedan med hjälp av de tre kriterierna betydelse-bevarande, formalitets-bevarande och flödes-bevarande. Resultaten från studien indikerade att den svenska modellen hade kapaciteten att matcha kvaliteten på den engelska modellen men hölls tillbaka av den svenska korpusens sämre kvalitet. Studien underströk också behovet av uppgiftsspecifika korpusar på svenska.
Špaček, Milan. "Porovnání možností komprese multimediálních signálů." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-220319.
Full textHardy, Clément. "Architectures multi-échelles de type encοdeur-décοdeur pοur la stéréοphοtοmétrie." Electronic Thesis or Diss., Normandie, 2024. http://www.theses.fr/2024NORMC222.
Full textPhotometric stereo is a technique for 3D surface reconstruction of objects. This field has seen a surge in research interest due to its potential applications in industry. Specifically, photometric stereo can be employed for tasks such as detecting machining defects in mechanical components or facial recognition. This thesis delves into deep learning methods for photometry stero, with a particular focus on training data and network architectures.While neural network over-parameterization is often adequate, the training dataset plays a pivotal role in task adaptation. To generate a highly diverse and extensible training set, we propose a new synthetic dataset. This dataset incorporates a broad spectrum of geometric, textural, lighting, and environmental variations, allowing for the creation of nearly infinite training instances.The second decisive point of a good reconstruction concerns the choice of architecture. The architecture of a network must ensure a good generalization capacity on new data to generate very good results on unseen data. And this, regardless of the application. In particular, for the photometric stereo problem, the challenge is to be able to reconstruct very high-resolution images in order not to lose any details. We therefore propose a multi-scale encoder-decoder architecture to address this problem.We first introduce a convolutional neural network architecture for calibrated photometric stereo, where the lighting direction is known. To handle unconstrained environments, we propose a Transformers-based approach for universal photometric stereo. Lastly, for challenging materials shiny like translucent or shiny surfaces, we introduce a ``weakly calibrated'' approach that assumes only approximate knowledge of the lighting direction.The approaches we have investigated have consistently demonstrated strong performance on standard benchmarks, as evidenced by both quantitative metrics and visual assessments. Our results, particularly the improved accuracy of reconstructed normal maps, represent a significant advancement in photometric stereo
Trčka, Tomáš. "Turbokódy a jejich použití ve sdělovacích systémech." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217561.
Full textNilsson, Mårten. "Augmenting High-Dimensional Data with Deep Generative Models." Thesis, KTH, Robotik, perception och lärande, RPL, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-233969.
Full textDataaugmentering är en teknik som kan utföras på flera sätt för att förbättra träningen av diskriminativa modeller. De senaste framgångarna inom djupa generativa modeller har öppnat upp nya sätt att augmentera existerande dataset. I detta arbete har ett ramverk för augmentering av annoterade dataset med hjälp av djupa generativa modeller föreslagits. Utöver detta så har en metod för kvantitativ evaulering av kvaliteten hos genererade data set tagits fram. Med hjälp av detta ramverk har två dataset för pupillokalisering genererats med olika generativa modeller. Både väletablerade modeller och en ny modell utvecklad för detta syfte har testats. Den unika modellen visades både kvalitativt och kvantitativt att den genererade de bästa dataseten. Ett antal mindre experiment på standardiserade dataset visade exempel på fall där denna generativa modell kunde förbättra prestandan hos en existerande diskriminativ modell. Resultaten indikerar att generativa modeller kan användas för att augmentera eller ersätta existerande dataset vid träning av diskriminativa modeller.
Djikic, Addi. "Segmentation and Depth Estimation of Urban Road Using Monocular Camera and Convolutional Neural Networks." Thesis, KTH, Robotik, perception och lärande, RPL, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-235496.
Full textDeep learning för säkra autonoma transportsystem framträder mer och mer inom forskning och utveckling. Snabb och robust uppfattning om miljön för autonoma fordon kommer att vara avgörande för framtida navigering inom stadsområden med stor trafiksampel. I denna avhandling härleder vi en ny form av ett neuralt nätverk som vi kallar AutoNet. Där nätverket är designat som en autoencoder för pixelvis djupskattning av den fria körbara vägytan för stadsområden, där nätverket endast använder sig av en monokulär kamera och dess bilder. Det föreslagna nätverket för djupskattning hanteras som ett regressions problem. AutoNet är även konstruerad som ett klassificeringsnätverk som endast ska klassificera och segmentera den körbara vägytan i realtid med monokulärt seende. Där detta är hanterat som ett övervakande klassificerings problem, som även visar sig vara en mer simpel och mer robust lösning för att hitta vägyta i stadsområden. Vi implementerar även ett av de främsta neurala nätverken ENet för jämförelse. ENet är utformat för snabb semantisk segmentering i realtid, med hög prediktions- hastighet. Evalueringen av nätverken visar att AutoNet utklassar ENet i varje prestandamätning för noggrannhet, men visar sig vara långsammare med avseende på antal bilder per sekund. Olika optimeringslösningar föreslås för framtida arbete, för hur man ökar nätverk-modelens bildhastighet samtidigt som man behåller robustheten.All träning och utvärdering görs på Cityscapes dataset. Ny data för träning samt evaluering för djupskattningen för väg skapas med ett nytt tillvägagångssätt, genom att kombinera förberäknade djupkartor med semantiska etiketter för väg. Datainsamling med ett Scania-fordon utförs även, monterad med en monoculär kamera för att testa den slutgiltiga härleda modellen. Det föreslagna nätverket AutoNet visar sig vara en lovande topp-presterande modell i fråga om djupuppskattning för väg samt vägklassificering för stadsområden.
Benetka, Miroslav. "Modul digitálního signálového procesoru pro ruční RFID čtečku." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217543.
Full textBalestri, Roberto. "Intelligenza artificiale e industrie culturali storia, tecnologie e potenzialità dell’ia nella produzione cinematografica." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2022. http://amslaurea.unibo.it/25176/.
Full textChang, Hao-Ming, and 張浩銘. "Implementation of AES encoder/decoder with FPGA." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/21005168836243667774.
Full text龍華科技大學
電子工程研究所
96
In this thesis, we report the implementation methods of AES encoder/decoder algorithm with Altera FPGA. The theoretical background, data flow, transformations/generations of round keys and the process of encoding/decoding are first reviewed and the corresponding circuit architectures are introduced subsequently. The simulations and synthesis are performed on Altera Stratix II EPS60F1020C5 device, and the figure of merits are as follows: the highest clock rate is 90.03MHz, the latencies for AES-128, AES-192 and AES-256 are 21, 24 and 29 clocks respectively. The throughput are 548.75Mbps, 480.16Mbps and 397.37Mbps for the above three cases respectively. The three options of AES-128, 192 and 256 encoder/decoder are integrated in our module such that it can meet the needs of modern broadband communications.
Su, Chuan-Ming, and 蘇筌銘. "The CAVLC Encoder/Decoder for H.264." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/70347252506009426331.
Full text南台科技大學
電子工程系
94
The representation of audio, image and video signals involves a vast amount of data, so signal compression is indispensable. Recently, Variable-Length Code (VLC) has been widely used in multimedia and lossless coding compression such as JPEG and MPEG. It is also an important part in MPEG-4 video compression standard. The CAVLC (context adaptive variable length coding) in H.264 Standard (also called MPEG-4 Part 10) is an adaptive VLC. This thesis describes a low memory class-based CAVLC encoder/decoder algorithm for H.264.The computation complexity of the proposed CAVLC is quite low and its memory requirement is small. Hence, it’s easily implemented by VLSI. The CAVLC architecture has been synthesized on Quartus II (FPGA software).Finally, the logic element of CAVLC encoder/decoder is 4144 and its clock frequency is 12MHz.
Lei, Chao-Sheng, and 雷朝聖. "The VLC encoder/decoder for MPEG-4." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/79750329993411057859.
Full text南台科技大學
電子工程系
92
The representation of audio, image and video signals involves a vast amount of data, so signal compression is indispensable. Recently, variable length code (VLC) has been widely used in multimedia and lossless coding compression such as JPEG and MPEG. This thesis describes an efficient class-based VLC encoder/decoder and its VLSI architecture for MPEG-4. It takes advantage of logic optimization techniques, and achieves high throughput. The computation complexity of the proposed VLC is quite low and its memory requirement is small. Hence, it is easily implemented by VLSI and very suitable for real-time MPEG-4 applications. The VLC architecture has been synthesized on Synopsys Design Compiler with the standard-cell from TSMC 0.35-μm cell library. Finally, the layout for the design was generated with the Avant! tools, Apollo (for floorplan, placement and routing). The gate counts and core size of VLC encoder/decoder are 9624/9486 and / , respectively. In the simulation, it’s clock frequency achieves 50MHz.
Shao, Chi-Yung, and 邵志勇. "An Efficient Class-Based VLC Encoder/Decoder." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/02310155774295126365.
Full text南台科技大學
電子工程系
90
The representation of audio, image and video signals involves a vast amount of data, so signal compression is indispensable. Recently, variable length code (VLC) has been widely used in multimedia and lossless coding compression. This thesis describes an efficient class-based VLC Encoder/Decoder and its VLSI architecture. It takes advantage of logic optimization techniques, and achieves high throughput. Besides, it required smaller memory size and it very suitable for applications on the many international image standard, such as JPEG, H.261 and MPEG. The computation complexity of the VLC is quite low and its memory requirement is small. Hence, it is easily implemented by VLSI and very suitable for real-time applications. An efficient VLSI architecture for VLC is designed and implemented with FPGA chip. It is synthesized with the standard-cell from TSMC’s 0.35um cell library. The chip areas are about 1645.2um *1645.2um and 1646um*1646um for the encoder and the decoder respectively. It can achieve about 50Mega symbols/sec encoding/decoding rate.
Chen, Jung-Yu, and 陳榮裕. "Study of Parallel Encoder and Decoder of BCH." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/38970291157601272195.
Full text國立高雄第一科技大學
電腦與通訊工程所
98
With the error control code development, early by the Hamming code, Reed-Solomon Code have the current popularity of BCH codes, error control code is quite a mature technology now, the traditional sequence of BCH codes, need to wait for the full transmission code length before End for encoding and decoding, the parallel transmission structure, use quite a waste of time. This is paper attempts to develop parallel architecture of the BCH code and to hardware implementation, so many dollars to meet the immediate transfer of the demand for high-speed operation of the Nand flash with degrees under more fit. This is paper used (7,4) BCH code and can correct 1 bit for the prototype structure, the parallel realization of BCH codes, observed and recorded every bit flow situation, the coding part of the framework we use LFSR encoder for parallel , in the decoder side we find a parallel circuit syndrome start, followed by the syndrome vector use the wrong location to do the corresponding correction actions. We observe and record the sequence of experiments by (7,4) BCH code for each element flow conditions, and parallel simulation in Xilinx platform architecture BCH code, (7,4) The experimental results show that code execution time on parallel 4bits architecture is the traditional sequence of 4 times the cost of the upgrade is only 1.667 times, and decoding parallel to the traditional 7-bit sequence is 7 times the cost of the upgrade is only 1.276 times. Parallel encoding up to 50Mb / s, decode 10Mb / s.
Kuo, Shih-Shan, and 郭仕杉. "A Chip Design for TCM Encoder/Decoder system." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/84882337170197028063.
Full text國立成功大學
電機工程研究所
82
Trellis-coded modulation(TCM) is a scheme combining codingnd modulation. It can get significant coding gains withoutncreasing the transmitted power or the required bandwidth.ut the complexity of Viterbi decoder increases correspondingly.or the TCM encoder proposed in this thesis, there are eight pathsn all parallel transitions of the four- state trellis diagram.he VLSI architecture proposed in this thesis has the advantagef TL(Table-Lookup) method, that it needs only a clock time toecide the minimum branch metric path of the parallel transition,nd finish the branch metric calculation. On the other hand,t needs much smaller area than TL method. This chip has two working modes: Encoding and Decoding.two-phase pipelining architecture for implementing both encodingnd decoding improves the speed performance of this chip. We usehe standard-cell of CCL provided by CIC(Chip Implementationenter),to finish the chip design on CADENCE OPUS3. This chipas fabricated using TSMC 0.8um technology. The chip size is.43*0.46 cm*cm, it contains 48 PADs and gate count is 15440.he working frequency is 30MHZ, and the data rate is 13.3Mbits/s.
Lee, Yu-jen, and 李友仁. "Implementation of MPEG-4 Video Encoder/Decoder on Microprocessors." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/54437330710388387590.
Full text國立中山大學
資訊工程學系研究所
92
Digital image data requires large compression ratio in applications like internet, communication and audio-visual environment. In this thesis, we realize the MPEG-4 codec standard on the ARM9-based platform and improve the execution performance by efficient implementations of the core operations such as Motion Estimation and DCT. In the assembly codes obtained by directly compiling the C codes, there exists a lot of redundant checking which causes a large amount of execution time waste. We rewrite some of the compiled assembly codes to improve the execution efficiency using a variety of techniques such as loop-unrolling and data-type optimization. We also analyze the experimental results using several benchmark video sequences with different modes.
Chen, Jia-Wei, and 陳嘉偉. "Power Efficient H.264 Video Encoder/Decoder Chip Design." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/41858166558877613536.
Full text國立中正大學
電機工程研究所
100
With the advances in the video coding algorithms, there is more and more demanded computational complexity as well as power consumption for battery-operated devices. In this dissertation, several design techniques with low operational voltage scheme are proposed to realize power efficient H.264 video coding design for battery-operated devices. The proposed design techniques which include the quality-adjustable search algorithm, the energy efficient CMOS scheme, and multiple-power domain CMOS scheme reduce the operational voltage for reducing the power consumption at the same time provide better processing performance in low operational voltage. In addition, this dissertation also provides the optimization in the aspects of algorithmic, architectural, and logic levels to reduce the memory bandwidth, hardware cost, and computational complexity to achieve the design goal of power efficient H.264 video design. Using those techniques, this dissertation proposes three power efficient designs for different battery-driven device applications. First, to achieve high throughput rates, low-power consumption, and power-aware features, we proposes a dynamic quality-adjustable H.264 baseline profile (BP) video encoder that can achieve real-time H.264 video encoding on CIF, D1, and HD720@30fps with 7mW-to-25mW, 27mW-to-162mW, and 122mW-to-183mW power dissipation in different quality modes. In addition, this chapter also proposes a dynamic quality-adjustable H.264 intra coder to encode H.264 intra video sequences on D1, HD720 and HD1080 with 10mW to 16mW, 27mW to 45mW, and 60mW power consumption under different quality modes, respectively. For low operational voltage and high processing performance features, the proposed test chip supporting low voltage (LV) H.264/AVC high profile (HP) video decoding with MBAFF coding tool is fabricated in a 90nm CMOS technology. It delivers a maximum throughput of D1@35fps at 0.5-V, which outperforms the 65nm video design at 0.5-V through a 28x improvement in throughput and provides a minimum energy consumption of 280pJ/pixel at 0.5-V as compared to the state-of-the-art H.264 video decoders. Finally, we propose a 0.4v ultra-low-energy (ULE) H.264 image/video encoder to achieve high throughput rates and low power features for wireless capsule endoscope (WCE) applications. Designed in 65nm CMOS technology at the supply voltage of 0.4v, the proposed design owns 2.5x improvement in processing throughput with 0.0196mW. Furthermore, the energy consumption of the proposed design is 14.2pJ/pixel which can achieve one order of the reduction in energy consumption as compared to state-of-the-art implementations. Moreover, in this chapter we also realize the H.264 video encoder by the same design concept with low-voltage and low-power features. Compared to previous compressors used in WCE applications, the proposed video encoder can obtain 18% reduction in energy consumption at 0.4-V.
Cheng, Wei-Cheng, and 程偉政. "Bus Arbiters of the VC-1 Encoder and Decoder." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/89780672286158088262.
Full text國立中正大學
電機工程所
97
In this dissertation, the bus arbiters for the Video Codec 1 (VC-1) are successfully implemented on the Field Programmable Gate Array (FPGA) platform. Particularly, there are three versions of the bus arbiter for the VC-1 decoder and one version of the bus arbiter for the VC-1 encoder. First, the data flows, memory organization and timing arrangement of the bus arbiter are introduced in detail where the addressing mechanism of the bus arbiter depends on the memory types. Second, the implementation manners of the bus arbiters are clearly illustrated. The verilog codes of the bus arbiters are synthesized by the Xilinx synthesis tool, and then simulated by the ModelSim software to verify their functionalities. Third, the proposed bus arbiters integrated with the other modules of the VC-1 codec at different profiles are demonstrated. Additionally, the total equivalent gate counts of the bus arbiters at four versions are explored. From the practical results, the proposed bus arbiters can effectively and correctly conduct the data accessing and manipulation for the VC-1 codec on various multimedia applications.
Song, Wu Chin, and 吳錦松. "Design of an Encoder/Decoder of Reed Solomon code." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/88182428915938709677.
Full textBanakar, Rajeshwari M. "Low power design methodology for turbo encoder and decoder." Thesis, 2004. http://localhost:8080/xmlui/handle/12345678/5557.
Full textLiao, Wen-Hsien, and 廖文賢. "Real-time Implementation for H.264 CAVLC Encoder and Decoder." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/65547232605630931189.
Full text國立高雄第一科技大學
電腦與通訊工程所
95
In this thesis, we design some IPs for the CODEC of H.264/AVC, specially for intra-mode coding. In the encoder, the main module for Discrete Cosine Transform(DCT), Quantizer, Zigzag Scan converter, CAVLC encoder and Packer, are designed. With the modular-by-modular connecting, the circuit can read by 4 pixels per cycle and are compressed to video bit-stream in real-time operation. For CAVLC encoder, we design a parallel architecture that can process a 4*4 block within 16 cycles. For VLC codebook, the equation-based is used rather than ROM table to reduce the ROM size. The simulations are step-by-step to check each modular output to verify the function. The encoder used about 30K gates using cell-based design and the operation speed can achieve 52MHz. In the decoder, the design flow is the relative inverse module to correspond the encoder. We also have the timing control module and input-buffer control module. With parallel structure, the CAVLC decoder can decode one codeword per cycle. Also, we use some condition equations rather than ROM tables. The decoder is implemented with 63K gates, and the operation speed can achieve 40MHz. The output of encoder is sent to the decoder to do the whole system simulation. The decoder can construct the original block in real-time schedule and the results meet our expectations.