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Relevant bibliographies by topics / Energy Power IQ Switch Crossbar

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Academic literature on the topic 'Energy Power IQ Switch Crossbar'

Author: Grafiati

Published: 14 March 2023

Last updated: 31 July 2025

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Journal articles on the topic "Energy Power IQ Switch Crossbar"

1

Luo, Jun, and Boxun Liao. "A Fault-Tolerant Structure for Nano-Power Communication Based on the Multidimensional Crossbar Switch Network." International Transactions on Electrical Energy Systems 2022 (August 24, 2022): 1–8. http://dx.doi.org/10.1155/2022/4783847.

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In order to realize fault tolerance and further reduce the transmission delay, a fault-tolerant structure design method for nano-power communication based on a multidimensional crossbar switch network is proposed. The TSV router is designed as a double crossbar structure, namely the master crossbar (MasterCrossbar) and the slave crossbar (SlaveCrossbar). Each input port of the TSV router is divided into two subports. The port connected to the master crossbar has no input buffer, and the port connected to the slave crossbar has an input buffer. Master crossbar is the first choice for data trans

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2

N, Geethanjali, and Dr Rekha K. R. "Performance Analysis of an Efficient Router using X Y Algorithm." International Journal of Innovative Technology and Exploring Engineering 12, no. 7 (2023): 14–21. http://dx.doi.org/10.35940/ijitee.g9609.0612723.

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As more and more functions are expected to be performed by a single electronic device (such as a smartphone, smart television, etc.), the need to have more and more components on SoC is increasing, posing new difficulties for NoC. The majority of NoC designs utilise mesh, torus, or other topologies to ensure a robust router. Most solutions, however, fall short when it comes to addressing key issues like throughput, area overhead, and latency, as well as QoS and congestion. The current paper proposes a concept for a reconfigurable router that can be used in No C settings. For the suggested rout

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Geethanjali, N., and Rekha K. R. Dr. "Performance Analysis of an Efficient Router using X Y Algorithm." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 12, no. 7 (2023): 14–21. https://doi.org/10.35940/ijitee.G9609.0612723.

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<strong>Abstract: </strong>As more and more functions are expected to be performed by a single electronic device (such as a smartphone, smart television, etc.), the need to have more and more components on SoC is increasing, posing new difficulties for NoC. The majority of NoC designs utilise mesh, torus, or other topologies to ensure a robust router. Most solutions, however, fall short when it comes to addressing key issues like throughput, area overhead, and latency, as well as QoS and congestion. The current paper proposes a concept for a reconfigurable router that can be used in No C setti

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4

Systems, International Transactions on Electrical Energy. "Retracted: A Fault-Tolerant Structure for Nano-Power Communication Based on the Multidimensional Crossbar Switch Network." International Transactions on Electrical Energy Systems 2023 (September 20, 2023): 1. http://dx.doi.org/10.1155/2023/9850432.

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Ying, Jiajie, Guangyi Wang, Yujiao Dong, and Simin Yu. "Switching Characteristics of a Locally-Active Memristor with Binary Memories." International Journal of Bifurcation and Chaos 29, no. 11 (2019): 1930030. http://dx.doi.org/10.1142/s0218127419300301.

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A number of important applications would benefit from the introduction of locally-active memristors, which is defined to be any memristor that exhibits negative differential memristance for at least a voltage or a current applied to the memristor. Two leading examples are emerging nonvolatile memory based on memristor-based crossbar array architectures, and neural networks that exhibit improved computational complexity when operated at the edge of chaos. In this paper, a novel locally-active memristor model is presented for exploring the nonvolatile and switching mechanism of the memristor and

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Humood, Khaled, Yihan Pan, Grahame Reynolds, et al. "SPIKA: an energy-efficient time-domain hybrid CMOS-RRAM compute-in-memory macro." Frontiers in Electronics 6 (April 30, 2025). https://doi.org/10.3389/felec.2025.1567562.

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The increasing significance of machine learning (ML) has led to the development of circuit architectures suited to handling its multiply-accumulate-heavy computational load such as Compute-In-Memory (CIM). A big class of such architectures uses resistive RAM (RRAM) devices, typically in the role of neural weights, to save power and area. In this work, we introduce SPIKA, a novel RRAM-based ML accelerator implemented in 180nm CMOS technology. The design features a 64×128 crossbar array, supports 4-bit inputs, ternary weights, and 5-bit outputs. Post-layout analysis indicates a remarkable perfor

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7

Patel, Ranjeeta, and Anup Kumar Panda. "Real Time Harmonic Mitigation Using Fuzzy Based Highly Reliable Three Dual-Buck Full-Bridge APF for Dynamic Unbalanced Load." International Journal of Emerging Electric Power Systems 19, no. 3 (2018). http://dx.doi.org/10.1515/ijeeps-2017-0167.

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Abstract This study presents a highly reliable 3-phase 4-wire, three dual-buck full-bridge shunt active power filter (3 DB FB APF) for distribution system. The proposed topology uses three single phase dual buck full bridge inverter sharing the same dc-link capacitor with high utilization of dc-bus voltage. The dual buck inverter circuit composed of one power switch and one diode leg instead of two power switches conventional inverter leg effectually eliminate the undesirable “shoot-through” phenomenon occurs in conventional inverter circuit. The fuzzy and adaptive hysteresis current controlle

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Parepalli, Ramanamma, Sanjeev Sharma, and Mohan Kumar Naik. "Design and analysis of 2D 4 × 4 mesh NoC architecture with novel bufferless router for optical communication." Journal of Optical Communications, May 6, 2025. https://doi.org/10.1515/joc-2025-0072.

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Abstract One common connectivity technology in large-scale tiled chip multiprocessors (TCMPs) is network-on-chip (NoC). There are two main types of NoC routers namely buffered and bufferless. Because of its hardware efficiency, lower energy usage, and simplified design, the latter presents a possible option. This paper suggests a new bufferless NoC router design for a 2D 4 × 4 mesh NoC architecture. Each of the four nearby peers (North, South, East, and West) and one processing element are linked to the routers that make up the suggested mesh network. The crossbar switch, input buffers, and ou

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Parepalli, Ramanamma, Sanjeev Shama, and Mohan Kumar Naik. "Bufferless NoC router design for optical networks-on-chip." Journal of Optical Communications, December 10, 2024. https://doi.org/10.1515/joc-2024-0264.

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Abstract In large-scale tiled chip multiprocessors (TCMPs), network-on-chip (NoC) is a prevalent interconnect solution. The NoC router plays a crucial role in NoC architecture, and two primary types exist: buffered and bufferless. The latter offers a promising solution due to its streamlined design, reduced energy consumption, and hardware efficiency. This paper proposes a 2D 4 × 4 mesh NoC architecture with a novel bufferless NoC router design using XY routing algorithm. The proposed mesh network consists of routers and processing elements, with each router connected to its four adjacent peer

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Dissertations / Theses on the topic "Energy Power IQ Switch Crossbar"

1

RICCA, MARCO. "Energy aware control algorithms for computer networks." Doctoral thesis, Politecnico di Torino, 2012. http://hdl.handle.net/11583/2497193.

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The main motivation of this work is to investigate techniques to reduce the power consumption inside a network element. It is enough to consider the high energy demand associated to the telecommunication networks field. As practical consequence the power consumption has become a relevant parameter and it represents a critical constraint for the network designers looking both the whole network infrastructure and the network elements like switches, routers and servers. The PhD has been focused mainly on two research areas of interest, the first one was the power consumption inside the switching

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