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Journal articles on the topic 'ENOB'

Author: Grafiati

Published: 4 June 2021

Last updated: 14 February 2022

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1

Rahmani, Najmeh, Ebrahim Farshidi, and Esmaeil Fatemi-Behbahani. "Analysis and Modeling of Imperfections in Multi-Bit Per Stage Pipelined ADCs." Journal of Circuits, Systems and Computers 25, no. 07 (April 22, 2016): 1650079. http://dx.doi.org/10.1142/s0218126616500791.

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In this paper, an approach to estimate signal to noise ratio (SNR) and effective number of bits (ENOB) in nonideal multi-bit stages of pipelined analog to digital converters (ADCs) is presented. The most significant error sources in multistage ADCs are the capacitor mismatch and the finite and imprecise gain of amplifier. Output voltage of each stage in pipelined ADC is modeled by an ideal and a nonideal output, where nonideal output is the error due to circuit imperfections in each stage. Using an appropriate model, the SNR and ENOB due to circuit nonidealities and in terms of standard deviation of random errors are calculated. Simulation results show the accuracy of the analytical proposed approach in estimation of SNR and ENOB in multi-bit per stage pipelined converters.

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2

Liu, Yue, Jifang Qiu, Chang Liu, Yan He, Ran Tao, and Jian Wu. "An Optical Analog-to-Digital Converter with Enhanced ENOB Based on MMI-Based Phase-Shift Quantization." Photonics 8, no. 2 (February 14, 2021): 52. http://dx.doi.org/10.3390/photonics8020052.

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An optical analog-to-digital converter (OADC) scheme with enhanced bit resolution by using a multimode interference (MMI) coupler as optical quantization is proposed. The mathematical simulation model was established to verify the feasibility and to investigate the robustness of the scheme. Simulation results show that 20 quantization levels (corresponding to 4.32 of effective number of bits (ENOB)) are realized by using only 6 channels, which indicates that the scheme requires much fewer quantization channels or modulators to realize the same amount of ENOB. The scheme is robust and potential for integration.

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3

Liu, Xiao Wei, Qiang Li, Guan Nan Sun, and Wen Yan Liu. "A Fourth-Order MASH Sigma-Delta Modulator in Inertial Sensors." Key Engineering Materials 562-565 (July 2013): 311–16. http://dx.doi.org/10.4028/www.scientific.net/kem.562-565.311.

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The theory of a Sigma-Delta modulator is introduced in this paper. Based on this theory, a feedback 2-1-1 multi-stage-noise-shaping (MASH) sigma-delta modulator is designed, and the coefficients of the modulator are calculated. The system-level simulation results show that the effective number of bits (ENOB) is 24 bits when the signal bandwidth is 1 kHz and the over-sampling (OSR) rate is 128. Then the circuits of modulator are designed, including integrator, comparator, multi-phase clock and the noise cancelling logic. The whole modulator is simulated in Cadence, the signal to noise ratio (SNR) of the modulator is 125.4dB, and the ENOB is 21.1bits, which meet the technical requirements of the sensor.

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4

Dastagiri Nadhindla, Bala, and K. Hari Kishore. "A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 30. http://dx.doi.org/10.14419/ijet.v7i2.8.10319.

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This brief presents a 10kS/s 14 bit 12.5 ENOB Successive Approximation Register Analog-to- Digital Converter for Cardiac Implantable Medical. For achieving power efficient operation, SAR ADC employ SAR control, a new power and noise efficient comparator topology, non- binary weighted capacitive DAC. The linearity of implemented SAR ADC is enhanced with the uniform geometry of non-binary weighted capacitive DAC.The proposed SAR ADC is implemented using 65nm CMOS technology. The latched comparator consumes a power of 2.4uW and it provides an ENOB of 12.6 at a supply voltage of 1V.The INL is between -2.7/+1.6 LSB and DNL is between -0.6/+1.4LSB. The FOM of ADC is 40fJ/conv. Step which is comparable with existing ADC topologies.

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5

Liu, Xin, Yan Liu, and Zengshou Dong. "An ENOB Evaluation Method for an Acquisition Channel." Journal of Circuits, Systems and Computers 28, no. 11 (October 2019): 1950185. http://dx.doi.org/10.1142/s0218126619501858.

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Three-parameter and four-parameter sine-wave fitting algorithms are powerful tools for estimating the parameters of the excited single-tone sine-wave for ADC. In the dynamic performance testing processes of instruments, the angle frequency, amplitude, phase and dc component of the input sine-wave are all unknown, so the fitting procedure is nonlinear. This paper proposes and analyzes a test method based on iteration Interpolated Discrete Fourier Transform (IpDFT) and sine-wave fitting method for evaluating the effective number of bit (ENOB) of the acquisition channel. Mathematical expressions of the Least-square fitting residual error and the proposed ENOB evaluation based on iteration IpDFT method are derived. These expressions are then particularized for acquisition circuit output noise composed of single-tone and additive white noise. Simulation results show that the DFT-based golden section searching algorithm (DGSSA) is an effective algorithm under coherent and non-coherent sampling conditions. The accuracy of the derived expressions and estimated parameters are verified through both the computer simulations and experimental results.

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6

Liu, Liang, Song Chen, Chong He, Liang Yin, and Xiao Wei Liu. "Design of Third-Order Single-Loop Full Feed-Forward Sigma Delta Modulator." Key Engineering Materials 609-610 (April 2014): 1176–80. http://dx.doi.org/10.4028/www.scientific.net/kem.609-610.1176.

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Sigma Delta modulator is widely used in ADC for kinds of micro inertial sensors, Sigma Delta ADC can be easily integrated with digital circuits. It possesses some performances of good linearity and high accuracy, while it has no such strict requirements for the match of device dimensions. In this paper, the design of third-order Sigma Delta modulator with a structure of single-loop full feed-forward is accomplished, meanwhile it uses local feedback for zero optimization to improve the shaping capacity of the modulator noise within the signal bandwidth. The OSR (over-sampling rate) of the modulator is 128 and the signal bandwidth is 10 kHz. By the system model building and simulation in the Simulink of MATALAB, the SNR is 96.3 dB and the ENOB is 15.71 bits. Then the modulator is implemented into transistor-level circuits with 0.5um process, by the simulation in Spectre of Cadence, the SNR is 88.5 dB and the ENOB is 14.41 bits. 搜

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7

Abdo, Ahmad, Xueyang Li, Md Samiul Alam, Mahdi Parvizi, Naim Ben-Hamida, Claude D’Amours, and David Plant. "Partial Pre-Emphasis for Pluggable 400 G Short-Reach Coherent Systems." Future Internet 11, no. 12 (December 11, 2019): 256. http://dx.doi.org/10.3390/fi11120256.

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Pre-emphasis filters are used to pre-compensate for the transmitter frequency response of coherent systems to mitigate receiver noise enhancement. This is particularly essential for low-cost, low-power coherent transceivers due to having an extremely bandlimited transmitter. However, the pre-emphasis filter also increases the signal peak-to-average power ratio (PAPR), thus posing a higher effective number of bits (ENoB) requirement for the arbitrary waveform generator (AWG). In this paper, we first numerically study the PAPR impact of partial pre-emphasis filters. We show that with partial pre-emphasis, an ENoB reduction from 5 to 4.5 bits is attainable at the same signal-to-noise ratio (SNR) out of the AWG. Next, we experimentally investigate the overall performance penalty of partial pre-emphasis in a 50 Gbaud 16QAM coherent system. A manageable Q factor penalty of around 0.5 dB is found for both single-polarization and dual-polarization systems with a 0.8 dB PAPR reduction.

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8

Kowalski, Tomasz, Gian Piero Gibiino, Jaroslaw Szewinski, Pawel Barmuta, Piotr Bartoszek, and Pier Andrea Traverso. "Design, characterisation, and digital linearisation of an ADC analogue front-end for gamma spectroscopy measurements." ACTA IMEKO 10, no. 2 (June 29, 2021): 70. http://dx.doi.org/10.21014/acta_imeko.v10i2.1042.

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<p class="Abstract">This work presents the design, experimental characterisation, and digital post-distortion (i.e., digital linearisation) of a MHz-range ADC analogue front-end prototype for a gamma radiation spectrometry system under development at the National Center for Nuclear Research (NCBJ) in Poland. The design accounts for the electrical response of the gamma particle detector in providing signal conditioning and ADC protection against high-voltage spikes due to occasional high-energy cosmic radiation, as well as proper ADC clocking. As the front-end inevitably introduces nonlinear distortion and dynamic effects, a characterisation is performed to quantify the actual performance in terms of Total Harmonic Distortion (THD) and Effective Number of Bits (ENOB). Thus, a digital linearisation based on both static and memory polynomial models is successfully applied by means of post-distortion processing, guaranteeing a substantial improvement in THD and ENOB, and demonstrating the effectiveness of the hardware/software method for gamma radiation spectrometers. </p>

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9

Varughese, Siddharth, Daniel Lippiatt, Sorin Tibuleac, and Stephen E. Ralph. "Frequency Dependent ENoB Requirements for 400G/600G/800G Optical Links." Journal of Lightwave Technology 38, no. 18 (September 15, 2020): 5008–16. http://dx.doi.org/10.1109/jlt.2020.3000177.

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10

Alvero-Gonzalez, Leidy Mabel, Victor Medina, Vahur Kampus, Susana Paton, Luis Hernandez, and Eric Gutierrez. "Ring-Oscillator with Multiple Transconductors for Linear Analog-to-Digital Conversion." Electronics 10, no. 12 (June 11, 2021): 1408. http://dx.doi.org/10.3390/electronics10121408.

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This paper proposes a new circuit-based approach to mitigate nonlinearity in open-loop ring-oscillator-based analog-to-digital converters (ADCs). The approach consists of driving a current-controlled oscillator (CCO) with several transconductors connected in parallel with different bias conditions. The current injected into the oscillator can then be properly sized to linearize the oscillator, performing the inverse current-to-frequency function. To evaluate the approach, a circuit example has been designed in a 65-nm CMOS process, leading to a more than 3-ENOB enhancement in simulation for a high-swing differential input voltage signal of 800-mVpp, with considerable less complex design and lower power and expected area in comparison to state-of-the-art circuit based solutions. The architecture has also been checked against PVT and mismatch variations, proving to be highly robust, requiring only very simple calibration techniques. The solution is especially suitable for high-bandwidth (tens of MHz) medium-resolution applications (10–12 ENOBs), such as 5G or Internet-of-Things (IoT) devices.

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11

Duan, Jihai, Zhiyong Zhu, Jinli Deng, and Weilin Xu. "An 8 bit 1 MS/s SAR ADC with 7.72-ENOB." Journal of Semiconductors 38, no. 8 (August 2017): 085005. http://dx.doi.org/10.1088/1674-4926/38/8/085005.

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12

Song, Yan, Zhongming Xue, Pengcheng Yan, Jueying Zhang, and Li Geng. "A 0.6-V 8.3-ENOB asynchronous SAR ADC for biomedical applications." Journal of Semiconductors 35, no. 8 (August 2014): 085007. http://dx.doi.org/10.1088/1674-4926/35/8/085007.

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13

Morton, S. L., A. E. Cosand, D. A. Hitko, C. Baringer, L. Luh, C. M. Lin, J. F. Jensen, C. M. Li, and D. Crampton. "Ku-band subsampling track-and-hold amplifier with 8 ENOB resolution." Electronics Letters 42, no. 8 (2006): 459. http://dx.doi.org/10.1049/el:20060150.

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14

Chen, Cheng Ying, Lan Dai, Xiao Yu Hu, and Yong Hei. "A 10bit 1MHZ SAR ADC for Automobile Electronics MCU with Rail-to-Rail Input Swing." Advanced Materials Research 765-767 (September 2013): 2439–43. http://dx.doi.org/10.4028/www.scientific.net/amr.765-767.2439.

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Based on the DAC structure of single sampling capacitor that insures the rail-to-rail input swing a 10bit 1MHZ SAR ADC is implemented in GSMC 0.18μm 1P6M CMOS Mixed-Signal process for automobile electronics MCU. The measurement results show that in 1.8V power supply, 51KHZ input frequency and 1MHZ clock frequency, the SFDR is 71.364 dB, ENOB is 9.49 bit, total power is 2.24mW, which meet the application requirements of automobile electronics MCU.

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15

Liu, Wen Yan, Bin Zhang, Long Chen, Chao Gao, and Xiao Wei Liu. "A High-Performance Mash Fourth-Order Sigma-Delta Modulator." Key Engineering Materials 503 (February 2012): 207–10. http://dx.doi.org/10.4028/www.scientific.net/kem.503.207.

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This paper reports on a system level design and analysis of a mash fourth-order sigma-delta (ΣΔ) modulator. Compared with a high-order single-loop ΣΔ modulator (ΣΔM), there’s no need to consider about the system stability of a mash ΣΔM, which has the advantages of better signal to quantization noise ratio (SQNR). System level simulation results indicate that the SQNR is 122.0 dB, and the effective number of bits (ENOB) is 19.97 bits when the over sampling ratio (OSR) is 128.

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16

Ivanisevic, Nikola, Saul Rodriguez, and Ana Rusu. "A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems." IEEE Transactions on Circuits and Systems I: Regular Papers 65, no. 12 (December 2018): 4051–61. http://dx.doi.org/10.1109/tcsi.2018.2838135.

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17

Wang, Ke, Chaojie Fan, Jianjun Zhou, and Wenjie Pan. "A 14-bit 100-MS/s CMOS pipelined ADC with 11.3 ENOB." Journal of Semiconductors 34, no. 8 (August 2013): 085015. http://dx.doi.org/10.1088/1674-4926/34/8/085015.

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18

TANG, XIAN, and KONG PANG PUN. "A NOVEL SWITCHED-CURRENT SUCCESSIVE APPROXIMATION ADC." Journal of Circuits, Systems and Computers 20, no. 01 (February 2011): 15–27. http://dx.doi.org/10.1142/s0218126611007049.

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A novel switched-current successive approximation ADC is presented in this paper with high speed and low power consumption. The proposed ADC contains a new high-accuracy and power-efficient switched-current S/H circuit and a speed-improved current comparator. Designed and simulated in a 0.18-μm CMOS process, this 8-bit ADC achieves 46.23 dB SNDR at 1.23 MS/s consuming 73.19 μW under 1.2 V voltage supply, resulting in an ENOB of 7.38-bit and an FOM of 0.357 pJ/Conv.-step.

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19

Makara, Felipe, Lucas Mangini da Silva, Luis Henrique Assumpção Lolis, and Andre Mariano. "A low-power 10-bit 6.66 MS/s CMOS SAR ADC with built-in digital calibration dedicated to Wireless Sensor Networks applications." Journal of Integrated Circuits and Systems 13, no. 3 (December 12, 2018): 1–8. http://dx.doi.org/10.29292/jics.v13i3.4.

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In this paper, an energy-efficient SAR ADC for IoT applications is presented. The proposed ADC relies on a built-in calibration circuit to improve accuracy and introduces an original DAC that merges the concepts of binary-weighted and C/2C arrays in order to achieve a favorable trade-off between area, accuracy and power consumption. The system consumes 58 µW per conversion cycle sampling at a frequency of 6.66 MHz with an SNDR of 49.78 dB for a 1MHz input signal. With an ENOB of 8 bits, the resulting FOM is 34fJ/conversion-step.

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20

CHEN, Zhijie, Masaya MIYAHARA, and Akira MATSUZAWA. "A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC." IEICE Transactions on Electronics E99.C, no. 8 (2016): 963–73. http://dx.doi.org/10.1587/transele.e99.c.963.

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21

Zhang, Dai, and Atila Alvandpour. "A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS." IEEE Transactions on Circuits and Systems II: Express Briefs 63, no. 3 (March 2016): 244–48. http://dx.doi.org/10.1109/tcsii.2015.2482618.

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22

Zhuang, Haoyu, Q. Cao, X. Peng, and H. Tang. "A 7.6b ENOB, 16× Gain, 360mVpp Output Swing, Open-Loop Charge Steering Amplifier." IEEE Access 8 (2020): 203294–300. http://dx.doi.org/10.1109/access.2020.3037228.

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23

Mattia, O. E., and B. Murmann. "80 GS/s 5.5 ENOB time‐interleaved inverter‐based CMOS track‐and‐hold." Electronics Letters 56, no. 7 (March 2020): 328–29. http://dx.doi.org/10.1049/el.2019.4104.

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24

Cai, Hua. "A 1.8 V low-power 14-bit 20 Msps ADC with 11.2 ENOB." Journal of Semiconductors 33, no. 11 (November 2012): 115013. http://dx.doi.org/10.1088/1674-4926/33/11/115013.

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25

Fan, Hua, Xue Han, Qi Wei, and Huazhong Yang. "An 11-bit ENOB, accuracy-programmable, and non-calibrating time-mode SAR ADC." Journal of Semiconductors 34, no. 1 (January 2013): 015010. http://dx.doi.org/10.1088/1674-4926/34/1/015010.

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26

Fu, Qiang, Wei Ping Chen, Song Chen, Peng Fei Wang, and Xiao Wei Liu. "A High Bandwidth Sigma-Delta Modulator Applied in Micro-Gyroscope." Key Engineering Materials 562-565 (July 2013): 369–73. http://dx.doi.org/10.4028/www.scientific.net/kem.562-565.369.

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In this paper a fourth-order single-loop sigma-delta modulator applied in micro-gyroscope is designed. The modulator system chose the fully feedforword structure. The signal bandwidth is 200KHz, oversampling ratio is 64 and sampling frequency is 25.6MHz. By system simulation result in Matlab, the signal to noise ratio (SNR) is 92.3dB and effective number of bits (ENOB) is 15.03bits. The whole circuit of modulator is designed and simulated in Cadence Spectre. It is gotten that the SNR is 78.6dB and changes linearly with input level. When input level is bigger than -4dBFs, the modulator becomes overload.

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27

Qin, Peng, Hao Lu, Zhi Ye Jiang, Jin Liang Bai, Lu Gao, and Gang Meng. "Design and Test of High Speed Digitization Sampling Circuit Based on FPGA." Applied Mechanics and Materials 482 (December 2013): 386–89. http://dx.doi.org/10.4028/www.scientific.net/amm.482.386.

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To sample wideband IF signal with large amounts of data, a high-speed data acquisition program is presented. The program focus on circuit design, issues that need attention, and high-speed sampling signal deceleration strategy. The 2.4GHz rate sampling data acquisition, reception and demux are completed with ADC083000 and Field-Programmable Gate Array (FPGA). At last, a result of sampling with the converter is offered by chipscope software. The result verified ADC083000 has an excellent performance with more than 6.5 bit ENOB and good phase coherence. In engineering practice, the design has been used and has good performance.

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28

Hong, Hui, Shi Liang Li, and Shuai Liu. "Design of a Low Power Multi-Channel 10Bit SAR ADC." Applied Mechanics and Materials 513-517 (February 2014): 4576–79. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.4576.

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To meet the demand of low power multi-channel ADCs, a 10bit 4-channels SAR ADC using CSMC 0.35um 3.3V 2P4M technology was designed. By optimizing the power dissipation of the interior comparator and the interior DAC, the designed ADC costs only 300uW under 2V single supply with a sampling rate as high as 300KS/s. Meanwhile 1024 points FFT was used with MATLAB tools to analysis and calculate the converted results of the SAR ADC and the calculated results shown the SNR is about 60dB, ENOB is 9.6bit, DNL is 0.033LSB and the INL is 0.312LSB.

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29

SHEN, SIDA AMY, SHUANG XIE, and WAI TUNG NG. "A POWER AND AREA EFFICIENT 65 nm CMOS DELAY-LINE ADC FOR ON-CHIP VOLTAGE SENSING." Journal of Circuits, Systems and Computers 22, no. 09 (October 2013): 1340014. http://dx.doi.org/10.1142/s0218126613400148.

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This paper presents a 4-bit windowed delay-line analog-to-digital converter (ADC) implemented in 65 nm CMOS technology for VLSI dynamic voltage scaling power management applications. Good linearity is achieved in the proposed power and area efficient ADC without the use of resistors for compensation. The circuit performance was analyzed theoretically and verified experimentally. The measured DNL is within ±0.25 LSB and INL ±0.15 LSB. It occupies an area of 0.009 mm2. With a sampling rate of 4 MHz, the ADC consumes 14 μW with an ENOB of 4.1 and voltage sensing range from 0.87 V to 1.32 V.

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30

Lv, Bing Jun, Peng Fei Wang, Dong Bo Wang, Jun'an Liu, and Xiao Wei Liu. "A High-Performance Closed-Loop Fourth-Order Sigma-Delta Micro-Machined Accelerometer." Key Engineering Materials 503 (February 2012): 134–38. http://dx.doi.org/10.4028/www.scientific.net/kem.503.134.

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In this paper a high-performance closed-loop fourth-order sigma-delta (ΣΔ) micro-accelerometer is presented. After a introduction of sigma-delta accelerometer, system-level analysis and design of a fourth-order sigma-delta micro-accelerometer is given. The simulation result shows that an accelerometer with 107dB signal to noise ratio (SNR) and 17.5 bits effective number of bits (ENOB) is achieved. Through the root locus analysis, it is got that accelerometer is stable when quantization gain is bigger than 0.262. The accelerometer gets a good linearity and it becomes overload when input signal level is greater than -5dBFS.

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31

ZHANG, YAJING, WENGAO LU, GUANNAN WANG, ZHONGJIAN CHEN, and YACONG ZHANG. "A LOW POWER HIGH RESOLUTION ROIC DESIGN WITH 14-BIT COLUMN-LEVEL ADC FOR 384 × 288 IRFPA." Journal of Circuits, Systems and Computers 22, no. 09 (October 2013): 1340015. http://dx.doi.org/10.1142/s021812661340015x.

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A readout integrated circuit (ROIC) of infrared focal plane array (IRFPA) with low power and low noise is presented in this paper. It consists of a 384 × 288 pixel array and column-level A/D conversion circuits. The proposed system has high resolution because of the odd–even Analog to Digital Conversion (ADC) structure, containing correlated switches design, multi-Vth amplifier design and high speed high resolution comparator design including latch-stage. Designed and simulated in 0.35-μm CMOS process, this high performance ROIC achieves 81.24 dB SNR at 8.64 KS/s consuming 98 mW under 5 V voltage supply, resulting in an ENOB of 13.2-bit.

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32

Lee, Hokyu, Sejin Park, Chaegang Lim, and Chulwoo Kim. "A 100-nW 9.1-ENOB 20-kS/s SAR ADC for Portable Pulse Oximeter." IEEE Transactions on Circuits and Systems II: Express Briefs 62, no. 4 (April 2015): 357–61. http://dx.doi.org/10.1109/tcsii.2014.2387680.

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33

NESHANI, SARA, and SEYED JAVAD AZHARI. "A LOW-POWER LOW-VOLTAGE 6-BIT 1.33 GS/s FULLY MCML ALL NMOS FLASH ADC WITHOUT A FRONT-END T/H." Journal of Circuits, Systems and Computers 22, no. 08 (September 2013): 1350074. http://dx.doi.org/10.1142/s0218126613500746.

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In this work, a 6-bit 1.33 GS/s flash analog-to-digital converter (ADC) is proposed. To noticeably save the power and area and greatly increase the speed, compactness and accuracy its complete structure is elaborately implemented in MOS Current Mode Logic (MCML) topology. The proposed ADC does not use a front-end track and hold (T/H) block either. Furthermore, a novel optimized resistance ratio averaging-interpolation scheme is applied to: (1) reduce the offset, nonlinearity, number of preamplifiers, area and the power (2) increase the accuracy and mismatch insensitivity (3) minimize the size of elements towards the more compact size, smaller area and higher speed for the ADC. To maximize all these achievements, most favorably, it is completely built by NMOS transistors realizing the ever desired unique NMCML (NMOS-MCML) structure. Using intermediate gray encoding and exponential gains by extra latches greatly removes the bubble/meta-stability error and increases both the speed and the accuracy. Utilizing a differential ladder and some other deliberate arrangements reduces the kickback noise and common mode interferences, minimizes the structure and facilitates fast recovery of overdrive signals. The proposed ADC is simulated by Hspice using 0.18 μm TSMC technology and shows; effective resolution band width (ERBW) larger than 903 MHz that is 1.36 times more than Nyquist frequency (fs/2), 35.17 dB/49.4 dB SNDR/SFDR, 5.53 bits ENOB (rather flat SNDR and ENOB from 50 MHz to 750 MHz), and the low power consumption of 37.77 mW from a 1.2 V supply. These results prove that applying so many effective and novel plans has obtained a unique all N-MCML flash ADC with power-efficiency of 0.61 pJ per conversion step. Both Monte Carlo and corner cases simulations in addition to temperature analysis are performed that prove both intra-die and inter-die robustness of the proposed structure.

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34

Zhou, Jia Jun, Di Wang, Ying Kai Zhao, Hong Lin Xu, and Xiao Wei Liu. "A High-Resolution Lowpass Sigma-Delta Modulator Applied in Micro-Gyroscope." Key Engineering Materials 609-610 (April 2014): 964–67. http://dx.doi.org/10.4028/www.scientific.net/kem.609-610.964.

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In this paper, in order to enhance resolution and guarantee the stability of the micro-gyroscope, a high-resolution lowpass sigma-delta modulator is proposed. It employs single-loop fourth-order and full differential structure. The simulated result on the Simulink platform shows that the SNDR is 105.4dB and the effective number of bits (ENOB) is 17.22bits. The entire circuits are implemented with 0.5μm CMOS process. The simulated result on Cadence shows that the SNDR is 99.7dB. The modulator operates at a sampling frequency of 25.6MHz and the signal bandwidth is 100kHz with 128 oversampling ratio (OSR). The dynamic range (DR) is 120 dB approximately and the SNDR changes linearly with the input level.

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35

Gao, Yu Han, Yong Lu Wang, Guang Bin Chen, Zheng Ping Zhang, Can Zhu, Lei Zhang, Rong Ke Ye, and Rong Bin Hu. "An 8-bit 5-Gsample/s Time-Interleaved Analog-to-Digital Converter Used for Optical Communication." Advanced Materials Research 756-759 (September 2013): 205–8. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.205.

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In this paper, we present an 8-bit 5 Gsample/s time-interleaved analog-to-digital converter (TI ADC). A 4-phase low jitter clock is designed to control four 1.25 Gsample/s sub-ADCs which is implemented using folding and interpolating architecture. Digital calibration is used to adjust the offset error and gain error of sub-ADCs. Meanwhile, serial peripheral interface (SPI) is adopted to adjust mismatch of gain and sample time between sub-ADCs. The whole TI ADC is designed using a 0.18m SiGe BiCMOS process. The whole ADC has a SNR of about 45 dB at the input frequency of 495 MHZ and an equivalent ENOB of 7.2 bits.

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Wang, Peng Fei, Yuan Yuan, Dong Bo Wang, Xiao Wei Liu, and Jun'an Liu. "A High Performance Fourth-Order Single-Loop Sigma Delta Modulator Applied in Micro-Inertial Sensors." Key Engineering Materials 503 (February 2012): 303–7. http://dx.doi.org/10.4028/www.scientific.net/kem.503.303.

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This paper presents a fourth-order sigma delta (ΣΔ)modulator applied in micro-inertial sensors. After a introduction of sigma-delta modulator and its application in micro-inertial sensors, the system-level analysis and design is given and the gain coefficients is calculated. By the use of root locus, the stability of high order ΣΔ modulator is analyzed and it is got the minimum value of quantizer gain k is 0.287. The simulation shows that the signal to noise ratio (SNR) is 121.6 dB and the effective number of bits (ENOB) is 19.91 bits. When input level is smaller than -6 dBFs, the quantizer and integrators would not be overload and work well.

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Fexa, Pavel, Josef Vedral, and Jakub Svatoš. "DAC Testing Using Modulated Signals." Metrology and Measurement Systems 18, no. 2 (January 1, 2011): 283–94. http://dx.doi.org/10.2478/v10178-011-0010-0.

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DAC Testing Using Modulated Signals This document analyses qualities of methods used for testing dynamical parameters of Digital-to-Analog Converters (DAC) using a multi-frequency signal. As the source for these signals, Amplitude Modulated (AM) and Frequency Modulated (FM) signals are used. These signals are often used in radio engineering. Results of the tests, like Effective Number of Bits (ENOB), Signal-to-Noise and Distortion (SINAD), are evaluated in the frequency domain and they are compared with standard results of Sine Wave FFT test methods. The aim of this research is firstly to test whether it is possible to test a DAC using modulated signals, secondly to reduce testing time, while estimating band performance of DAC.

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Lee, Han-Yeol, Dong-Gil Jeong, Yu-Jeong Hwang, Hyun-Bae Lee, and Young-Chan Jang. "A 1-V 1.6-GS/s 5.58-ENOB CMOS Flash ADC using Time-Domain Comparator." JSTS:Journal of Semiconductor Technology and Science 15, no. 6 (December 30, 2015): 695–702. http://dx.doi.org/10.5573/jsts.2015.15.6.695.

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Ghanad, Mehrdad A., Michael M. Green, and Catherine Dehollain. "A 15 $\mu{\rm W}$ 5.5 kS/s Resistive Sensor Readout Circuit with 7.6 ENOB." IEEE Transactions on Circuits and Systems I: Regular Papers 61, no. 12 (December 2014): 3321–29. http://dx.doi.org/10.1109/tcsi.2014.2334932.

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Gamad, R. S., and D. K. Mishra. "Gain error, offset error and ENOB estimation of an A/D converter using histogram technique." Measurement 42, no. 4 (May 2009): 570–76. http://dx.doi.org/10.1016/j.measurement.2008.10.003.

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Gamad, R. S., and D. K. Mishra. "Code transition error effects on estimation of nonlinearity and ENOB of an A/D converter." International Journal of Electronics 98, no. 11 (November 2011): 1503–15. http://dx.doi.org/10.1080/00207217.2011.601440.

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Belcher, R. Allan. "ADC Standard IEC 60748-4-3: Precision Measurement of Alternative ENOB Without a Sine Wave." IEEE Transactions on Instrumentation and Measurement 64, no. 12 (December 2015): 3183–200. http://dx.doi.org/10.1109/tim.2015.2450296.

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Ghosh, Abhishek, and Sudhakar Pamarti. "Linearization Through Dithering: A 50 MHz Bandwidth, 10-b ENOB, 8.2 mW VCO-Based ADC." IEEE Journal of Solid-State Circuits 50, no. 9 (September 2015): 2012–24. http://dx.doi.org/10.1109/jssc.2015.2423975.

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Chen, Kairang, Prakash Harikumar, and Atila Alvandpour. "Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS." Analog Integrated Circuits and Signal Processing 86, no. 1 (October 18, 2015): 87–98. http://dx.doi.org/10.1007/s10470-015-0648-2.

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Li, Yao Guang, Xiao Wei Liu, Yan Xiao, and Yun Tao Liu. "A High-Performance Fourth-Order Sigma-Delta Micromachined Accelerometer." Key Engineering Materials 483 (June 2011): 422–26. http://dx.doi.org/10.4028/www.scientific.net/kem.483.422.

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This paper reports on a system level design and analysis of a single-loop fourth-order sigma-delta (ΣΔ) accelerometer. Compared with a second-order single-loop ΣΔ modulator (ΣΔM) formed by the sensing element here the sensing element is cascaded with two extra electronic integrators to form the fourth ΣΔM, which has the advantages of better signal to quantization noise ratio (SQNR). System level simulation results indicate that the SQNR is 96.86 dB, and the effective number of bits (ENOB) is 15.8 bits when the over sampling ratio (OSR) is 128. Stability of the system is analyzed by root locus method based on the linear model established in this work, and the minimum gain of the quantizer Kq min is about 0.375.

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Et.al, Yarlagadda Archana. "Design of 16-Bit SAR ADC Using DTMOS Technique." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (April 10, 2021): 3046–54. http://dx.doi.org/10.17762/turcomat.v12i3.1339.

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This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. The designed comparator is a differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created for proper operation to remain in saturation and could be used with differential amplifier. The comparator is the chief block of power consumption, so we focused mainly much of ability we make to design this module. The ADC is designed using Cadence virtuoso with CMOS 45nm technology. For SFDR, SNR, ENOB and power consumption, the converter utilizes 63.97dB, 51.06 dB, 15.15 and 528.8uw.

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Kakarla Hari Kishore, Yarlagadda Archana,. "Design of 16-Bit SAR ADC Using DTMOS Technique." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (April 11, 2021): 144–52. http://dx.doi.org/10.17762/turcomat.v12i5.806.

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This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. The designed comparator is a differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created for proper operation to remain in saturation and could be used with differential amplifier. The comparator is the chief block of power consumption, so we focused mainly much of ability we make to design this module. The ADC is designed using Cadence virtuoso with CMOS 45nm technology. For SFDR, SNR, ENOB and power consumption, the converter utilizes 63.97dB, 51.06 dB, 15.15 and 528.8uw.

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48

Dobrynin, V. V. "Increasing the accuracy of an analogue-to-digital converter (ADC) with an intermediate voltage-to-frequency conversion." Journal of «Almaz – Antey» Air and Space Defence Corporation, no. 1 (February 27, 2021): 42–51. http://dx.doi.org/10.38013/2542-0542-2021-1-42-51.

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The article proposes an approach to increasing the resolution of integrated analogue-to-digital (ADC) converters with intermediate voltage-to-frequency conversion (VFC). At sampling rate1 kHz was achieved effective number of bits (ENOB) from 12 to 16. In addition, an approach to compensating for the non-linearity of voltage-to-frequency conversion was proposed. Across the range of measured voltages from 100 mV to 8 V, the voltage measurement error comprised no more than ±0.025 %, which corresponds to a five-and-a-half-bit voltmeter. The proposed device was implemented exclusively on mass-produced chips. The six independent ADC channels, implemented on 1316PP1AU VFCs, are serviced by a single 1986VE91 microcontroller, with the processor loading with the task of improving accuracy being no more than 10%.

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Ray, Arghya, Yan Song, Dharminder Chauhan, and Kenneth C. Anderson. "Preclinical Validation of Alpha-Enolase (ENO1) As a Novel Immunometabolic Target in Multiple Myeloma." Blood 134, Supplement_1 (November 13, 2019): 856. http://dx.doi.org/10.1182/blood-2019-123328.

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Introduction. Bone marrow plasmacytoid dendritic cells (pDCs) in patients with multiple myeloma (MM) both promote tumor growth, survival, and drug resistance, as well as induce decreased T/NK effector cell function and immune suppression. Delineation of the mechanism(s) mediating pDCs-MM-T-NK cells interactions may therefore identify novel therapeutic targets to enhance anti-MM immunity. Using gene expression profiling, we show that pDC-MM interactions trigger significant upregulation of the immunosuppressive metabolic enzyme alpha-Enolase (ENO1) in both pDCs and MM cells. ENO-1 functions as a glycolytic enzyme and plasminogen receptor which is overexpressed on the surface of tumor cells and MM pDCs. Here, we utilized our coculture models of patient autologous pDC-T-NK-MM cells to examine whether targeting ENO1, either alone or in combination can enhance anti-MM immunity in the BM milieu. Methods Gene expression profiles of MM cells cultured in the presence vs absence of pDCs were compared, and a heat map was generated (>1.5-fold change was considered significant, CI > 95%). MM cells were co-cultured with pDCs for 24h, followed by multicolor flow analyses to determine the pDC-induced change in ENO1 expression. Cytotoxic T lymphocyte (CTL) and NK cell activity assays: MM patient BM CD8+ T or NK-cells were cocultured with autologous pDCs (pDC1:T/NK10 ratio) in the presence or absence of ENO1 inhibitor/ENO1i ENOblock (0.2 µM) or anti-ENO1 Ab for 5 days; MM pre-stained cells were added for 24h (10T/NK:1MM), followed by quantification of viable MM cells by FACS. Anti-PD-L1 Ab (5 ug/ml) or HDAC 6 selective inhibitor ACY-241 (0.2 uM) were utilized for combination studies with ENO1i. CD107a expression was quantified in a degranulation assay. Results GEP analysis showed that pDCs induce upregulation of ENO1 transcript in MM (1.8-fold vs MM alone; n = 3; CI > 95%). Protein expression analysis showed that ENO1 is expressed in both pDC and MM cells; and importantly, that pDC-MM coculture further increases ENO1 expression in MM cells (5-6-fold; n=3; p = 0.003). The ENO+ MM cell population is also increased after pDC-MM cell coculture (3-4-fold vs MM; mean ± SD; n = 3; p = 0.005). Blockade of ENO1 with ENO inhibitor (ENOi) activates pDCs, as evidenced by increase in pDCs maturation/activation markers (CD80/CD83/CD86). Importantly, ENOi restores the ability of pDCs to trigger T cell activation and proliferation (n = 3; p = 0.018). Above all, ENOi increases pDC-induced MM-specific CD8+ CTL activity (p = 0.006), as well as NK cell-mediated cytolytic activity against autologous tumor cells (p = 0.005). Moreover, pDC-mediated MM-specific CD8+ CTL activity was effective even against allogeneic HLA-A2+ U266 MM cells (p = 0.008). Consistent with CTL and NK cell activation, ENO1i increases expression of surface CD107a on CD8+ T and NK cells (p = 0.006 and p= 0.0112, respectively; n = 7). The combination of ENO1i and anti-PD-L1 Ab induces more robust allogeneic and autologous MM-specific CD8+ CTL activity than ENO1i alone (% MM lysis: ENO1i: 34%; ENO1i + anti-PD-L1 Ab: 54%; n = 7; p = 0.0013). Finally, the combination of ENOi and ACY-241 also enhances anti-MM immune responses (% MM lysis: ENO1i: 35%; ENO1i + ACY-241: 54%; n = 8; p = 0.0044). Conclusions Our preclinical data provide the basis for novel immune-based therapeutic approaches targeting immunosuppressive metabolic alpha-enolase enzyme ENO1 to restore anti-MM immunity and improve patient outcome. Disclosures Chauhan: Stemline Therapeutics: Consultancy; C4 Therapeutics.: Equity Ownership. Anderson:Sanofi-Aventis: Other: Advisory Board; Bristol-Myers Squibb: Other: Scientific Founder; Oncopep: Other: Scientific Founder; Amgen: Consultancy, Speakers Bureau; Janssen: Consultancy, Speakers Bureau; Takeda: Consultancy, Speakers Bureau; Celgene: Consultancy, Speakers Bureau.

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Fredenburg, Jeffrey A., and Michael P. Flynn. "Statistical Analysis of ENOB and Yield in Binary Weighted ADCs and DACS With Random Element Mismatch." IEEE Transactions on Circuits and Systems I: Regular Papers 59, no. 7 (July 2012): 1396–408. http://dx.doi.org/10.1109/tcsi.2011.2177006.

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