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1
Kiaei, Ali. "A 10 Gb/s receiver with equalizer and clock and data recovery circuit /." May be available electronically:, 2009. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
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Guzeev, Andrew. "Use of equalization and echo canceling on circuit board wires." Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1466.
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Advances in CMOS technology have resulted in increased clock fre-quencies, even exceeding 3GHz. At the same time, frequencies on most board wires are 125-800MHz. It is especially problematic in modern computer mem-ory buses and high speed telecommunication devices, such as switches and routers operating at 10Gb/s on its ports. It is believed that circuit board buses can be used up to about 20GHz, but there is a problem with Intersymbol Inter-ference (ISI) causing distortion of transmitted symbols by multiple reflections.
Actually, the circuit board bus behaves like a passive low pass filter with unknown (perhaps changing) transfer characteristic. The problem of ISI was solved some time ago in the telecommunication area. With use of adaptive equalizers it is possible to increase throughput of a long distance communication channel dramatically.
But the microprocessor bus has certain differences from telecommunica-tion devices such as modems. First of all, the clock frequency on a bus is much higher than in modems. Secondly, a bus has a much more complex structure than a telecommunication channel. At the same time, we can’t use a lot of re-sources for bus maintaining.
The aim of the thesis work is to investigate the possibility of using adap-tive equalization on a bus, and the construction of a reasonable mathematical model of such an equalizer. Also limits of equalizationare examined and de-pendencies are derived.
3
Hernandez, Garduno David. "Analog integrated circuit design techniques for high-speed signal processing in communications systems." [College Station, Tex. : Texas A&M University, 2006. http://hdl.handle.net/1969.1/ETD-TAMU-1104.
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Fayed, Ayman Adel. "Adaptive techniques for analog and mixed signal integrated circuits." Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1097519730.
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Thesis (Ph. D.)--Ohio State University, 2004.Title from first page of PDF file. Document formatted into pages; contains xix, 232 p.; also includes graphics (some col.). Includes bibliographical references (p. 222-230).
5
Štěrba, Václav. "Návrh 10-ti kanálového equalizeru s optimalizací kmitočtové charakteristiky a spektrálním audio-analyzátorem." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-219896.
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This work deals with the design of a 10-zones equalizer with optimized frequency characteristics with a spectrum audio analyzer. In this work the problem of processing audio signals using equalization for filtering the interference frequencies, correction of frequency cover signal boost or suppression of the required zones of the audible spectrum are also analyzed. The influence of subjective perception of sound intensity of the audio signals reproduction and its use in working with equalizer is discussed too. The work describes the principles and usage of the audio-analyzer as a tool for the optimization of the audio equalization setting when ensuring the appropriate listening conditions of music reproduction, spoken word, sounds, etc. It also focuses on the signal source for testing audio-chains, their generation and measurement using the audio analyzer. The equalizer equipment, audio-analyzer generator of reference signals equipment and power supply are designed as a single unit.
6
Hrubý, Ondřej. "Gramofonový elektronkový zesilovač." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-413191.
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This master´s thesis deals with a design and simulation of an audio power phono amplifier using vakuum tubes. The frequency response of suggested solution should comply with the norm specified by RIAA. It also describes a vacuum tube basic description and also its advantages for audio applications and principle of usage a magnetodynamic pick-up. Last part contains a design of microprocessor system and power supply.
7
Hollis, Timothy M. "Circuit and modeling solutions for high-speed chip-to-chip communication /." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd1721.pdf.
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PORPORA, Francesco. "Design and Prototyping of Battery Management Systems for Lithium-ion Battery Packs." Doctoral thesis, Università degli studi di Cassino, 2021. http://hdl.handle.net/11580/83987.
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High-performance equalization circuits have to satisfy different requirements, including modularity, scalability, weight and volume, reliability, cost, hardware and software complexity. Currently, the design targets are mainly focused on minimizing the equalization time and the overall size of the circuit. This also implies the definition of a proper thermal management for dissipating the heat generated due to the high balancing currents that may be needed.
However, literature and industry standards do not address the problem of the optimal sizing of the equalization circuits, which is strongly affected by the operating conditions of the battery pack as well as the parameter variations of the components adopted. The original contribute proposed in this dissertation regards the definition of design methodologies for passive and active equalization circuits that take into account for relevant aspects of both battery pack and power electronics components. Firstly, the real operating conditions of both individual cells and the overall battery pack have been
considered in terms of cell technology, temperature, model calibration and voltage imbalances among the cells. Secondly, the real behavior of the components used for the specific equalization circuit and their parameter variations have be taken into account. In this way, a proper evaluation of the performance of the equalization circuits can be achieved by considering their functionalities in real operating conditions. In particular, design strategies have been proposed for four BMS architectures, one for each main equalization type, including passive, capacitor-based, inductor-based and transformed-based solutions. Moreover, a novel architecture for an active equalization circuit has been developed for the transformer-based equalizer, which allows for achieving a cells-to-cells energy transfer. Besides the development of design strategies for passive and active equalization circuits, real prototypes have been sized and implemented as well. In detail, a modular architecture for the passive equalizer of a 50HP electric kart and the novel active equalizer have been prototyped with the aim of validating their performance in real-world environments. These prototypes also allow for managing high-voltage battery packs or hybrid systems, which are composed by different technologies
of batteries (second life applications). Moreover, a detailed comparison between the prototypes developed has been carried out in order to highlight their main features in different operating conditions, including charging, discharging and idle state.
9
Digvadekar, Ashish A. "A sub 1 V bandgap reference circuit /." Online version of thesis, 2005. https://ritdml.rit.edu/dspace/handle/1850/2595.
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Lee, Kil-Hoon. "Design of signal integrity enhancement circuits." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/37191.
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This dissertation is aimed at examining signal integrity degradation factors and realizing signal integrity enhancement circuits for both wired and wireless communication systems. For wired communication systems, an optical coherent system employing an electrical equalization circuit is studied as a way of extending the transmission distance limited by optical fiber dispersion mechanisms. System simulation of the optical coherent receiver combined with the feed-forward equalizers is performed to determine the design specification of the equalizer circuit. The equalization circuit is designed and implemented in a 0.18 µm complementary metal-oxide semiconductor (CMOS) process and demonstrates the capability to extend the transmission reach of long-haul optical systems over single-mode fiber to 600 km. Additionally, for wireless applications, signal integrity issues found in a full-duplex wireless communication network are examined. Full-duplex wireless systems are subject to interference from their own transmitter leakage signals; thus, a transmitter leakage cancellation circuit is designed and implemented in a 0.18 µm CMOS technology. The proposed cancellation circuit is integrated with a low-noise amplifier and demonstrates over 20 dB of transmitter leakage signal suppression.
11
Bartholomew, David Ray. "Design of a High Speed Mixed Signal CMOS Mutliplying Circuit." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd362.pdf.
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Klubus, Jan. "Elektronické filtrační obvody s obecnými kmitočtovými charakteristikami." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-413252.
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Master’s thesis deals with the issue of electronic filtering circuits with arbitrary frequency characteristics. First part of the thesis describes theoretical basis. Second part explores the possibilities of design procedures for filters with arbitrary frequency characteristics. Design procedures are demonstrated on examples accordingly to the presented methods, including their circuit implementation and computer simulation to verify the correctness of theoretical assumptions. Thesis also explores the possibilities of tuning circuit structures and electronic setting for characteristics using controllable active elements.
13
Hong, Zheng-Hao, and 洪政豪. "25Gbps Equalizer and Clock and Data Recovery Circuit." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/90291761985777164559.
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碩士國立交通大學
電子工程學系 電子研究所
102
This paper describes a 25-Gb/s receiver comprising of a continuous time linear equalizer followed by a 2 tap decision feedback equalizer embedded clock and data recovery circuit. The hybrid half-rate CDR facilitates ISI and jitter suppression over 19 Gbps-25Gbps operation. A quadrature relaxation oscillator provides the sampling phases without bulky inductors. Fabricated in a 40 nm CMOS technology, the whole receiver consumes 84.5 mW from 1.2 V supply with a core area of 0.09 mm2.
14
Chiu, Chi-Chun, and 邱繼群. "A Neat Circuit Realizing Differential-Mode Equalizer and Common-Mode Filter." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/77139953724646686599.
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碩士國立臺灣大學
電信工程學研究所
105
With the clock rate of the CPU increasing to the GHz frequency level, problems that are not very critical in the past become more serious in the high-speed (Gbit/s) data/signal transmission systems. Good differential signal and effective suppression of common mode noise are two vital factors in the high-speed signal transmission system to maintain high quality signal integrity. The aim of this thesis is to propose a structure composed of a low impedance line connected with resistors between two high impedance lines to achieve the function of equalizer and common mode filter, which is different from conventional passive equalizer with only equalization function. The fundamental of this structure is mainly based on the intermediate open circuit properties in the differential line to achieve the common mode filter function. Meanwhile, due to the intermediate short circuit characteristic, the resistor can be grounded to suppress low frequency signal can achieve equalization effect. In addition, the circuit structures with different parameters are analyzed and equivalent models are proposed to compare with experimental and simulation results. In the measurement, the proposed structure exhibits excellent common mode noise suppression behavior. Under differential mode transmission, the intrinsically closed eye diagram is significantly improved and can be re-open.
15
Lin, You-Ping, and 林祐平. "Implementation of Equalizer and Timing Recovery Circuit for 1Gbps Automotive Ethernet Transmission." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/m6624v.
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碩士國立中央大學
電機工程學系
107
In order to develop an IEEE 802.3bp™-2016 compatible next generation gigabit Ethernet transceiver for automotive environment, the algorithms and circuits for channel equalization and timing recovery are presented in this thesis. In order to overcome the harmful inter-symbol interference (ISI), feedforward equalizer and decision feedback equalizer are employed to deal with pre-cursor and post-cursor of inter-symbol interference, respectively. Since the wired channels are slow time-variant, the low complexity Least Mean Square (LMS) algorithm can be adopted to update the coefficients of equalizer. In timing recovery, Phase-Lock Loop (PLL) will overcome two factors that are resulted from channel response and the clock mismatch between AD/DA converters, respectively. Furthermore, the phenomenon induced by the interaction of equalization and timing recovery is combated by the proposed timing recovery approach. Finally, this design is coded on Xilinx ISE Design Suite, verified on SMIMS VeriEnterprise Xilinx FPGA and Design Compiler. And then the proposed design is implemented in 40nm CMOS technology.
16
Huang, Wen-Chieh, and 黃文杰. "Clock and Data Recovery Circuit and Equalizer for High-Speed Serial-Link Receiver." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/90238237373551825752.
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碩士國立交通大學
電子研究所
100
With the advances in information technology, the demand of high speed transmission increase with each passing day. But the limitation bandwidth of the channel will causes the inter-symbol interference (ISI) when the data passes through the channel. ISI may cause wrong symbol detection. Therefore, the equalizer, which can be used to compensate for the channel loss, play an important role in high speed transmission. In this thesis, we propose a high speed serial link receiver that operates at 8 Gbps. The receiver includes an analog equalizer, a decision feedback equalizer(DFE) and a clock and data recovery circuit (CDR). The analog equalizer provides gain peaking at high frequency by putting an additional pole in the feedback path. The decision feedback equalizer will adjust the coefficient adaptively by sign-sign LMS algorithm to cancel the post-cursor ISI. Using soft-decision architecture will enhance the operation speed of the decision feedback equalizer. The clock and data recovery circuit can adjust the phase of the clock signal by using a phase interpolator. The phase detector of the CDR will let the clock phase lock at proper position by detecting the slope of the data. Finally, we also add an SSCG clock tracking function in the receiver. Implemented in a 55nm CMOS technology, the area is 1.0x1.85 mm2 including PAD, the chip consumes 65.9mW from 1V supply.
17
Yao, Chang-Hung, and 姚昌宏. "Design of Equalizer and Timing Recovery Circuit for IEEE Std 802.3bwTM-2015 Automotive Ethernet Receiver." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/u73gxs.
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碩士國立中央大學
電機工程學系
107
This research develops a proprietary decoding algorithm based on IEEE Std 802.3bwTM-2015[1] specification for digital Ethernet receiver in automotive Ethernet transmission and focuses on equalizer algorithms, timing recovery circuits and digital circuit design. Because the automotive Ethernet channel is dispersion channel, the equalizer architecture uses a modified Constant Modulus Algorithm (CMA) [2] in forward equalizer which has lower complexity and a Decision Directed (DD) [3] algorithm in decision feedback equalizer[4] The forward equalizer is used for eliminating pre-cursor and decision feedback equalizer is used for eliminating post-cursor. In the part of timing recovery circuits, the Mueller and Müller algorithm [5] is employed to find timing phase. In addition, the adaptive canceler equalizer (ACE) [6]is adopted to make channel information approximate to sinc function and then benefit for the Mueller and Müller algorithm. At last, the digital circuits of proposed equalizer and timing recovery circuit are simulated through Verilog HDL, implemented in TSMC 40 nanometer process and verified on the SMIMS VeriEnterprise Xilinx FPGA.
18
Tasi, Ming-Shiung, and 蔡明雄. "Blind Equalizer and Timing Recovery Circuit Design for 100Mbps Receiver of Mixed Copper/Fiber EFM Systems." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/00082450140751639973.
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碩士國立中央大學
電機工程研究所
94
In recent years, all kinds of network application have been develoed, and bandwidth is not satisfied with appetite of consumers. From Modem to present Asymmetric Digital Subscriber Line(ADSL) and Cable Modem, the bottleneck is user’s bandwidth develop(First Mile/Last Mile). The speed is unable to promote, and the price of the ethernet service is a very heavy burden to users. If ethernet connects directly to user, then the ethernet signal will transmit to user. Hence, this will save unnecessary transmit equipment, bandwidth and has at least 10 Mbps data rate. We build EFM receiver simulation platform utilizing Matlab with finite wordlength. This simulation includes blind equalizer, timing recovery loop. In this simulation, equalizer coefficients convergence and does not need any training sequence. This equalizer can operate at least at data rate of 100Mbps with system requirement, where a 9bit ADC is used for sampling the receiver signal. And, we utilize some techniques to reduce the circuit area .The timing recovery loop contains timing extracting circuit, loop filter and NCO. The timing error detects from equalizer output. We utilize PLL and NCO to adjust sampling phase of ADC. The correction range of timing recovery loop is ±200ppm.
19
Lin, Yen-Chen, and 林彥辰. "A 3-Gb/s 1/3-Rate Fully Differential Clock and Data Recovery Circuit with an Adaptive Equalizer." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/9tp493.
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碩士國立中興大學
電機工程學系所
106
Due to the rapid development of semiconductor process in recent years, the operating speed of the overall circuit increases progressively, and the display quality of consumer electronics, too. The video streaming applications develop rapidly between mobile devices and TVs, from the early resolution 480P(640×480) to the current mainstream Full HD 1080P(1920×1080), resulting in that, the high-speed display interface must achieve a higher transmission rate to satisfy the high-definition video. In order to achieve the next generation Ultra HD 4K2K(3840×2160) specification, the high-speed interface used in large display panel have replaced from early multi-drop systems to point-to-point systems for higher speed and lower power consumption. In the first part, this thesis proposes a 3-Gb/s equalizer with adaptive swing controller that compensates for the large display panel channel loss of 24-dB at 1.5GHz. In order to solve the different amplitude between input and output of limiting amplifier, and tradeoff between high-frequency and low-frequency compensation issue, we use adaptive swing controller technique. The test chip was implemented in UMC 0.18-μm 1P6M CMOS technology. It works at power supply 1.8-V with 27-mW. The core area is 0.12-(mm)^2, and output peak-to-peak jitter is 0.256-UI. In the second part, the thesis proposes a 3-Gb/s clock and data recovery with adaptive equalizer. In order to achieve high speed, lower power consumption and jitter, we propose a 1/3-rate sampling technique, and the entire system architecture is made up by fully differential structure. The test chip was implemented in UMC 0.18-μm 1P6M CMOS technology. It works at power supply 1.8-V and sampling rate is 1Gb/s with 112-mW. The core area is 0.36-(mm)^2, and peak-to-peak jitter of recovery clock is 5.07-ps, and recovery data of 1-Gb/s peak-to-peak jitter is 5.31、4.75、4.23-ps, respectively.
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Chou, Wen-Hsiung, and 周文雄. "Charging Circuit of Intelligent Equalized Battery." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/90910931378092003279.
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碩士國立高雄應用科技大學
電子與資訊工程研究所碩士班
95
The object of this thesis is to research the methodology of fast charging equalization management of series-connected batteries to improve efficiency under the consideration of the environmental protection, the life of the battery and the economic cost. Because the difference of characteristics of the battery and all different kinds of fast charging way will cause the battery degradation beforehand under the recycle charging and discharging due to imbalance charging between string batteries. The charge imbalance will cause some batteries being over-charged or over-discharged which will causes accelerate aging of battery life. It’s necessary to develop charge technology to equalize each electric potential difference of battery to improve the efficiency of charging and discharging and lengthen usable life of the battery. This text use a switching mode power converter with three steps charging mode, constant current charging, constant voltage charging and floating charging, to increase the charging efficiency. Using a microprocessor in this converter to detect voltage and examine each battery state, those signals will feedback to microprocessor to control conductive switch alternately to equalize charge capacity of batteries between maximum and minimum battery voltage difference after cycle charging. After test each function of charging cycle using this charger, we can know the microprocessor audit voltage difference and calculate to conduct the minimum battery charging circuit with trickle charging current to increase battery voltage or turn off the charging circuit to decrease battery voltage to minimized the difference of each battery. The test records show that the difference is 0.29V without equalized circuit and 0.11V with equalized circuit so it had improved 0.18V after end of charging process which prove this equalized circuit can work effectively. A battery pack with series-connected lead-acid batteries is used as an example to illustrate the operation and characteristic of the balance charging circuit. But the circuit does not limit using on the specific battery, modifying the control software of the microprocessor can be applicable to nickel cadmium, nickel hydrogen or the lithium battery.
21
Chiang, Chin-Che, and 江晉哲. "Design of High-speed Circuit Board for Optical Receivers with Equalizers." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/274459.
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碩士國立臺灣科技大學
光電工程研究所
106
The transmission of high-data-rate signals usually encounters the signal distortion problems from insufficient bandwidth in the transmitters, receivers, or channels. Electric equalization is the frequently used scheme to overcome the bandwidth limitation. In this thesis we realize 25-Gb/s optical receiver modules by designing a high-speed PCB for the receiver circuit which includes a clock/data recovery (CDR), continuous-time linear equalizer (CTLE), and the circuit board connecting to a receiver optical subassembly (ROSA). By adjusting the operating conditions of the transmitter optical subassembly (TOSA) to vary the signal amplitude, the effect of using an equalizer in the high-speed receiver is investigated. It was found that by increasing the bias voltage of the electro absorption modulator(EAM) in the TOSA to obtain a larger extinction ratio(ER) for the optical output signals, the signal quality can be much improved by equalization even if the intersection of the optical signal eye diagram deviates from the half point. However, further increasing the EAM bias may increase the power penalty due to the rise of optical insertion loss and the low intersection point of the eye diagram that is too close to the zero level. Under this condition, the signal can be severely distorted after passing through the optical fiber. Therefore, the use of CTLE still needs to avoid the signal distortion caused by overmodulation. We can obtain higher ER by using higher signal amplitude, but a higher signal amplitude uses more nonlinear section of EAM, which will lead to more signal distortion and degrade the effectiveness of CTLE.
22
Tsai, Yu-Chang, and 蔡玉章. "Design and Implementation of Adaptive Equalizer and Clock Synchronization Circuits for Wired-Line Transceivers." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/36621637792779281065.
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博士國立中央大學
電機工程研究所
99
In high-speed transceivers, phase-locked loops (PLLs) and delay-locked loops (DLLs) are used as clock generators to avoid clock skew. In the transmitter, the clock synchronization circuits are used to provide the clock signal to the serializer. Therefore, the data can be transmitted from the parallel data to the serial data. In the receiver, the clock synchronization circuits provide the reference clock signal to the clock and data recovery circuit. In addition, the clock synchronization circuits provide the clock signal to the deserializer. Therefore, the data can be transferred from serial data to parallel data. The solar battery provides the 0.5 V supply voltage. Therefore, low-voltage and low power consumption integrated circuits have become more and more important. In high-speed systems, the data is sent from the transmitter and passes through the channel. The channel loss causes the inter-symbol interference (ISI) when the data passes through the channel. The eye diagram of the data is closed. Therefore, the equalizer can be used to compensate for the channel loss in the receiver so that the receiver can receive the data correctly. First, a low-jitter PLL is proposed for 10 Gbps high speed wired-line transceiver applications. The PLL provides 2.5 GHz, eight-phase output clock to the transceiver. The new variable delay cell (VDC) for the voltage-controlled oscillator (VCO) achieves a wide-range of output frequencies and a low noise sensitivity with low KVCO. The PLL consists of a self-adjustment circuit (SAC), which protects the PLL from variations in the process, voltage and temperature (PVT). The PLL is implemented in 0.13 μm CMOS technology. The PLL output jitter is 2.83 ps (rms). The total power dissipation is 21 mW at a 2.5 GHz output frequency, and the core area is 0.08 mm^2. Next, an inductorless PLL is proposed for low-power consumption applications. The PLL is suitable for the solar battery, which provides a 0.5 V supply voltage. A new charge pump (CP) circuit affords a low leakage current and high speed operation. A low-voltage voltage-controlled oscillator (LV-VCO) composed of 4-stage delay cells and a low-voltage segmented current mirror (LV-SCM) achieves a low voltage-controlled oscillator gain (KVCO), a wide tuning range, and good linearity. The LV-SCM generates more current within a small area by switching the body rather than the gate. The PLL is implemented in standard 90 nm CMOS with regular VT (RVT) devices. Its output jitter is 2.22 ps (rms). The phase noise is −87 dBc/Hz at a 1 MHz offset from a 2.24 GHz center frequency. The total power dissipation at a 2.24 GHz output frequency, and with a 0.5 V power supply is 2.08 mW (excluding the buffers). The core area is 0.074 mm^2. To solve the ISI effect while the data passes through the channel, an equalizer can be added in the receiver. Finally, this dissertation also proposed an analog adaptive equalizer to compensate for the channel loss. This equalizing filter uses low-voltage zero generators (LVZGs) to generate high-frequency gain boosting without inductors. The spectrum-balancing technique eliminates the need for a slicer. The power detector combines current steering techniques and a pre-amplifier circuit to enhance the voltage swing. The equalizer can compensate for the channel loss of 14 dB at 2.5 GHz. This design consumes 17.6 mW (excluding the output buffers) at a 1.6 V supply voltage with an output swing of 560 mV (pk-pk). The occupied area is 0.1 mm^2 (including output buffers), and the output peak-to-peak jitter is 0.28 UI. In this dissertation, the proposed clock synchronization circuits can be used in high-speed wired-line transceivers. They provide a clock signal and phases to other circuits for correct operation. The analog equalizer compensates for the channel loss when the high-speed data passes through the channel.
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Ng, George Chung Fai. "Distributed Circuit Techniques for Equalization of Short Multimode Fiber Links." Thesis, 2008. http://hdl.handle.net/1807/11156.
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Electronic dispersion compensation (EDC) of intermodal dispersion on short multimode fiber (MMF) links operating at 40 Gb/s is investigated through system level simulations and the design of two analog integrated circuit (IC) equalizers. System simulations using worst-case MMF link models show the effectiveness of a 2-tap baud spaced finite impulse response (FIR) equalizer for 40-m links, and a second-order Tbaud/2 infinite impulse response (IIR) equalizer for 50-m links. An IIR filter topology suitable for IC implementation with double loops and multiple delay sections was developed. The 2-tap FIR and the IIR equalizer are implemented in UMC 0.13-um and STM 90-nm CMOS processes respectively. Measurements demonstrate the FIR and IIR equalizing 38-Gb/s and 30-Gb/s cable channels respectively. To the author's knowledge, the double-loop multi-delay IIR equalizer is the first integrated traveling-wave equalizer utilizing poles as a means of frequency boosting, contrasting the conventional FIR technique of utilizing zeros.
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Hsieh, Chang-Lin, and 謝長霖. "Tens-Gb/s Decision-Feedback Equalizers and Clock and Data Recovery Circuits for High-Speed Wire-Line Communications." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/76237838755883185856.
Full textAbstract:
博士國立臺灣大學
電子工程學研究所
100
This dissertation focuses on the circuit design of the tens-Gb/s receiver front-end. This dissertation consists of four parts, the first part is a wide range clock and data recovery (CDR) circuit. The CDR circuit is implemented in 0.13um CMOS process, and it covers the operation frequency from 1Gb/s to 16Gb/s. By using the proposed bidirectional FD, the frequency acquisition process is automatically accomplished without resetting the VCO to reduce the acquisition time and it works for the various run-length data. In the second part, a 40Gb/s DFE is realized by 65nm CMOS process. The DFE adopts an adder by using the back-gate feedback technique to achieve a high operation speed and power efficiency. In the third part, a 30Gb/s cascaded DFE is fabricated in 65nm CMOS process by the proposed merged adder/DFF structure. This cascade DFE improves the performance of the re-timed data than a one-tap DFE without any speed penalty. In the fourth part, A 40Gb/s adaptive receiver using a linear equalizer and a merged half-rate DFE/CDR circuit is fabricated in a 65nm process. The proposed receiver not only reduces the loadings of the linear equalizer and the VCO, but also improves the jitter performance of the retimed data and recovery clock and power consumption.
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Dhanasekaran, Vijayakumar. "Baseband analog circuits in deep-submicron cmos technologies targeted for mobile multimedia." 2008. http://hdl.handle.net/1969.1/ETD-TAMU-2947.
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Three main analog circuit building blocks that are important for a mixed-signal
system are investigated in this work. New building blocks with emphasis on power
efficiency and compatibility with deep-submicron technology are proposed and
experimental results from prototype integrated circuits are presented.
Firstly, a 1.1GHz, 5th order, active-LC, Butterworth wideband equalizer that
controls inter-symbol interference and provides anti-alias filtering for the subsequent
analog to digital converter is presented. The equalizer design is based on a new series
LC resonator biquad whose power efficiency is analytically shown to be better than a
conventional Gm-C biquad. A prototype equalizer is fabricated in a standard 0.18μm
CMOS technology. It is experimentally verified to achieve an equalization gain
programmable over a 0-23dB range, 47dB SNR and -48dB IM3 while consuming 72mW
of power. This corresponds to more than 7 times improvement in power efficiency over
conventional Gm-C equalizers.
Secondly, a load capacitance aware compensation for 3-stage amplifiers is
presented. A class-AB 16W headphone driver designed using this scheme in 130nm technology is experimentally shown to handle 1pF to 22nF capacitive load while
consuming as low as 1.2mW of quiescent power. It can deliver a maximum RMS power
of 20mW to the load with -84.8dB THD and 92dB peak SNR, and it occupies a small
area of 0.1mm2. The power consumption is reduced by about 10 times compared to
drivers that can support such a wide range of capacitive loads.
Thirdly, a novel approach to design of ADC in deep-submicron technology is
described. The presented technique enables the usage of time-to-digital converter (TDC)
in a delta-sigma modulator in a manner that takes advantage of its high timing precision
while noise-shaping the error due to its limited time resolution. A prototype ADC
designed based on this deep-submicron technology friendly architecture was fabricated
in a 65nm digital CMOS technology. The ADC is experimentally shown to achieve
68dB dynamic range in 20MHz signal bandwidth while consuming 10.5mW of power. It
is projected to reduce power and improve speed with technology scaling.