Relevant bibliographies by topics / Equivalent Oxide Thickness - EOT

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  2. Dissertations / Theses
  3. Conference papers

Academic literature on the topic 'Equivalent Oxide Thickness - EOT'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Equivalent Oxide Thickness - EOT"

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Kim, Tae-Woo. "Effects of Equivalent-Oxide-Thickness and Fin-Width Scaling on In0.53Ga0.47As Tri-Gate Metal-Oxide-Semiconductor-Field-Effect-Transistors with Al2O3/HfO2 for Low-Power Logic Applications." Electronics 9, no. 1 (2019): 29. http://dx.doi.org/10.3390/electronics9010029.

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We created tri-gate sub-100 nm In0.53Ga0.47As metal-oxide-semiconductor-field-effect-transistors (MOSFETs) with a bi-layer Al2O3/HfO2 gate stack and investigated the scaling effects on equivalent-oxide-thickness (EOT) and fin-width (Wfin) at gate lengths of sub-100 nm. For Lg = 60 nm In0.53Ga0.47As tri-gate MOSFETs, EOT and Wfin scaling were effective for improving electrostatic immunities such as subthreshold swing and drain-induced-barrier-lowering. Reliability characterization for In0.53Ga0.47As Tri-Gate MOSFETs using constant-voltage-stress (CVS) at 300K demonstrates slightly worse VT degr
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Colombo, Luigi, Jim Chambers, and Hiroaki “Hiro” Niimi. "Gate Dielectric Process Technology for the Sub-1 nm Equivalent Oxide Thickness (EOT) Era." Electrochemical Society Interface 16, no. 3 (2007): 51–55. http://dx.doi.org/10.1149/2.f07073if.

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Chen, C. H., Y. K. Fang, C. W. Yang, et al. "Determination of deep ultrathin equivalent oxide thickness (EOT) from measuring flat-band C-V curve." IEEE Transactions on Electron Devices 49, no. 4 (2002): 695–98. http://dx.doi.org/10.1109/16.992882.

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Hosoi, Takuji, Yusuke Uenishi, Shuhei Mitani, et al. "Dielectric Properties of Thermally Grown SiO2 on 4H-SiC(0001) Substrates." Materials Science Forum 740-742 (January 2013): 605–8. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.605.

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The bulk properties of thermally grown SiO2 on 4H-SiC(0001) substrates were thoroughly investigated by capacitance-voltage (C-V) measurement, atomic force microscopy (AFM), spectroscopic ellipsometry (SE), x-ray photoelectron spectroscopy (XPS), and secondary ion mass spectrometry (SIMS). The equivalent oxide thickness (EOT) extracted from the capacitance-voltage (C-V) characteristics of TiN/SiO2 capacitors was proportional to the physical thickness (Tphys), but the slope of the linear fit was found to be 1.11, indicating that the permittivity of SiO2 on 4H-SiC formed by thermal oxidation is o
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Felício, A. G., José Alexandre Diniz, J. Godoy Fo., I. Doi, M. A. A. Pudenzi, and Jacobus W. Swart. "The Effect of Nitrogen Concentration at Oxynitride Gate Insulators Formed by 28N2 + Implantation into Silicon with Additional Conventional or Rapid Thermal Oxidation." Journal of Integrated Circuits and Systems 1, no. 2 (2004): 41–47. http://dx.doi.org/10.29292/jics.v1i2.263.

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Silicon oxynitride (SiOxNy) insulators have been obtained by nitrogen ion implantation into Si substrates prior to conventional or rapid thermal oxidation. These films have been used as gate insulators in nMOSFETs and MOS capacitors. nMOSFET electrical characteristics, such as field effect mobility between 390 cm2/Vs and 530 cm2/Vs, and sub-threshold slope between 70 mV/decade and 150 mV/decade, were obtained. MOS capacitors were used to obtain capacitance-voltage (C-V) and current-voltage (I-V) measurements. The Equivalent Oxide Thickness (EOT) of the films were obtained from C-V curves, resu
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Sahari, Siti Kudnie, Muhammad Kashif, Norsuzailina Mohamed Sutan, et al. "Growth kinetic and composition of the interfacial layer for RF sputtering Al2O3 layer on germanium." Microelectronics International 34, no. 2 (2017): 64–68. http://dx.doi.org/10.1108/mi-12-2015-0099.

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Purpose The quality of GeOx–Ge interface and the equivalent oxide thickness (EOT) are the main issues in fabricating high-k/Ge gate stack due to the low-k of GeOx interfacial layer (IL). Therefore, a precise study of the formation of GeOx IL and its contribution to EOT is of utmost importance. In this study, the GeOx ILs were formed through post-oxidation annealing of sputtered Al2O3 on the Ge substrate. The purpose of this paper is to report on growth kinetics and composition of IL between Al2O3 and Ge for HCl- and HF-last Ge surface. Design/methodology/approach After wet chemical cleaning wi
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Watanabe, Heiji, Katsuhiro Kutsuki, Iori Hideshima, Gaku Okamoto, Takuji Hosoi, and Takayoshi Shimura. "Improved Electrical Properties and Thermal Stability of GeON Gate Dielectrics Formed by Plasma Nitridation of Ultrathin Oxides on Ge(100)." Key Engineering Materials 470 (February 2011): 152–57. http://dx.doi.org/10.4028/www.scientific.net/kem.470.152.

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We demonstrated the impact of plasma nitridation on thermally grown GeO2 for the purposes of obtaining high-quality germanium oxynitride (GeON) gate dielectrics. Physical characterizations revealed the formation of a nitrogen-rich surface layer on the ultrathin oxide, while keeping an abrupt GeO2/Ge interface without a transition layer. The thermal stability of the GeON layer was significantly improved over that of the pure oxide. We also found that although the GeO2 layer is vulnerable to air exposure, a nitrogen-rich layer suppresses electrical degradation and provides excellent insulating p
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A.Hamid, Farah, Afiq Hamzah, N. Ezaila Alias, and Razali Ismail. "Optimization of high-k composite dielectric materials of variable oxide thickness tunnel barrier for nonvolatile memory." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 2 (2019): 765. http://dx.doi.org/10.11591/ijeecs.v14.i2.pp765-772.

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<span>Downscaling the tunnel oxide thickness has become one of the innovative solutions to minimize the operational voltage with better the programming/erasing (P/E) operation time. However, the downscaling technique faces several challenges where the conventional SiO<sub>2</sub> tunnel layer has reached its limit. But a practical alternative has been introduced; Variable Oxide Thickness (VARIOT) technology in flash memory has been promising. VARIOT is one of tunnel barrier engineering technology for incorporating the high-k dielectric materials as a composite tunnel barrier.
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Lin, K. C., C. H. Chou, J. Y. Chen, C. J. Li, J. Y. Huang, and C. H. Liu. "The Effect of Ternary Material (Zr, Y, and O) High-k Gate Dielectrics." Advanced Materials Research 699 (May 2013): 422–25. http://dx.doi.org/10.4028/www.scientific.net/amr.699.422.

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In this research, the Y2O3 layer is doped with the zirconium through co-sputtering and rapid thermal annealing (RTA) at 550°C, 700°C, and 850°C. Then the Al electrode is deposited to generate two kinds of structures, Al/ZrN/ Y2O3/ Y2O3+Zr/p-Si and Al/ZrN/ Y2O3+Zr/ Y2O3/p-Si. According to the XRD results, when Zr was doped on the upper layer, the crystallization phenomenon was more significant than Zr was at the bottom layer, meaning that Zr may influence the diffusion of the oxygen. The AFM also shows that the surface roughness of Zr has worse performance. For the electrical property, the infl
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Noor, Fatimah A., Mikrajuddin Abdullah, and Khairurrijal. "The Effects of Nitrogen Concentration in TiNx and the Thickness of HfSiOxN to the Tunneling Currents in Isotropic TiNx/HfSiOxN/SiO2/Si(100) Capacitors." Applied Mechanics and Materials 481 (December 2013): 121–24. http://dx.doi.org/10.4028/www.scientific.net/amm.481.121.

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In this paper, we have computed electron tunneling currents in TiNx/HfSiOxN/SiO2/Si (100) MOS capacitors by including a coupling term between transverse and longitudinal kinetic energies which is represented by an electron phase velocity in the gate. The effective mass of the substrate is considered as an isotropic mass. The transmittance was analytically calculated by employing an Airy-wavefunction approach, and the obtained transmittance was then utilized to calculate the tunneling current for different nitrogen compositions in the TiNx metal gate and the equivalent oxide thicknesses (EOTs)
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Dissertations / Theses on the topic "Equivalent Oxide Thickness - EOT"

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Pelloquin, Sylvain. "LaAlO3 amorphe déposé par épitaxie par jets moléculaires sur silicium comme alternative pour la grille high-κ des transistors CMOS". Phd thesis, INSA de Lyon, 2011. http://tel.archives-ouvertes.fr/tel-00694351.

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Depuis l'invention du transistor MOS à effet de champ dans les années 60, l'exploitation de cette brique élémentaire a permis une évolution exponentielle du domaine de la microélectronique, avec une course effrénée vers la miniaturisation des dispositifs électroniques CMOS. Dans ce contexte, l'introduction des oxydes "high-κ" (notamment HfO2) a permis de franchir la barrière sub-nanométrique de l'EOT (Equivalent Oxide Thickness) pour l'oxyde de grille. Les travaux actuels concernent notamment la recherche de matériaux "high-κ" et de procédés qui permettraient d'avoir une interface abrupte, the
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Tung, Kuan-wen, and 東冠妏. "Barium Doped Titanium Silicon Oxide with Equivalent Oxide Thickness below 1 nm Prepared by Liquid Phase Deposition." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/61297065521657627828.

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博士<br>國立中山大學<br>電機工程學系研究所<br>93<br>High dielectric constant barium doped titanium silicon oxide films with equivalent oxide thickness below 1 nm can be prepared by liquid phase deposition. We learn from this research that the deposition rate of titanium silicon oxide films can be much enhanced by nitric acid incorporation, and the dielectric constant of materials can be increased by the dipole polarization from barium. The key parameter for the deposition rate, refractive index, and the dielectric constant of barium doped titanium silicon oxide is the molarity of barium nitrate. The electrical
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Hsiao, Tsung-Cheng, and 蕭宗錚. "On the Minimum Equivalent Oxide Thickness of High-k Dielectrics for advanced CMOS Technology." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/98688900309544433264.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>95<br>For continuous scaling down of advanced ULSI CMOS technology into deep sub-100-nm regime, further reduction in gate oxide (SiO2 and SiONx) thickness is required. Performance gains obtained from thinning oxide thickness as low as 1 nm no longer exists because gate tunneling leakage becomes a substantial power drain. Under the circumstance, other alternative gate dielectrics with high-dielectric constants (k) must be considered, which allow the use of a physically thicker film while acting electrically as a thin dielectric. Nevertheless, as scaling down of CMO
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Hou, Tzu-Ching, and 侯姿清. "Study of 1nm-oxide-equivalent-thickness La2O3 and HfO2 Multilayer Composite Oxides on In0.53Ga0.47As for MOS Capacitor Application." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/7z75t4.

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碩士<br>國立交通大學<br>光電系統研究所<br>103<br>In this study, La2O3 and HfO2 were used as gate oxides on InGaAs metal oxide semiconductor (MOS) capacitor. There are many advantages of Hafnium–Lanthanum-Based gate dielectrics, such as high dielectric constant, large energy bandgap and high crystallization temperature, etc. These results suggest that the (Hf–La)Ox system will become a potential candidate for advanced CMOS applications The composite oxide was formed by MBD depositing 4 layers of La2O3 (1nm)/ HfO2(1nm) and 8 layers of La2O3 (0.5nm)/ HfO2(0.5nm) on InGaAs with varied post deposition annealin
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Lee, Kun-Yu, та 李昆育. "The Study of Sub-Nanometer Equivalent Oxide Thickness of MBE and ALD Grown High κ Gate Dielectrics on Silicon and In0.53Ga0.47As Substrates". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/32141202705303068548.

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博士<br>國立清華大學<br>材料科學工程學系<br>96<br>Metal oxide semiconductor (MOS) capacitors that incorporated high κ materials of HfO2 and Al2O3 are fabricated by Molecular beam epitaxy (MBE) and Atomic layer deposition (ALD) on Silicon and InGaAs substrates. The achievements in this work are to minimize the thickness of the interfacial layer at oxide/semiconductor and attain sub-nanometer equivalent oxide thickness (EOT) value in the MOS diodes. In Silicon phase, MBE grown high κ dielectrics of Al2O3 and HfO2 are employed as templates to suppress effectively the oxide/Si interfacial layer formation during t
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Conference papers on the topic "Equivalent Oxide Thickness - EOT"

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Ni, Kai, Atanu Saha, Wriddhi Chakraborty та ін. "Equivalent Oxide Thickness (EOT) Scaling With Hafnium Zirconium Oxide High-κ Dielectric Near Morphotropic Phase Boundary". У 2019 IEEE International Electron Devices Meeting (IEDM). IEEE, 2019. http://dx.doi.org/10.1109/iedm19573.2019.8993495.

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Hudec, B., M. Tapajna, K. Husekova, J. Aarik, A. Aidla, and K. Frohlich. "Low equivalent oxide thickness metal/insulator/metal structures for DRAM application." In 2008 International Conference on Advanced Semiconductor Devices and Microsystems (ASDAM). IEEE, 2008. http://dx.doi.org/10.1109/asdam.2008.4743296.

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Li, Dong Hua, Il Han Park, Seongjae Cho, et al. "Effects of equivalent oxide thickness on bandgap-engineered SONOS flash memory." In 2009 IEEE Nanotechnology Materials and Devices Conference (NMDC). IEEE, 2009. http://dx.doi.org/10.1109/nmdc.2009.5167538.

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Chen, H. W., H. W. Hsu, S. Y. Chen, H. S. Huang, M. C. Wang, and C. H. Liu. "Current conduction mechanisms of 0.65 nm equivalent oxide thickness HfZrLaO thin films." In 2011 IEEE 4th International Nanoelectronics Conference (INEC). IEEE, 2011. http://dx.doi.org/10.1109/inec.2011.5991686.

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Li, Qiang, Jae-Hoon Han, Tsung-En Lee, Shinichi Takagi, and Mitsuru Takenaka. "Equivalent oxide thickness scaling for efficient III-V/Si hybrid MOS optical phase shifter." In 2019 Compound Semiconductor Week (CSW). IEEE, 2019. http://dx.doi.org/10.1109/iciprm.2019.8819195.

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Han, Kaizhen, Subhranu Samanta, Chen Sun, Jishen Zhang, Zijie Zheng, and Xiao Gong. "Top-Gate Short Channel Amorphous Indium-Gallium-Zinc-Oxide Thin Film Transistors with Sub-1.2 nm Equivalent Oxide Thickness." In 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). IEEE, 2021. http://dx.doi.org/10.1109/edtm50988.2021.9421049.

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Haraguchi, Keiichi, Kazuyoshi Torii, Jiro Yugami, and Takahiro Onai. "A TiO2 Gate Insulator of a 1-nm Equivalent Oxide Thickness Deposited by Electron-Beam Evaporation." In 1999 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 1999. http://dx.doi.org/10.7567/ssdm.1999.lb-1-3.

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Morita, Y., S. Migita, W. Mizubayashi, and H. Ota. "Extremely scaled (~0.2 nm) equivalent oxide thickness of higher-k ALD-HfO2 gate stacks." In 2011 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2011. http://dx.doi.org/10.7567/ssdm.2011.e-9-4l.

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Do, H., Q. Luc, M. Ha, et al. "Equivalent Oxide Thickness Self-Reduction and Work Function Self-Alignment Using Ti/AlN Doping Layer for Mo/HfO2/InGaAs NMOS." In 2016 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2016. http://dx.doi.org/10.7567/ssdm.2016.ps-6-03.

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Kane, Terence, Michael P. Tenney, Andrew Erickson, and Peter Harris. "Calibration of Nanoprobe Capacitance-Voltage Spectroscopy (NCVS)." In ISTFA 2008. ASM International, 2008. http://dx.doi.org/10.31399/asm.cp.istfa2008p0204.

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Abstract MOSFET devices are routinely measured at the probe pad level with conventional capacitance-voltage (CV) measurement instruments. Such measurements are done at the front end of line (FEOL) and back end of line (BEOL) process completion levels. The CV data is used to monitor the process and verify certain parametrics such as effective oxide thickness (EOT), Tox, gate drain overlap capacitance (Miller capacitance), trapped charge, diffusion/halo implant oxide leakage, doping concentration, threshold implant level and many others. This type of testing is treated at length in the classic t
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