Relevant bibliographies by topics / Error-Detection Circuits

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Error-Detection Circuits'

Author: Grafiati
Published: 4 June 2021
Last updated: 8 February 2022

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Journal articles on the topic "Error-Detection Circuits"

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HAGHPARAST, MAJID, and KEIVAN NAVI. "NOVEL REVERSIBLE FAULT TOLERANT ERROR CODING AND DETECTION CIRCUITS." International Journal of Quantum Information 09, no. 02 (March 2011): 723–38. http://dx.doi.org/10.1142/s0219749911007447.

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Reversible logic is an emerging area of research, having applications in nanotechnology, low power CMOS design, quantum computing, and DNA computing. In this paper, two different parity-preserving reversible error coding and detection circuits are studied. First we propose two new reversible Hamming code generator circuits. One of them is parity-preserve. We also propose a new parity-preserving reversible Hamming code error detector circuit. The proposed parity-preserving reversible Hamming code generator (PPHCG) and error detector circuits provide single error correction–double error detection (SEC–DED). The designs are better than the existing counterparts in terms of quantum cost (QC), number of constant inputs, and number of garbage outputs. Then we propose parity-preserving reversible cyclic code encoder/decoder circuits for the first time. A parity-preserving reversible D flip-flop is also proposed. Equivalent quantum representation of two parity-preserving 4 ∗ 4 reversible gates, IG, and PPHCG, are also proposed. We show for the first time that IG has a QC of only 7 and PPHCG has a QC of only 6.
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Sapozhnikov, Valeriy, Vladimir Sapozhnikov, Dmitriy Efanov, and Ruslan Abdullaev. "The specificities of organization of concurrent error detection systems for combinational circuits based on polynomial codes." Proceedings of Petersburg Transport University, no. 3 (September 20, 2018): 432–45. http://dx.doi.org/10.20295/1815-588x-2018-3-432-445.

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Objective: To study the specificities of polynomial codes application during the organization of concurrent error detection systems for combinational logic circuits of automation and computer engineering. Methods: The methods of information theory and coding, the theory of discrete devices and diagnostic engineering of discrete systems were applied. Results: The possibilities of using polynomial codes in the process of combinational logic circuits control organization were analyzed. Some essential properties, inherent in generator polynomials, which make it possible to synthesize self-checking circuits of concurrent error detection systems, were pointed out. Particularly, one of such essential properties is the presence of a constant term in a generator polynomial (otherwise, all the required test patterns are not generated for a complete check of a coding device). An example of concurrent error detection sys- tem implementation for a combinational circuit was given. Some experimental data on error detection in LGSynth’89 combinational benchmarks were described. Practical importance: The use of polynomial codes for combinational circuit control makes it possible to synthesize self-checking discrete devices of automation and computer engineering.
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Almukhaizim, Sobeeh, Petros Drineas, and Yiorgos Makris. "Compaction-based concurrent error detection for digital circuits." Microelectronics Journal 36, no. 9 (September 2005): 856–62. http://dx.doi.org/10.1016/j.mejo.2005.03.009.

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Wei, Shugang, and Kensuke Shimizu. "Residue Checker with Signed-Digit Arithmetic for Error Detection of Arithmetic Circuits." Journal of Circuits, Systems and Computers 12, no. 01 (February 2003): 41–53. http://dx.doi.org/10.1142/s0218126603000842.

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This paper presents a fast residue checker for the error detection of arithmetic circuits. The residue checker consists of a number of residue arithmetic circuits such as adders, multipliers and binary-to-residue converters based on radix-two signed-digit (SD) number arithmetic. The proposed modulo m (m = 2p ± 1) adder is designed with a p-digit SD adder, so that the modulo m addition time is independent of the word length of operands. The modulo m multiplier and binary-to-residue number converter are constructed with a binary tree structure of the modulo m SD adders. Thus, the modulo m multiplication is performed in a time proportional to log 2 p and an n-bit binary number is converted into a p-digit SD residue number, n ≫ p, in a time proportional to log 2(n/p). By using the presented residue arithmetic circuits, the error detection can be performed in real-time for a large product-sum circuit.
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Han, Zhen Wei, and Kei Fei Song. "Error Analysis of the Micro Temperature Control System." Applied Mechanics and Materials 241-244 (December 2012): 364–67. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.364.

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In order to improve the measurement accuracy of optical detection instruments, temperature control circuits for narrow band-pass filters are given, and the error analysis is applied to temperature control circuits.The principle of a temperature measurement circuit is studied and the method of a driver circuit is described. A variety of influencing factors of temperature control accuracy are discussed. Moreover, for these error factors, improvement measures are given to reduce the nonlinear error. Finally, circuit parameter error is quantified to propose a calculation method for margin of error in a temperature control system.
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Pour Aryan, N., L. Heiß, D. Schmitt-Landsiedel, G. Georgakos, and M. Wirnshofer. "Comparison of in-situ delay monitors for use in Adaptive Voltage Scaling." Advances in Radio Science 10 (September 18, 2012): 215–20. http://dx.doi.org/10.5194/ars-10-215-2012.

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Abstract. In Adaptive Voltage Scaling (AVS) the supply voltage of digital circuits is tuned according to the circuit's actual operating condition, which enables dynamic compensation to PVTA variations. By exploiting the excessive safety margins added in state-of-the-art worst-case designs considerable power saving is achieved. In our approach, the operating condition of the circuit is monitored by in-situ delay monitors. This paper presents different designs to implement the in-situ delay monitors capable of detecting late but still non-erroneous transitions, called Pre-Errors. The developed Pre-Error monitors are integrated in a 16 bit multiplier test circuit and the resulting Pre-Error AVS system is modeled by a Markov chain in order to determine the power saving potential of each Pre-Error detection approach.
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Dmitriev, A., V. Saposhnikov, Vl Saposhnikov, M. Goessel, Vl Moshanin, and A. Morosov. "New Self-dual Circuits for Error Detection and Testing." VLSI Design 11, no. 1 (January 1, 2000): 1–21. http://dx.doi.org/10.1155/2000/84720.

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In this paper new methods for the transformation of a given combinational circuit into a self-dual circuit based on the notion of a self-dual complement are investigated. The large variety of self-dual complements can be utilized to optimize the transformed self-dual circuit. Self-dual duplication and self-dual parity prediction are considered in detail. As a method for the reduction of self-dual outputs, output space compaction of self-dual outputs is considered. For the first time we also describe in this paper how a self-dual circuit can be modified into a self-dual fault-secure circuit.
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Busaba, Fadi, and Parag K. Lala. "Techniques for Self-Checking Combinational Logic Synthesis." VLSI Design 2, no. 3 (January 1, 1994): 209–21. http://dx.doi.org/10.1155/1994/29238.

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This paper presents techniques for designing arbitrary combinational circuits so that any single stuck-at fault will result in either single bit error or unidirectional multibit error at the output. If the outputs are encoded using Berger code or m-out-of-n code, then the proposed technique will enable on-line detection of faults in the circuit. An algorithm for indicating whether a certain fault at an input will create bidirectional error at the output is presented. An input encoding algorithm and an output encoding algorithm that ensure that every fault will either produce single bit error or unidirectional multibit error at the output are proposed. If there are no input fault which produces bidirectional error, no internal stuck-at fault will result in such an error irrespective of the way the circuit is implemented. Thus, only single bit or unidirectional multibit error will result in the presence of a fault in the circuit. The proposed techniques have been applied to MCNC benchmark circuits and the overhead is estimated.
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Touba, N. A., and E. J. McCluskey. "Logic synthesis of multilevel circuits with concurrent error detection." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16, no. 7 (July 1997): 783–89. http://dx.doi.org/10.1109/43.644041.

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Tung, Dam Minh, Nguyen Van Toan, and Jeong-Gun Lee. "A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA." Electronics 9, no. 4 (April 10, 2020): 633. http://dx.doi.org/10.3390/electronics9040633.

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Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.
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Dissertations / Theses on the topic "Error-Detection Circuits"

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Morozov, Alexei. "Optimierung von Fehlererkennungsschaltungen auf der Grundlage von komplementären Ergänzungen für 1-aus-3 und Berger Codes." Phd thesis, Universität Potsdam, 2005. http://opus.kobv.de/ubp/volltexte/2005/536/.

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Die Dissertation stellt eine neue Herangehensweise an die Lösung der Aufgabe der funktionalen Diagnostik digitaler Systeme vor. In dieser Arbeit wird eine neue Methode für die Fehlererkennung vorgeschlagen, basierend auf der Logischen Ergänzung und der Verwendung von Berger-Codes und dem 1-aus-3 Code. Die neue Fehlererkennungsmethode der Logischen Ergänzung gestattet einen hohen Optimierungsgrad der benötigten Realisationsfläche der konstruierten Fehlererkennungsschaltungen. Außerdem ist eins der wichtigen in dieser Dissertation gelösten Probleme die Synthese vollständig selbstprüfender Schaltungen.
In this dissertation concurrent checking by use of a complementary circuit for an 1-out-of-n Codes and Berger-Code is investigated. For an arbitrarily given combinational circuit necessary and sufficient conditions for the existence of a totally self-checking checker are derived for the first time.
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Rhod, Eduardo Luis. "Proposal of two solutions to cope with the faulty behavior of circuits in future technologies." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/16086.

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A diminuição no tamanho dos dispositivos nas tecnologias do futuro traz consigo um grande aumento na taxa de erros dos circuitos, na lógica combinacional e seqüencial. Apesar de algumas potenciais soluções começarem a ser investigadas pela comunidade, a busca por circuitos tolerantes a erros induzidos por radiação, sem penalidades no desempenho, área ou potência, ainda é um assunto de pesquisa em aberto. Este trabalho propõe duas soluções para lidar com este comportamento imprevisível das tecnologias futuras: a primeira solução, chamada MemProc, é uma arquitetura baseada em memória que propõe reduzir a taxa de falhas de aplicações embarcadas micro-controladas. Esta solução baseia-se no uso de memórias magnéticas, que são tolerantes a falhas induzidas por radiação, e área de circuito combinacional reduzida para melhorar a confiabilidade ao processar quaisquer aplicações. A segunda solução proposta aqui é uma implementação de um IP de infra-estrutura para o processador MIPS indicada para sistemas em chip confiáveis, devido a sua adaptação rápida e por permitir diferentes níveis de robustez para a aplicação. A segunda solução é também indicada para sistemas em que nem o hardware nem o software podem ser modificados. Os resultados dos experimentos mostram que ambas as soluções melhoram a confiabilidade do sistema que fazem parte com custos aceitáveis e até, no caso da MemProc, melhora o desempenho da aplicação.
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions are being investigated by the community, the search for circuits tolerant to radiation induced errors, without performance, area, or power penalties, is still an open research issue. This work proposes two solutions to cope with this unpredictable behavior of future technologies: the first solution, called MemProc, is a memory based architecture proposed to reduce the fault rate of embedded microcontrolled applications. This solution relies in the use magnetic memories, which are tolerant to radiation induced failures, and reduced combinational circuit area to improve the reliability when processing any application. The second solution proposed here is an infrastructure IP implementation for the MIPS architecture indicated for reliable systems-on-chip due to its fast adaptation and different levels of application hardening that are allowed. The second solution is also indicated for systems where neither the hardware nor the software can be modified. The experimental results show that both solutions improve the reliability of the system they take part with affordable overheads and even, as in the case of the MemProc solution, improving the performance results.
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Rhod, Eduardo Luis. "Quaternary CLB a falul tolerant quaternary FPGA." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/72925.

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A diminuição no tamanho dos transistores vem aumentando cada vez mais o número de funções que os dispositivos eletrônicos podem realizar. Apesar da diminuição do tamanho mínimo dos transistores, a velocidade máxima dos circuitos não consegue seguir a mesma taxa de aumento. Um dos grandes culpados apontados pelos pesquisadores são as interconexões entre os transistores e também entre os componentes. O aumento no número de interconexões dos circuitos traz consigo um significativo aumento do cosumo de energia, aumento do atraso de propagação dos sinais, além de um aumento da complexidade e custo do projeto dos circuitos integrados. Como uma possível solução a este problema é proposta a utilização de lógica multivalorada, mais especificamente, a lógica quaternária. Os dispositivos FPGAs são caracterizados principalmente pela grande flexibilidade que oferecem aos projetistas de sistemas digitais. Entretanto, com o avanço nas tecnologias de fabricação de circuitos integrados e diminuição das dimensões de fabricação, os problemas relacionados ao grande número de interconexões são uma preocupação para as próximas tecnologias de FPGAs. As tecnologias menores que 90nm possuem um grande aumento na taxa de erros dos circuitos, na lógica combinacional e sequencial. Apesar de algumas potenciais soluções começara a ser investigadas pela comunidade, a busca por circuitos tolerantes a erros induzidos por radiação, sem penalidades no desempenho, área ou potência, ainda é um assunto de pesquisa em aberto. Este trabalho propõe o uso de circuitos quaternários com modificações para tolerar falhas provenientes de eventos transientes. Como principal contribuição deste trabalho destaca-se o desenvolvimento de uma CLB (do inglês Configurable Logic Block) quaternária capaz de suportar eventos transientes e, na possibilidade de um erro, evitá-lo ou corrigi-lo.
The decrease in transistor size is increasing the number of functions that can be performed by the electronic devices. Despite this reduction in the transistors minimum size, the circuit’s speed does not follow the same rate. One of the major reasons pointed out by researchers are the interconnections between the transistors and between the components. The increase in the number of circuit interconnections brings a significant increase in energy consumption, propagation delay of signals, and an increase in the complexity and cost of new technologies IC designs. As a possible solution to this problem the use of multivalued logic is being proposed, more specifically, the quaternary logic. FPGA devices are characterized mainly by offering greater flexibility to designers of digital systems. However, with the advance in IC manufacturing technologies and the reduced size of the minimum fabricated dimensions, the problems related to the large number of interconnections are a concern for future technologies of FPGAs. The sub 90nm technologies have a large increase in the error rate of its functions for the combinational and sequential logic. Although potential solutions are being investigated by the community, the search for circuits tolerant to radiation induced errors, without performance, area, or power penalties, is still an open research issue. This work proposes the use of quaternary circuits with modifications to tolerate faults from transient events. The main contribution of this work is the development of a quaternary CLB (Configurable Logic Block) able to withstand transient events and the occurrence of soft errors.
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Mohamed, Mohamed Hassan Wahba Ayman. "Diagnostic des erreurs de conception dans les circuits digitaux : le cas des erreurs simples." Grenoble 1, 1997. http://www.theses.fr/1997GRE10086.

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Le diagnostic automatique des erreurs de conception est un probleme important dans le domaine de la cao. Bien que des outils automatises de synthese soient employes pour generer des structures de circuits correctes-par-construction, celles-ci sont souvent modifiees manuellement pour refleter des petites modifications faites sur la specification, ou pour ameliorer certaines caracteristiques critiques de la conception. Les outils de verification peuvent reveler l'existence d'erreurs, mais ils ne donnent aucune information sur leurs emplacements ou la facon de les corriger. Ces outils generent seulement quelques contres-exemples qui mettent en evidence l'erreur. Les concepteurs utilisent ces contre-exemples pour diagnostiquer manuellement leur conception. Le diagnostic manuel est un processus tres lent et tres couteux. Le temps de diagnostic peut etre egal, voire superieur, au temps de conception. Nous presentons dans cette these de nouveaux algorithmes pour la localisation et la correction automatique des erreurs simples de conception dans les circuits logiques sous l'hypothese d'une seule erreur. Les erreurs traitees ici sont : le remplacement d'un composant dans les circuits combinatoires et sequentiels, et une erreur de connexion dans les circuits combinatoires. Le modele d'une seule erreur exige une strategie de verification frequente, dans laquelle la conception est verifiee apres chaque modification, pour que la probabilite d'insertion de plus d'une erreur ne soit pas trop elevee. Notre approche consiste a simuler et analyser automatiquement le circuit sous l'application de vecteurs de test que nous produisons specialement pour accelerer le diagnostic. Nous avons realise deux logiciels prototypes bases sur ces algorithmes. Ccds est l'outil de diagnostic pour les circuits combinatoires, et scds est l'outil de diagnostic pour les circuits sequentiels. Ces outils sont actuellement integres dans l'environnement de preuves prevail#t#m.
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Bousselam, Kaouthar. "Résistance des circuits cryptographiques aux attaques en faute." Phd thesis, Université Montpellier II - Sciences et Techniques du Languedoc, 2012. http://tel.archives-ouvertes.fr/tel-00771357.

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Les blocs cryptographiques utilisés dans les circuits intégrés implémentent des algorithmes prouvés robustes contre la cryptanalyse. Toutefois des manipulations malveillantes contre le circuit lui-même peuvent permettre de retrouver les données secrètes. Entre autres, les attaques dites " en fautes " se sont révélés particulièrement efficaces. Leur principe consiste à injecter une faute dans le circuit (à l'aide d'un faisceau laser par exemple), ce qui produira un résultat erroné et à le comparer à un résultat correct. Il est donc essentiel de pouvoir détecter ces erreurs lors du fonctionnement du circuit. Les travaux de thèse présentées dans ce mémoire ont pour objet la détection concurrente d'erreurs dans les circuits cryptographique, en prenant comme support l'implantation du standard d'encryption symétrique l'Advanced Encryption standard " AES ". Nous analysons donc plusieurs schémas de détection d'erreur basés sur de la redondance d'information (code détecteur), certains issus de la littérature, d'autres originaux utilisant un double code de parité entrée-sortie permettant l'amélioration du taux de détection d'erreur dans ces circuits. Nous présentons aussi une étude montrant que le choix du type du code détecteur le plus approprié dépend, d'une part du type d'erreur exploitable pouvant être produite par un attaquant, et d'autre part du type d'implémentation du circuit à protéger. Les circuits cryptographiques sont également la cible d'autres attaques, et en particulier les attaques par analyse de consommation. Les contre mesures proposés jusqu'à lors pour un type d'attaques, se révèlent la plupart du temps néfastes sur la résistance du circuit face à d'autres types d'attaque. Nous proposons dans cette thèse une contre mesure conjointe qui protège le circuit à la fois contre les attaques en fautes et les attaques par analyse de consommation.
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Mirchandani, Chandru, David Fisher, and Parminder Ghuman. "Cost Beneficial Solution for High Rate Data Processing." International Foundation for Telemetering, 1999. http://hdl.handle.net/10150/606836.

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International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada
GSFC in keeping with the tenets of NASA has been aggressively investigating new technologies for spacecraft and ground communications and processing. The application of these technologies, together with standardized telemetry formats, make it possible to build systems that provide high-performance at low cost in a short development cycle. The High Rate Telemetry Acquisition System (HRTAS) Prototype is one such effort that has validated Goddard's push towards faster, better and cheaper. The HRTAS system architecture is based on the Peripheral Component Interconnect (PCI) bus and VLSI Application-Specific Integrated Circuits (ASICs). These ASICs perform frame synchronization, bit-transition density decoding, cyclic redundancy code (CRC) error checking, Reed-Solomon error detection/correction, data unit sorting, packet extraction, annotation and other service processing. This processing in performed at rates of up to and greater than 150 Mbps sustained using a high-end performance workstation running standard UNIX O/S, (DEC 4100 with DEC UNIX or better). ASICs are also used for the digital reception of Intermediate Frequency (IF) telemetry as well as the spacecraft command interface for commands and data simulations. To improve the efficiency of the back-end processing, the level zero processing sorting element is being developed. This will provide a complete hardware solution to extracting and sorting source data units and making these available in separate files on a remote disk system. Research is on going to extend this development to higher levels of the science data processing pipeline. The fact that level 1 and higher processing is instrument dependent; an acceleration approach utilizing ASICs is not feasible. The advent of field programmable gate array (FPGA) based computing, referred to as adaptive or reconfigurable computing, provides a processing performance close to ASIC levels while maintaining much of the programmability of traditional microprocessor based systems. This adaptive computing paradigm has been successfully demonstrated and its cost performance validated, to make it a viable technology for the level one and higher processing element for the HRTAS. Higher levels of processing are defined as the extraction of useful information from source telemetry data. This information has to be made available to the science data user in a very short period of time. This paper will describe this low cost solution for high rate data processing at level one and higher processing levels. The paper will further discuss the cost-benefit of this technology in terms of cost, schedule, reliability and performance.
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Rymer, J. W. "ERROR DETECTION AND CORRECTION -- AN EMPIRICAL METHOD FOR EVALUATING TECHNIQUES." International Foundation for Telemetering, 2000. http://hdl.handle.net/10150/606802.

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International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California
This paper describes a method for evaluating error correction techniques for applicability to the flight testing of aircraft. No statistical or math assumptions about the channel or sources of error are used. An empirical method is shown which allows direct “with and without” comparative evaluation of correction techniques. A method was developed to extract error sequences from actual test data independent of the source of the dropouts. Hardware was built to allow a stored error sequence to be repetitively applied to test data. Results are shown for error sequences extracted from a variety of actual test data. The effectiveness of Reed-Solomon (R-S) encoding and interleaving is shown. Test bed hardware configuration is described. Criteria are suggested for worthwhile correction techniques and suggestions are made for future investigation.
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Mein, Gordon F. (Gordon Francis) Carleton University Dissertation Engineering Electrical. "A study of common logic design errors and methods for their detection." Ottawa, 1988.

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Grymel, Martin-Thomas. "Error control with binary cyclic codes." Thesis, University of Manchester, 2013. https://www.research.manchester.ac.uk/portal/en/theses/error-control-with-binary-cyclic-codes(a5750b4a-e4d6-49a8-915b-3e015387ad36).html.

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Error-control codes provide a mechanism to increase the reliability of digital data being processed, transmitted, or stored under noisy conditions. Cyclic codes constitute an important class of error-control code, offering powerful error detection and correction capabilities. They can easily be generated and verified in hardware, which makes them particularly well suited to the practical use as error detecting codes.A cyclic code is based on a generator polynomial which determines its properties including the specific error detection strength. The optimal choice of polynomial depends on many factors that may be influenced by the underlying application. It is therefore advantageous to employ programmable cyclic code hardware that allows a flexible choice of polynomial to be applied to different requirements. A novel method is presented in this thesis to realise programmable cyclic code circuits that are fast, energy-efficient and minimise implementation resources.It can be shown that the correction of a single-bit error on the basis of a cyclic code is equivalent to the solution of an instance of the discrete logarithm problem. A new approach is proposed for computing discrete logarithms; this leads to a generic deterministic algorithm for analysed group orders that equal Mersenne numbers with an exponent of a power of two. The algorithm exhibits a worst-case runtime in the order of the square root of the group order and constant space requirements.This thesis establishes new relationships for finite fields that are represented as the polynomial ring over the binary field modulo a primitive polynomial. With a subset of these properties, a novel approach is developed for the solution of the discrete logarithm in the multiplicative groups of these fields. This leads to a deterministic algorithm for small group orders that has linear space and linearithmic time requirements in the degree of defining polynomial, enabling an efficient correction of single-bit errors based on the corresponding cyclic codes.
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Schweitzer, Alexis. "Amélioration du niveau de sécurité des systèmes électroniques programmables par application du concept d'analyse de signature." Nancy 1, 1987. http://www.theses.fr/1987NAN10034.

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Mise en oeuvre d'un analyseur de signature en ligne destiné à la sécurité des systèmes électroniques programmables. Présentation d'une méthodologie générale pour une utilisation optimale du modèle analyseur
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Books on the topic "Error-Detection Circuits"

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Gössel, Michael. Error detection circuits. London: McGraw-Hill, 1993.

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Book chapters on the topic "Error-Detection Circuits"

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Gössel, Michael. "Optimal Error Detection Circuits for Sequential Circuits with Observable States." In Fault-Tolerant Computing Systems, 171–80. Berlin, Heidelberg: Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/978-3-642-76930-6_15.

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Holmquist, Lawrence P., and L. L. Kinney. "Concurrent error detection in sequential circuits using convolutional codes." In Applied Algebra, Algebraic Algorithms and Error-Correcting Codes, 183–94. Berlin, Heidelberg: Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/3-540-54522-0_107.

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Margaria, Tiziana. "Fully automatic verification and error detection for parameterized iterative sequential circuits." In Tools and Algorithms for the Construction and Analysis of Systems, 258–77. Berlin, Heidelberg: Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/3-540-61042-1_49.

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Tripathi, Divya, and Subodh Wairya. "A Cost-Efficient Magnitude Comparator and Error Detection Circuits for Nano-Communication." In Inventive Systems and Control, 239–54. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-1395-1_19.

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Borowik, Grzegorz, and Andrzej Kraśniewski. "Trading-Off Error Detection Efficiency with Implementation Cost for Sequential Circuits Implemented with FPGAs." In Computer Aided Systems Theory – EUROCAST 2011, 327–34. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-27579-1_42.

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Aydos, Gökçe, and Görschwin Fey. "In-circuit Error Detection with Software-based Error Correction – An Alternative to TMR." In Formal Modeling and Verification of Cyber-Physical Systems, 272–74. Wiesbaden: Springer Fachmedien Wiesbaden, 2015. http://dx.doi.org/10.1007/978-3-658-09994-7_10.

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Dhiman, Sahil, Pushpinder Garg, Divya Sharma, and Chiranjoy Chattopadhyay. "Automatic Synthesis of Boolean Expression and Error Detection from Logic Circuit Sketches." In Communications in Computer and Information Science, 410–23. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-0020-2_36.

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"Decentralized Fault Detection in Wireless Sensor Network based on gaussian function error." In Sensors, Circuits & Instrumentation Systems, 13–26. De Gruyter Oldenbourg, 2017. http://dx.doi.org/10.1515/9783110470444-002.

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Sulc, Bohumil, and David Klimanek. "Evolutionary Algorithms in Supervision of Error-Free Control." In Soft Computing Applications for Database Technologies, 39–48. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-60566-814-7.ch003.

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Evolutionary algorithms are well known as optimization techniques, suitable for solving various kinds of problems (Ruano, 2005). The new application of evolutionary algorithms represents their use in the detection of biased control loop functions caused by controlled variable sensor discredibility (Klimanek, Sulc, 2005). Sensor discredibility occurs when a sensor transmitting values of the controlled variable provides inexact information, however the information is not absolutely faulty yet. The use of discredible sensors in control circuits may cause the real values of controlled variables to exceed the range of tolerated differences, whereas zero control error is being displayed. However, this is not the only negative consequence. Sometimes, sensor discredibility is accompanied with undesirable and hardly recognizable side effects. Most typical is an increase of harmful emission production in the case of combustion control, (Sulc, Klimanek, 2005). We have found that evolutionary algorithms are useful tools for solving the particular problem of finding a software-based way (so called software redundancy) of sensor discredibility detection. Software redundancy is a more economical way than the usual hardware redundancy, which is otherwise necessary in control loop protection against this small, invisible control error occurrence. New results from a long-term tracking residuum trends show that credibility loss can be forecasted. Operators can be warned in advance that the sensor measuring the controlled variable needs to be exchanged. This need can be effectively reflected in maintenance plans. Namely, the standard genetic algorithm and the simulated annealing algorithm have been successfully applied and tested to minimize the given cost function. By means of these algorithms, a newly developed method is able to detect controlled variable sensor discredibility. When applied to combustion processes, production of harmful emissions can be kept within accepted limits. The application of the used evolutionary algorithms inclusive terminology transfer in this application area can serve as an explanatory case study to help readers gain a better understanding of the how the evolutionary algorithms operate.
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Kaye, Phillip, Raymond Laflamme, and Michele Mosca. "Quantum Error Correction." In An Introduction to Quantum Computing. Oxford University Press, 2006. http://dx.doi.org/10.1093/oso/9780198570004.003.0013.

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A mathematical model of computation is an idealized abstraction. We design algorithms and perform analysis on the assumption that the mathematical operations we specify will be carried out exactly, and without error. Physical devices that implement an abstract model of computation are imperfect and of limited precision. For example, when a digital circuit is implemented on a physical circuit board, unwanted electrical noise in the environment may cause components to behave differently than expected, and may cause voltage levels (bit-values) to change. These sources of error must be controlled or compensated for, or else the resulting loss of efficiency may reduce the power of the information-processing device. If individual steps in a computation succeed with probability p, then a computation involving t sequential steps will have a success probability that decreases exponentially as pt. Although it may be impossible to eliminate the sources of errors, we can devise schemes to allow us to recover from errors using a reasonable amount of additional resources. Many classical digital computing devices use error-correcting codes to perform detection of and recovery from errors. The theory of error-correcting codes is itself a mathematical abstraction, but it is one that explicitly accounts for errors introduced by the imperfection and imprecision of realistic devices. This theory has proven extremely effective in allowing engineers to build computing devices that are resilient against errors. Quantum computers are more susceptible to errors than classical digital computers, because quantum mechanical systems are more delicate and more difficult to control. If large-scale quantum computers are to be possible, a theory of quantum error correction is needed. The discovery of quantum error correction has given researchers confidence that realistic large-scale quantum computing devices can be built despite the presence of errors. We begin by considering fundamental concepts for error correction in a classical setting. We will focus on three of these concepts: (a) the characterization of the error model, (b) the introduction of redundancy through encoding, and (c) an error recovery procedure. We will later see that these concepts generalize quite naturally for quantum error correction.
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Conference papers on the topic "Error-Detection Circuits"

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Ming, Hu, and Wang Yan. "MD5-Based Error Detection." In 2009 Pacific-Asia Conference on Circuits, Communications and Systems (PACCS). IEEE, 2009. http://dx.doi.org/10.1109/paccs.2009.147.

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Aydos, Gokce, and Goerschwin Fey. "Exploiting error detection latency for parity-based soft error detection." In 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2016. http://dx.doi.org/10.1109/ddecs.2016.7482440.

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Almukhaizim, Sobeeh, Sara Bunian, and Ozgur Sinanoglu. "Reconfigurable low-power Concurrent Error Detection in logic circuits." In 2010 5th International Design and Test Workshop (IDT). IEEE, 2010. http://dx.doi.org/10.1109/idt.2010.5724415.

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Keren, Osnat, Ilya Levin, Vladimir Ostrovsky, and Beni Abramov. "Arbitrary Error Detection in Combinational Circuits by Using Partitioning." In 2008 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. IEEE, 2008. http://dx.doi.org/10.1109/dft.2008.34.

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Almukhaizim, Sobeeh, Sara Bunian, and Ozgur Sinanoglu. "Reconfigurable low-power Concurrent Error Detection in logic circuits." In 2010 IEEE 16th International On-Line Testing Symposium (IOLTS 2010). IEEE, 2010. http://dx.doi.org/10.1109/iolts.2010.5560202.

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Kumar, Ashish, G. S. Visweswaran, and Kaushik Saha. "Low voltage error resilient SRAM using run-time error detection and correction." In ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference. IEEE, 2015. http://dx.doi.org/10.1109/esscirc.2015.7313895.

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Fujihashi, Chugo. "Correction method for optical-signal detection-error caused by quantum noise." In Integrated Optical Circuits, edited by Ka K. Wong. SPIE, 1991. http://dx.doi.org/10.1117/12.50900.

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Maingot, V., and R. Leveugle. "Error Detection Code Efficiency for Secure Chips." In 2006 13th IEEE International Conference on Electronics, Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/icecs.2006.379850.

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Levine, David, William E. Lynch, and Tho Le-Ngoc. "Observations on error detection in H.264." In 2007 Joint 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) and the IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007). IEEE, 2007. http://dx.doi.org/10.1109/mwscas.2007.4488698.

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Sayers, I. L., G. Russell, and D. J. Kinniment. "CEDREC - A Concurrent Error Detection Schema using Residue Codes." In Twelfth European Solid-State Circuits Conference. IEEE, 1986. http://dx.doi.org/10.1109/esscirc.1986.5468382.

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