Journal articles: 'Error-Detection Circuits'

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HAGHPARAST, MAJID, and KEIVAN NAVI. "NOVEL REVERSIBLE FAULT TOLERANT ERROR CODING AND DETECTION CIRCUITS." International Journal of Quantum Information 09, no. 02 (March 2011): 723–38. http://dx.doi.org/10.1142/s0219749911007447.

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Reversible logic is an emerging area of research, having applications in nanotechnology, low power CMOS design, quantum computing, and DNA computing. In this paper, two different parity-preserving reversible error coding and detection circuits are studied. First we propose two new reversible Hamming code generator circuits. One of them is parity-preserve. We also propose a new parity-preserving reversible Hamming code error detector circuit. The proposed parity-preserving reversible Hamming code generator (PPHCG) and error detector circuits provide single error correction–double error detection (SEC–DED). The designs are better than the existing counterparts in terms of quantum cost (QC), number of constant inputs, and number of garbage outputs. Then we propose parity-preserving reversible cyclic code encoder/decoder circuits for the first time. A parity-preserving reversible D flip-flop is also proposed. Equivalent quantum representation of two parity-preserving 4 ∗ 4 reversible gates, IG, and PPHCG, are also proposed. We show for the first time that IG has a QC of only 7 and PPHCG has a QC of only 6.

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Sapozhnikov, Valeriy, Vladimir Sapozhnikov, Dmitriy Efanov, and Ruslan Abdullaev. "The specificities of organization of concurrent error detection systems for combinational circuits based on polynomial codes." Proceedings of Petersburg Transport University, no. 3 (September 20, 2018): 432–45. http://dx.doi.org/10.20295/1815-588x-2018-3-432-445.

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Objective: To study the speciﬁcities of polynomial codes application during the organization of concurrent error detection systems for combinational logic circuits of automation and computer engineering. Methods: The methods of information theory and coding, the theory of discrete devices and diagnostic engineering of discrete systems were applied. Results: The possibilities of using polynomial codes in the process of combinational logic circuits control organization were analyzed. Some essential properties, inherent in generator polynomials, which make it possible to synthesize self-checking circuits of concurrent error detection systems, were pointed out. Particularly, one of such essential properties is the presence of a constant term in a generator polynomial (otherwise, all the required test patterns are not generated for a complete check of a coding device). An example of concurrent error detection sys- tem implementation for a combinational circuit was given. Some experimental data on error detection in LGSynth’89 combinational benchmarks were described. Practical importance: The use of polynomial codes for combinational circuit control makes it possible to synthesize self-checking discrete devices of automation and computer engineering.

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Almukhaizim, Sobeeh, Petros Drineas, and Yiorgos Makris. "Compaction-based concurrent error detection for digital circuits." Microelectronics Journal 36, no. 9 (September 2005): 856–62. http://dx.doi.org/10.1016/j.mejo.2005.03.009.

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Wei, Shugang, and Kensuke Shimizu. "Residue Checker with Signed-Digit Arithmetic for Error Detection of Arithmetic Circuits." Journal of Circuits, Systems and Computers 12, no. 01 (February 2003): 41–53. http://dx.doi.org/10.1142/s0218126603000842.

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This paper presents a fast residue checker for the error detection of arithmetic circuits. The residue checker consists of a number of residue arithmetic circuits such as adders, multipliers and binary-to-residue converters based on radix-two signed-digit (SD) number arithmetic. The proposed modulo m (m = 2p ± 1) adder is designed with a p-digit SD adder, so that the modulo m addition time is independent of the word length of operands. The modulo m multiplier and binary-to-residue number converter are constructed with a binary tree structure of the modulo m SD adders. Thus, the modulo m multiplication is performed in a time proportional to log 2 p and an n-bit binary number is converted into a p-digit SD residue number, n ≫ p, in a time proportional to log 2(n/p). By using the presented residue arithmetic circuits, the error detection can be performed in real-time for a large product-sum circuit.

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Han, Zhen Wei, and Kei Fei Song. "Error Analysis of the Micro Temperature Control System." Applied Mechanics and Materials 241-244 (December 2012): 364–67. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.364.

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In order to improve the measurement accuracy of optical detection instruments, temperature control circuits for narrow band-pass filters are given, and the error analysis is applied to temperature control circuits.The principle of a temperature measurement circuit is studied and the method of a driver circuit is described. A variety of influencing factors of temperature control accuracy are discussed. Moreover, for these error factors, improvement measures are given to reduce the nonlinear error. Finally, circuit parameter error is quantified to propose a calculation method for margin of error in a temperature control system.

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Pour Aryan, N., L. Heiß, D. Schmitt-Landsiedel, G. Georgakos, and M. Wirnshofer. "Comparison of in-situ delay monitors for use in Adaptive Voltage Scaling." Advances in Radio Science 10 (September 18, 2012): 215–20. http://dx.doi.org/10.5194/ars-10-215-2012.

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Abstract. In Adaptive Voltage Scaling (AVS) the supply voltage of digital circuits is tuned according to the circuit's actual operating condition, which enables dynamic compensation to PVTA variations. By exploiting the excessive safety margins added in state-of-the-art worst-case designs considerable power saving is achieved. In our approach, the operating condition of the circuit is monitored by in-situ delay monitors. This paper presents different designs to implement the in-situ delay monitors capable of detecting late but still non-erroneous transitions, called Pre-Errors. The developed Pre-Error monitors are integrated in a 16 bit multiplier test circuit and the resulting Pre-Error AVS system is modeled by a Markov chain in order to determine the power saving potential of each Pre-Error detection approach.

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Dmitriev, A., V. Saposhnikov, Vl Saposhnikov, M. Goessel, Vl Moshanin, and A. Morosov. "New Self-dual Circuits for Error Detection and Testing." VLSI Design 11, no. 1 (January 1, 2000): 1–21. http://dx.doi.org/10.1155/2000/84720.

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In this paper new methods for the transformation of a given combinational circuit into a self-dual circuit based on the notion of a self-dual complement are investigated. The large variety of self-dual complements can be utilized to optimize the transformed self-dual circuit. Self-dual duplication and self-dual parity prediction are considered in detail. As a method for the reduction of self-dual outputs, output space compaction of self-dual outputs is considered. For the first time we also describe in this paper how a self-dual circuit can be modified into a self-dual fault-secure circuit.

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Busaba, Fadi, and Parag K. Lala. "Techniques for Self-Checking Combinational Logic Synthesis." VLSI Design 2, no. 3 (January 1, 1994): 209–21. http://dx.doi.org/10.1155/1994/29238.

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This paper presents techniques for designing arbitrary combinational circuits so that any single stuck-at fault will result in either single bit error or unidirectional multibit error at the output. If the outputs are encoded using Berger code or m-out-of-n code, then the proposed technique will enable on-line detection of faults in the circuit. An algorithm for indicating whether a certain fault at an input will create bidirectional error at the output is presented. An input encoding algorithm and an output encoding algorithm that ensure that every fault will either produce single bit error or unidirectional multibit error at the output are proposed. If there are no input fault which produces bidirectional error, no internal stuck-at fault will result in such an error irrespective of the way the circuit is implemented. Thus, only single bit or unidirectional multibit error will result in the presence of a fault in the circuit. The proposed techniques have been applied to MCNC benchmark circuits and the overhead is estimated.

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Touba, N. A., and E. J. McCluskey. "Logic synthesis of multilevel circuits with concurrent error detection." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16, no. 7 (July 1997): 783–89. http://dx.doi.org/10.1109/43.644041.

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Tung, Dam Minh, Nguyen Van Toan, and Jeong-Gun Lee. "A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA." Electronics 9, no. 4 (April 10, 2020): 633. http://dx.doi.org/10.3390/electronics9040633.

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Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.

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Stempkovskiy, A. L., D. V. Telpukhov, A. I. Demeneva, and T. D. Zhukova. "DESIGN FLOW OF CONCURRENT ERROR DETECTION SCHEMES FOR COMBINATIONAL CIRCUITS." Vestnik of Ryazan State Radio Engineering University 65 (2018): 92–98. http://dx.doi.org/10.21667/1995-4565-2018-65-3-92-98.

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Brebner, Gordon. "Configurable array logic circuits for computing network error detection codes." Journal of VLSI signal processing systems for signal, image and video technology 6, no. 2 (August 1993): 101–17. http://dx.doi.org/10.1007/bf01607875.

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Yang, Zhixi, Xianbin Li, and Jun Yang. "Power Efficient and High-Accuracy Approximate Multiplier with Error Correction." Journal of Circuits, Systems and Computers 29, no. 15 (June 30, 2020): 2050241. http://dx.doi.org/10.1142/s0218126620502412.

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Approximate arithmetic circuits have been considered as an innovative circuit paradigm with improved performance for error-resilient applications which could tolerant certain loss of accuracy. In this paper, a novel approximate multiplier with a different scheme of partial product reduction is proposed. An analysis of accuracy (measured by error distance, pass rate and accuracy of amplitude) as well as circuit-based design metrics (power, delay and area, etc.) is utilized to assess the performance of the proposed approximate multiplier. Extensive simulation results show that the proposed design achieves a higher accuracy than the other approximate multipliers from the previous works. Moreover, the proposed design has a better performance under comprehensive comparisons taking both accuracy and circuit-related metrics into considerations. In addition, an error detection and correction (EDC) circuit is used to correct the approximate results to accurate results. Compared with the exact Wallace tree multiplier, the proposed approximate multiplier design with the error detection and correction circuit still has up to 15% and 10% saving for power and delay, respectively.

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Sapozhnikov, V. V., Vl V. Sapozhnikov, and D. V. Efanov. "The features of the concurrent error-detection systems of combinational logic circuits based on the search for groups of symmetrically-independent outputs construction." Automation on Transport 6, no. 4 (December 2020): 532–49. http://dx.doi.org/10.20295/2412-9186-2020-6-4-532-549.

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The authors of the article found that in the use of classical sum codes (Berger codes) and a some of their modifications in the combinational circuits testing organization it is possible to detect both unidirectional and part of non-unidirectional errors in the data vectors. It is shown that it is possible to search for such groups of outputs of combinational circuits where only symmetrical errors occur due to stuck at-faults of elements of the internal structure of the circuits. Such groups of outputs are designated as symmetrically-independent outputs (SI-groups of outputs). The conditions of belonging of the group of outputs of the combinational circuits to the SI-groups of outputs are determined. It is shown that each SI-group of outputs can be controlled using a separate testing subsystem based on the code with the detection of any non-symmetrical errors (in particular, and any non-symmetrical errors up to certain multiplicities). The ways of searching for SI-groups of outputs in the combinational circuits testing organization are presented

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Vuillot, Christophe. "Is error detection helpful on IBM 5Q chips?" Quantum Information and Computation 18, no. 11&12 (September 2018): 949–64. http://dx.doi.org/10.26421/qic18.11-12-4.

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This paper reports on experiments realized on several IBM~5Q chips which show evidence for the advantage of using error detection and fault-tolerant design of quantum circuits. We show an average improvement of the task of sampling from states that can be fault-tolerantly prepared in the [4,2,2] code, when using a fault-tolerant technique well suited to the layout of the chip. By showing that fault-tolerant quantum computation is already within our reach, the author hopes to encourage this approach.

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Rizzo, Roberto Giorgio, and Andrea Calimera. "Implementing Adaptive Voltage Over-Scaling: Algorithmic Noise Tolerance vs. Approximate Error Detection." Journal of Low Power Electronics and Applications 9, no. 2 (April 21, 2019): 17. http://dx.doi.org/10.3390/jlpea9020017.

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Adaptive Voltage Over-Scaling can be applied at run-time to reach the best tradeoff between quality of results and energy consumption. This strategy encompasses the concept of timing speculation through some level of approximation. How and on which part of the circuit to implement such approximation is an open issue. This work introduces a quantitative comparison between two complementary strategies: Algorithmic Noise Tolerance and Approximate Error Detection. The first implements a timing speculation by means approximate computing, while the latter exploits a more sophisticated approach that is based on the approximation of the error detection mechanism. The aim of this study was to provide both a qualitative and quantitative analysis on two real-life digital circuits mapped onto a state-of-the-art 28-nm CMOS technology.

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Hsu, Chih-Cheng, Masanori Hashimoto, and Mark Po-Hung Lin. "Minimizing detection-to-boosting latency toward low-power error-resilient circuits." Integration 58 (June 2017): 236–44. http://dx.doi.org/10.1016/j.vlsi.2017.01.002.

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Afzaal, Umar, Abdus Sami Hassan, and Jeong-A. Lee. "Improved error detection performance of logic implication checking in FPGA circuits." Microprocessors and Microsystems 78 (October 2020): 103179. http://dx.doi.org/10.1016/j.micpro.2020.103179.

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Sapozhnikov, V. V., Vl V. Sapozhnikov, D. V. Efanov, and V. V. Dmitriev. "New structures of the concurrent error detection systems for logic circuits." Automation and Remote Control 78, no. 2 (February 2017): 300–312. http://dx.doi.org/10.1134/s0005117917020096.

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Chatterjee, A., and R. K. Roy. "Concurrent error detection in nonlinear digital circuits using time-freeze linearization." IEEE Transactions on Computers 46, no. 11 (1997): 1208–18. http://dx.doi.org/10.1109/12.644296.

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Ismaeel, Asad A., and Melvin A. Breuer. "The probability of error detection in sequential circuits using random test vectors." Journal of Electronic Testing 1, no. 4 (January 1991): 245–56. http://dx.doi.org/10.1007/bf00136314.

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Hassan, Abdus, Umar Afzaal, Tooba Arifeen, and Jeong Lee. "Input-Aware Implication Selection Scheme Utilizing ATPG for Efficient Concurrent Error Detection." Electronics 7, no. 10 (October 17, 2018): 258. http://dx.doi.org/10.3390/electronics7100258.

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Recently, concurrent error detection enabled through invariant relationships between different wires in a circuit has been proposed. Because there are many such implications in a circuit, selection strategies have been developed to select the most valuable implications for inclusion in the checker hardware such that a sufficiently high probability of error detection ( P d e t e c t i o n ) is achieved. These algorithms, however, due to their heuristic nature cannot guarantee a lossless P d e t e c t i o n . In this paper, we develop a new input-aware implication selection algorithm with the help of ATPG which minimizes loss on P d e t e c t i o n . In our algorithm, the detectability of errors for each candidate implication is carefully evaluated using error prone vectors. The evaluation results are then utilized to select the most efficient candidates for achieving optimal P d e t e c t i o n . The experimental results on 15 representative combinatorial benchmark circuits from the MCNC benchmarks suite show that the implications selected from our algorithm achieve better P d e t e c t i o n in comparison to the state of the art. The proposed method also offers better performance, up to 41.10%, in terms of the proposed impact-level metric, which is the ratio of achieved P d e t e c t i o n to the implication count.

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Pawase, Ramesh, and Niteen P. Futane. "Intelligent and Analog CMOS ASIC Development of Angular Rate Error Compensation for MEMS Gyroscope." International Journal of Sensors, Wireless Communications and Control 9, no. 3 (July 30, 2019): 388–403. http://dx.doi.org/10.2174/2210327909666181210161551.

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Background & Objective: MEMS-based gyroscopes are used in angular rate detection where precision is an important parameter; however, gyroscope output is limited by angular rate error. For minimizing these types of non-idealities, conventional external hardware-based analog or digital circuits have limitations for using in compact applications. CMOS analog ASIC for angular rate error compensation is necessary as both MEMS-CMOS technologies are supplementary and compatible. Method: In this paper, the output of MEMS gyroscope is taken as input for the compensation circuit which results in compensated angular rate. ANN is used in intelligent compensation circuit for error reduction in which offline data is trained and minimum optimum error of MSE of 1.72e-4 is achieved. ANN uses tanh sigmoidal activation function and back propagation trained MLP model with three neurons in the hidden layer. The equivalent ANN is implemented by CMOS ASIC where each neuron is implemented using Gilbert multiplier cell, differential analog adder, and differential amplifier as tanh sigmoidal circuit using OrCAD-PSpice 10.5 with 0.35 μ m technology. These blocks consist of differential configuration which has the capability of common mode interference rejection as noise becomes comparable at lower values of input analog signal. The entire ASIC consumes 77.8 mW of power which is far less and compact in size as compared to available external hardware interface circuits. Result and Conclusion: MEMS gyroscope with proposed analog ASIC becomes smart sensor with ANN based intelligent interface circuit. The proposed compensation cum interface circuit gives the average angular rate error of 1.91% in the range of minimum 0% to maximum 27% leading to improved accuracy.

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Stankovic, Tatjana, Mile Stojcev, and Goran Djordjevic. "On VHDL synthesis of self-checking two-level combinational circuits." Facta universitatis - series: Electronics and Energetics 17, no. 1 (2004): 69–79. http://dx.doi.org/10.2298/fuee0401069s.

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Concurrent error detection (CED) is an important technique in the design of system in which dependability and data integrity are important. Using the separable code for CED has the advantage that no decoding is needed to get the normal output bits. In this paper, we address the problem of synthesizing totally self-checking two level combinational circuits starting from a VHDL description. Three schemes for CED are proposed. The first scheme uses duplication of a combinational logic with the addition of a totally self-checking comparator. The second scheme for synthesizing combinational circuits with CED uses Bose-Lin code. The third scheme is based on parity codes on the outputs of a combinational circuit. The area overheads and operating speed decreases for seven combinational circuits of standard architecture are reported in this paper.

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Krstić, Miloš, Stefan Weidling, Vladimir Petrović, and Egor S. Sogomonyan. "Enhanced architectures for soft error detection and correction in combinational and sequential circuits." Microelectronics Reliability 56 (January 2016): 212–20. http://dx.doi.org/10.1016/j.microrel.2015.10.022.

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Chatterjee, A. "Concurrent error detection and fault-tolerance in linear analog circuits using continuous checksums." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1, no. 2 (June 1993): 138–50. http://dx.doi.org/10.1109/92.238422.

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Deveautour, B., A. Virazel, P. Girard, and V. Gherman. "On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits." Journal of Electronic Testing 36, no. 1 (January 23, 2020): 33–46. http://dx.doi.org/10.1007/s10836-020-05858-5.

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Leu, Jai-Houng, Jung-Kang Sun, Ho-Sheng Chen, Chong-Lin Huang, Dong-Kai Qiao, Tian-Syung Lan, Yu-Chih Chen, and Ay Su. "Design of a Cryptographic System for Communication Security using Chaotic Signals." Mathematical Problems in Engineering 2021 (May 26, 2021): 1–7. http://dx.doi.org/10.1155/2021/5585079.

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Disturbance or corresponding errors of the transmission of information affect the ability of error detection. The chaotic encryption system prevents errors and secures the transmission system safely. The security assures by updating chaotic signals with the parameters of the chaotic circuits which are frequently changed. The data decipher and the encryption by the chaotic signaling system renews and changes the initial condition of a chaotic electric circuit. When most of the decimal portions are less than the threshold, the transmission is accepted, and all the noninteger numbers are rounded to their nearest integers. The criterion allows the error-detection function in the security system that is proposed in this paper. The chaotic encryption system for information is applied to public channels by the authorized individual. Three pictorial examples transmitted in the proposed system successfully demonstrate the security and performance. The new system provides high efficiency in the satellite communication network.

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Sapozhnikov, Valeriy, Vladimir Sapozhnikov, Dmitriy Efanov, and Dmitriy Pyvovarov. "Application of constant-weight code "1-out-if-5" for the organization of combinational circuits check." Proceedings of Petersburg Transport University, no. 2 (June 20, 2017): 307–19. http://dx.doi.org/10.20295/1815-588x-2017-2-307-319.

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Objective: To study specificities of “1-out of-5”equilibrium code application in the process of concurrent error detection of combinational logic circuits organization. Methods: Information and coding theories, as well as technical diagnostics of discrete systems were applied. Results: It was suggested to apply a “1-out of-5”equilibrium code in organizing of combinational circuits control by means of Boolean complement method, the tester of which has a simple structure and needs five testing patterns for its full check. The calculation method of Boolean complement functions was given; the former makes it possible to provide testability of a Boolean complement block and a tester within a checking circuit. The advantages of a “1-out of-5”equilibrium code application were presented, compared to the usage of other equilibrium codes with a shorter length of a code word for organization of combinational circuits’ check. Practical importance: The application of a “1-out of-5”equilibrium code for organization of combinational circuits’ check is promising for self-checking discrete automatic and calculating machines.

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Alnajjar, Dawood, Yukio Mitsuyama, Masanori Hashimoto, and Takao Onoye. "PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices." IEICE Electronics Express 10, no. 5 (2013): 20130081. http://dx.doi.org/10.1587/elex.10.20130081.

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Efanov, D. V., G. M. Groshev, and O. B. Malikov. "Ways to set up a concurrent error detection system for logical circuits without memory." Russian Electrical Engineering 87, no. 5 (May 2016): 286–88. http://dx.doi.org/10.3103/s1068371216050060.

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Efanov, D. V., V. V. Sapozhnikov, and Vl V. Sapozhnikov. "Applications of modular summation codes to concurrent error detection systems for combinational boolean circuits." Automation and Remote Control 76, no. 10 (October 2015): 1834–48. http://dx.doi.org/10.1134/s0005117915100112.

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V.V., Sapozhnikov, Sapozhnikov Vl.V., and Efanov D.V. "Modified codes with weighted-transitions summation in concurrent error detection systems of combinational circuits." Proceedings of the Institute for System Programming of the RAS 29, no. 5 (2017): 39–60. http://dx.doi.org/10.15514/ispras-2017-29(5)-3.

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Demirtas, Mehmet, Mehmet Akif Erismis, and Salih Gunes. "A Lossy Capacitance Measurement Circuit Based on Analog Lock-in Detection." Elektronika ir Elektrotechnika 26, no. 5 (October 27, 2020): 4–10. http://dx.doi.org/10.5755/j01.eie.26.5.25809.

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This paper presents a lossy capacitance measuring circuit which is based on analog lock-in detection technique. Lossy capacitance can be modelled as a pure capacitor connected in parallel with a resistor. The measurement circuit mechanism consists of an excitation signal to drive the lossy capacitance, a transimpedance amplifier to produce a voltage, and a lock-in detection circuit to extract lossy values of capacitance. The lock-in detector multiplies its input with a square wave using switches and filters out high frequencies to give a DC output that is actually in proportional to the measured values. A field programmable gate array is employed to generate direct digital synthesis based sinusoidal excitation signal to generate reference signals required for demodulation and to measure the output of lock-in detection. The phase shift between the excitation signal and reference signals is controlled accurately in digital domain. Thus, due to the phase mismatch, errors are properly reduced. Also, analog phase shifter and analog switch-driving circuits are no longer required. Three different lossy capacitors realized using discrete components are simulated and tested. The maximum relative error is 1.62 % for the resistance measurement and 6.38 % for the capacitance measurement.

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Poorhosseini, Mehrdad, and Ali Reza Hejazi. "A Fault-Tolerant and Efficient XOR Structure for Modular Design of Complex QCA Circuits." Journal of Circuits, Systems and Computers 27, no. 07 (March 26, 2018): 1850115. http://dx.doi.org/10.1142/s0218126618501153.

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Despite its important existing challenges, quantum-dot cellular automata (QCA) is one of the promising replacement candidates of the traditional VLSI technology. Practical implementation issues such as fault tolerance and lack of customized CAD tools and algorithms for automatic synthesis of large complex systems are some important instances of QCA circuit design challenges. Currently, most of the research papers focus only on development of individually efficient QCA gates and circuits in terms of only their physical properties such as area and delay. However, throughout this paper, it is demonstrated that these compressed and fast individual QCA gates and circuits cause serious concerns when they are exploited as building blocks in modular design of higher level complex circuits. Some simple but effective design rules are then emphasized to solve this problem by preserving the “modular design efficiency” of the developed underlying QCA gates and circuits. As a case study, two new instances of fault-tolerant QCA XOR gates are introduced which are designed by simultaneously considering both area/delay and modular design efficiency rules. A wide range of numerical experiments are provided throughout the paper to prove the priority of the proposed gates with respect to eight other samples of the most efficient existing XOR structures, when exploiting them to build more complex circuits such as adders and error detection/correction circuits.

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Liu, Zilong, Xiaosuo Wu, Huifu Xiao, Xu Han, Wenping Chen, Miaomiao Liao, Ting Zhao, Hao Jia, Jianhong Yang, and Yonghui Tian. "On-chip optical parity checker using silicon photonic integrated circuits." Nanophotonics 7, no. 12 (October 30, 2018): 1939–48. http://dx.doi.org/10.1515/nanoph-2018-0140.

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AbstractThe optical parity checker plays an important role in error detection and correction for high-speed, large-capacity, complex digital optical communication networks, which can be employed to detect and correct the error bits by using a specific coding theory such as introducing error-detecting and correcting codes in communication channels. In this paper, we report an integrated silicon photonic circuit that is capable of implementing the parity checking for binary string with an arbitrary number of bits. The proposed parity checker consisting of parallel cascaded N micro-ring resonators (MRRs) is based on directed logic scheme, which means that the operands applied to MRRs to control the switching states of the MRRs are electrical signals, the operation signals are optical signals, and the final operation results are obtained at the output ports in the form of light. A 3-bit parity checker with an operation speed of 10 kbps, fabricated on a silicon-on-insulator (SOI) platform using a standard commercial complementary metal-oxide-semiconductor (CMOS) process, was experimentally and successfully demonstrated.

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JUNG, YUNHO, SEONGJOO LEE, and JAESEOK KIM. "DESIGN AND IMPLEMENTATION OF SYMBOL DETECTOR FOR MIMO SPATIAL MULTIPLEXING SYSTEMS." Journal of Circuits, Systems and Computers 20, no. 04 (June 2011): 727–39. http://dx.doi.org/10.1142/s0218126611007578.

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In this paper, we propose an efficient symbol detection algorithm for multiple-input multiple-output spatial multiplexing (MIMO-SM) systems and present its design and implementation results. By enhancing the error performance of the first detected symbol that causes error propagation, the proposed algorithm achieves a considerable performance gain compared with the conventional sorted QR decomposition (SQRD) based detection and the ordered successive detection (OSD) algorithms. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by a simulation. In the case of a 16QAM MIMO-SM system with 4 transmit and 4 receive (4 × 4) antennas, at BER = 10-3 the proposed algorithm results in a gain improvement of about 2.5–13.5 dB over the previous algorithms. The proposed detection algorithm was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18 μm 1.8 V CMOS standard cell library. The results show that the proposed algorithm can be implemented without increasing the hardware costs significantly.

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Aliferis, P., D. Gottesman, and J. Preskill. "Accuracy threshold for postselected quantum computation." Quantum Information and Computation 8, no. 3&4 (March 2008): 181–244. http://dx.doi.org/10.26421/qic8.3-4-1.

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We prove an accuracy threshold theorem for fault-tolerant quantum computation based on error detection and postselection. Our proof provides a rigorous foundation for the scheme suggested by Knill, in which preparation circuits for ancilla states are protected by a concatenated error-detecting code and the preparation is aborted if an error is detected. The proof applies to independent stochastic noise but (in contrast to proofs of the quantum accuracy threshold theorem based on concatenated error-correcting codes) not to strongly-correlated adversarial noise. Our rigorously established lower bound on the accuracy threshold, $1.04\times 10^{-3}$, is well below Knill's numerical estimates.

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Rejimon, T., and S. Bhanja. "Time and space efficient method for accurate computation of error detection probabilities in VLSI circuits." IEE Proceedings - Computers and Digital Techniques 152, no. 5 (2005): 679. http://dx.doi.org/10.1049/ip-cdt:20045106.

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Sapozhnikov, Valery V., Vladimir V. Sapozhnikov, Dmitry V. Efanov, and Dmitry V. Pivovarov. "Synthesis of concurrent error detection systems of multioutput combinational circuits based on Boolean complement method." Vestnik Tomskogo gosudarstvennogo universiteta. Upravlenie, vychislitel'naya tekhnika i informatika, no. 41 (December 1, 2017): 69–80. http://dx.doi.org/10.17223/19988605/41/9.

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Lee, Jae, and Seon-Hwan Hwang. "DC Offset Error Compensation Algorithm for PR Current Control of a Single-Phase Grid-Tied Inverter." Energies 11, no. 9 (September 2, 2018): 2308. http://dx.doi.org/10.3390/en11092308.

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In a single-phase grid-tied inverter, the direct current (DC) offset error included in the measured grid side phase current has various causes, such as a non-ideal current sensor, unbalanced power supply of an operational amplifier, and nonlinear features of analog components in interface circuits, etc. If the DC offset error is included in the measured current, it causes the secondary harmonic of fundamental frequency and the DC component in grid phase current which result in degradation of inverter performance. In this paper, a theoretical detection method of the secondary harmonic of the fundamental frequency and a DC component in grid phase current for a proportional-resonant (PR) current control system is introduced. Based on the detection method, an algorithm for compensating DC offset error is also presented for single-phase grid-tied inverters. Simulation results and experimental verification of the DC offset error compensation algorithm are shown in this paper.

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Han, Guo Hui, and Tie Lin Shi. "Force Acquisition for Impact Tester." Applied Mechanics and Materials 716-717 (December 2014): 1026–33. http://dx.doi.org/10.4028/www.scientific.net/amm.716-717.1026.

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A force acquisition system for digital impact tester was investigated, in which structural design of bar-shaped elastic element, circuit design as well as static analysis were involved. Based on analysis of international requirements on the detection precision of digital impact tester, information concerning the precision of sensor parameters, sensors and adhesive was collected, and adhesion sites were settled through finite element analysis and optimization. Circuit design involved zero setting, temperature compensation, amplifying circuit, filter circuit and circuits to connect host computer. Loading calibration test was performed on sensors under static working condition. According to partial authoritative examination, the linearity was 0.06%, the repetitiveness was 0.01%, the retardation was 0.08%, and the sensitivity was 1.112. According to the examination conducted in some metrology institute, the total work error of impact in a digital impact tester adopting the above force acquisition system was 2% of the impact value of a standard specimen, which has already reached the precision level and met the design requirement..

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Moezi, Alireza, and Seyed Mohamad Kargar. "Fault isolation of analog circuit using an optimized ensemble empirical mode decomposition approach based on multi-objective optimization." Proceedings of the Institution of Mechanical Engineers, Part I: Journal of Systems and Control Engineering 235, no. 9 (June 3, 2021): 1555–70. http://dx.doi.org/10.1177/09596518211020534.

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This article proposed a practical approach to isolating faults in analog circuits. The contribution of this article is twofold. First, the optimized empirical mode decomposition approach is presented based on the Hellinger distance such that there is a minimum dependency between intrinsic mode functions. Features with high distinction could be extracted by employing intrinsic mode functions in fault detection problem of analog benchmark circuits. Second, the non-dominated sorting genetic algorithm is employed to retain excellent features and speed up the execution, resulting in the high accuracy of fault detection and isolation. The number of features and mean squared error are selected as objective functions. The features from the data are also extracted using the fast Fourier and wavelet transforms for comparison. Finally, the support vector machine and artificial neural network are employed to isolate faults. Two circuits under test are simulated, and the output signals of the faulty and fault-free circuits are extracted by the Monte Carlo analysis. According to the obtained simulation results, the proposed method with a low-dimensional feature vector outperformed the previous methods, and the computational time has also reduced significantly.

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Hu, Hongzhi, Shulin Tian, and Qing Guo. "Fault Modeling and Testing for Analog Circuits in Complex Space Based on Supply Current and Output Voltage." Journal of Applied Mathematics 2015 (2015): 1–9. http://dx.doi.org/10.1155/2015/851837.

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This paper deals with the modeling of fault for analog circuits. A two-dimensional (2D) fault model is first proposed based on collaborative analysis of supply current and output voltage. This model is a family of circle loci on the complex plane, and it simplifies greatly the algorithms for test point selection and potential fault simulations, which are primary difficulties in fault diagnosis of analog circuits. Furthermore, in order to reduce the difficulty of fault location, an improved fault model in three-dimensional (3D) complex space is proposed, which achieves a far better fault detection ratio (FDR) against measurement error and parametric tolerance. To address the problem of fault masking in both 2D and 3D fault models, this paper proposes an effective design for testability (DFT) method. By adding redundant bypassing-components in the circuit under test (CUT), this method achieves excellent fault isolation ratio (FIR) in ambiguity group isolation. The efficacy of the proposed model and testing method is validated through experimental results provided in this paper.

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Liao, Zhi Rong, Liang Zhou, D. Gao, X. L. Zhang, and M. L. Yin. "Research of Detection and Control System for Lunar Dust Effects Simulator." Advanced Materials Research 426 (January 2012): 126–30. http://dx.doi.org/10.4028/www.scientific.net/amr.426.126.

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To simluate the effects of lunar dust environment veritably by using lunar dust effects simulator, a detection and control system based on singlechip microcomputer was developed. In this system, peripheral circuits with stepper motor driver, temperature sensor and rotary transformer were used to collect the signals and control the temperature as well as speed. Stepper motor speed up/down curve, digital convolution filter and error compensation were adhibited for improving the system accuracy. The results showed that this method was simple, reliable and had high control accuracy.

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Efanov, D. V., G. V. Osadchiy, and M. V. Zueva. "THE CHARACTERISTICS OF ERROR DETECTION BY CODES WITH THE SUMMATION OF SINGLE INFORMATION BITS IN THE RING OF RESIDUES, ACCORDING TO A GIVEN MODULUS ARE ANALYZED, WHICH ARE MANIFESTED IN THE SYNTHESIS OF BUILT-IN CONTROL CIRCUITS USING THE BOOLEAN COMPLEMENT METHOD." Automation on Transport 7, no. 2 (June 2021): 284–314. http://dx.doi.org/10.20295/2412-9186-2021-7-2-284-314.

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Errors occurring in the control vectors are always detected. Unlike previous studies in this subject area, the authors focus on the features of error detection by modular sum codes in all codewords, and not just in information vectors. Previously unknown properties of error detection by modular sum- mation codes with their classification by types (unidirectional, symmetrical and asymmetrical errors) and multiplicities have been established. Catalogs of detailed characteristics of modular sum codes are provided. The key patterns inherent in this class of codes are described. The research results can be used in organizing built-in control circuits using the Boolean complement method, in solving other problems of technical diagnostics, where it is important to know the properties of detecting errors in code words, as well as problems of data protection and transmission

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Reinoso Chisaguano, Diego Javier, and Minoru Okada. "Low Complexity Submatrix Divided MMSE Sparse-SQRD Detection for MIMO-OFDM with ESPAR Antenna Receiver." VLSI Design 2013 (April 30, 2013): 1–11. http://dx.doi.org/10.1155/2013/206909.

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Multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) with an electronically steerable passive array radiator (ESPAR) antenna receiver can improve the bit error rate performance and obtains additional diversity gain without increasing the number of Radio Frequency (RF) front-end circuits. However, due to the large size of the channel matrix, the computational cost required for the detection process using Vertical-Bell Laboratories Layered Space-Time (V-BLAST) detection is too high to be implemented. Using the minimum mean square error sparse-sorted QR decomposition (MMSE sparse-SQRD) algorithm for the detection process the average computational cost can be considerably reduced but is still higher compared with a conventional MIMOOFDM system without ESPAR antenna receiver. In this paper, we propose to use a low complexity submatrix divided MMSE sparse-SQRD algorithm for the detection process of MIMOOFDM with ESPAR antenna receiver. The computational cost analysis and simulation results show that on average the proposed scheme can further reduce the computational cost and achieve a complexity comparable to the conventional MIMO-OFDM detection schemes.

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Heinssen, Sascha, Theodor Hillebrand, Maike Taddiken, Steffen Paul, and Dagmar Peters-Drolshagen. "On-Line Error Correction in Sensor Interface Circuits by Using Adaptive Filtering and Digital Calibration." Proceedings 2, no. 13 (November 30, 2018): 963. http://dx.doi.org/10.3390/proceedings2130963.

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Numerous non-ideal effects can distort the functionality of sensor interfaces and have to be considered during the design phase. In order to relax the requirements for the analog circuit components, adaptive filtering and digital calibration are used in this work to detect and correct different gain- and offset-errors. The error detection is performed by transmitting a test signal through the sensor interface continuously and in parallel to the sensor signal. In the digital domain, variations of the test signal are evaluated and present errors can be determined and eliminated. In this way, an on-line error correction is realized, which makes the sensor interface more robust against static and dynamic non-idealities. The proposed concept is demonstrated by correcting different gain- and offset-errors in a 65nm CMOS sensor interface.

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Chapuis, Robert P., and Louis Sabourin. "Effects of installation of piezometers and wells on groundwater characteristics and measurements." Canadian Geotechnical Journal 26, no. 4 (November 1, 1989): 604–13. http://dx.doi.org/10.1139/t89-073.

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The results of a variable-head permeability test can be used to check whether a piezometer or sampling well has been successfully sealed in the soil and to detect hydraulic short circuits and possible cross-contamination between aquifers. An improper seal is a well-known cause of hydraulic short circuit. In some instances, also, although the tubing has been sealed over its full length, the water level in the pipe is not representative of the actual piezometric head. An example shows that the values of hydraulic conductivity determined using several test methods varied in a 1:6 ratio before detection of a piezometric error. The resulting correction reduced the variation in k to ± 12%. The causes of hydraulic short circuits have been investigated using computer simulations. It has been concluded that large errors recorded in the field are due to internal erosion of natural soils around the casing during drilling operations or development. The hydraulic damage to soils is documented. An analytical solution has been written for a simple case of hydraulic short circuit. Its theoretical predictions confirm the validity of the computer simulation. In light of experience, recommendations are proposed to reduce hydraulic damage, therefore improving the reliability of piezometric measurements and representativeness of groundwater samples. Key words: permeability, field test, piezometer, sealing, drilling, water level.

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Haghparast, Majid, and Soghra Shoaei. "Design of a New Parity Preserving Reversible Full Adder." Journal of Circuits, Systems and Computers 24, no. 01 (November 10, 2014): 1550006. http://dx.doi.org/10.1142/s0218126615500061.

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Power dissipation is one of the important issues in VLSI design. Reversible logic has zero power dissipation; therefore, nowadays, researchers attend to it in order to optimize the internal power consumption. On the other hand, fault tolerance is a solution for error detection in digital systems. In many systems, fault tolerance is achieved by parity checking. This article proposes a new parity-preserving reversible full adder circuit. For many years, researchers assumed that the quantum cost (QC) of the parity-preserving reversible full adder is 11. In this article we offered a new parity-preserving reversible full adder circuit with a QC of only 9. In addition, the proposed parity-preserving reversible full adder has optimum number of constant inputs and garbage outputs. A novel parity-preserving reversible 4:2 compressor circuit is also proposed using the proposed parity-preserving reversible full adder. This article would be a great initiation for building more complex parity-preserving reversible circuits. All the scales are in the nanometric area, and their fundamental parts are no bigger than a few nanometers.

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Journal articles on the topic 'Error-Detection Circuits'

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